blob: 1971bc94f7d3c2e2bfe5afffd13401278687c512 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Hao Zhangc13cbcf2014-10-22 16:32:33 +03002/*
3 * K2L EVM : Board initialization
4 *
5 * (C) Copyright 2014
6 * Texas Instruments Incorporated, <www.ti.com>
Hao Zhangc13cbcf2014-10-22 16:32:33 +03007 */
8
Simon Glass2dc9c342020-05-10 11:40:01 -06009#include <image.h>
Simon Glass97589732020-05-10 11:40:02 -060010#include <init.h>
Hao Zhangc13cbcf2014-10-22 16:32:33 +030011#include <asm/arch/ddr3.h>
12#include <asm/arch/hardware.h>
Hao Zhang7874b8a2014-10-29 13:09:34 +020013#include <asm/ti-common/keystone_net.h>
Hao Zhangc13cbcf2014-10-22 16:32:33 +030014
Lokesh Vutlaa9a0e122017-05-03 16:58:26 +053015unsigned int get_external_clk(u32 clk)
16{
17 unsigned int clk_freq;
18
19 switch (clk) {
20 case sys_clk:
21 clk_freq = 122880000;
22 break;
23 case alt_core_clk:
24 clk_freq = 100000000;
25 break;
26 case pa_clk:
27 clk_freq = 122880000;
28 break;
29 case tetris_clk:
30 clk_freq = 122880000;
31 break;
32 case ddr3a_clk:
33 clk_freq = 100000000;
34 break;
35 default:
36 clk_freq = 0;
37 break;
38 }
39
40 return clk_freq;
41}
Hao Zhangc13cbcf2014-10-22 16:32:33 +030042
Lokesh Vutla9da9afa2015-07-28 14:16:44 +053043static struct pll_init_data core_pll_config[NUM_SPDS] = {
44 [SPD800] = CORE_PLL_799,
45 [SPD1000] = CORE_PLL_1000,
Lokesh Vutlab4a96bd2015-08-17 19:58:34 +053046 [SPD1200] = CORE_PLL_1198,
Hao Zhangc13cbcf2014-10-22 16:32:33 +030047};
48
Lokesh Vutla70438fc2015-07-28 14:16:43 +053049s16 divn_val[16] = {
50 0, 0, 1, 4, 23, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
51};
52
Hao Zhangc13cbcf2014-10-22 16:32:33 +030053static struct pll_init_data tetris_pll_config[] = {
Lokesh Vutla9da9afa2015-07-28 14:16:44 +053054 [SPD800] = TETRIS_PLL_799,
55 [SPD1000] = TETRIS_PLL_1000,
56 [SPD1200] = TETRIS_PLL_1198,
57 [SPD1350] = TETRIS_PLL_1352,
58 [SPD1400] = TETRIS_PLL_1401,
Hao Zhangc13cbcf2014-10-22 16:32:33 +030059};
60
61static struct pll_init_data pa_pll_config =
62 PASS_PLL_983;
63
Lokesh Vutla79a94a22015-07-28 14:16:46 +053064struct pll_init_data *get_pll_init_data(int pll)
65{
66 int speed;
67 struct pll_init_data *data;
68
69 switch (pll) {
70 case MAIN_PLL:
Lokesh Vutlab35410e2016-03-04 10:36:40 -060071 speed = get_max_dev_speed(speeds);
Lokesh Vutla79a94a22015-07-28 14:16:46 +053072 data = &core_pll_config[speed];
73 break;
74 case TETRIS_PLL:
Lokesh Vutlab35410e2016-03-04 10:36:40 -060075 speed = get_max_arm_speed(speeds);
Lokesh Vutla79a94a22015-07-28 14:16:46 +053076 data = &tetris_pll_config[speed];
77 break;
78 case PASS_PLL:
79 data = &pa_pll_config;
80 break;
81 default:
82 data = NULL;
83 }
84
85 return data;
86}
87
Hao Zhangc13cbcf2014-10-22 16:32:33 +030088#ifdef CONFIG_BOARD_EARLY_INIT_F
89int board_early_init_f(void)
90{
Lokesh Vutla79a94a22015-07-28 14:16:46 +053091 init_plls();
Hao Zhangc13cbcf2014-10-22 16:32:33 +030092
93 return 0;
94}
95#endif
96
Jean-Jacques Hiblot2037fa42017-09-15 12:57:24 +020097#if defined(CONFIG_MULTI_DTB_FIT)
Cooper Jr., Franklin43ff2242017-06-16 17:25:16 -050098int board_fit_config_name_match(const char *name)
99{
100 if (!strcmp(name, "keystone-k2l-evm"))
101 return 0;
102
103 return -1;
104}
105#endif
106
Hao Zhangc13cbcf2014-10-22 16:32:33 +0300107#ifdef CONFIG_SPL_BUILD
Hao Zhangc13cbcf2014-10-22 16:32:33 +0300108void spl_init_keystone_plls(void)
109{
Lokesh Vutla79a94a22015-07-28 14:16:46 +0530110 init_plls();
Hao Zhangc13cbcf2014-10-22 16:32:33 +0300111}
112#endif