dts/upstream/Bindings/media/nxp,imx8-isi.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/nxp,imx8-isi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: i.MX8 Image Sensing Interface

maintainers:
  - Laurent Pinchart <laurent.pinchart@ideasonboard.com>

description: |
  The Image Sensing Interface (ISI) combines image processing pipelines with
  DMA engines to process and capture frames originating from a variety of
  sources. The inputs to the ISI go through Pixel Link interfaces, and their
  number and nature is SoC-dependent. They cover both capture interfaces (MIPI
  CSI-2 RX, HDMI RX, ...) and display engine outputs for writeback support.

properties:
  compatible:
    enum:
      - fsl,imx8mn-isi
      - fsl,imx8mp-isi
      - fsl,imx93-isi

  reg:
    maxItems: 1

  clocks:
    items:
      - description: The AXI clock
      - description: The APB clock
      # TODO: Check if the per-channel ipg_proc_clk clocks need to be specified
      # as well, in case some SoCs have the ability to control them separately.
      # This may be the case of the i.MX8[DQ]X(P)

  clock-names:
    items:
      - const: axi
      - const: apb

  fsl,blk-ctrl:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      A phandle referencing the block control that contains the CSIS to ISI
      gasket.

  interrupts:
    description: Processing pipeline interrupts, one per pipeline
    minItems: 1
    maxItems: 2

  power-domains:
    maxItems: 1

  ports:
    $ref: /schemas/graph.yaml#/properties/ports
    description: |
      Ports represent the Pixel Link inputs to the ISI. Their number and
      assignment are model-dependent. Each port shall have a single endpoint.

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - fsl,blk-ctrl
  - ports

allOf:
  - if:
      properties:
        compatible:
          contains:
            enum:
              - fsl,imx8mn-isi
              - fsl,imx93-isi
    then:
      properties:
        interrupts:
          maxItems: 1
        ports:
          properties:
            port@0:
              description: MIPI CSI-2 RX
            port@1: false
          required:
            - port@0

  - if:
      properties:
        compatible:
          contains:
            const: fsl,imx8mp-isi
    then:
      properties:
        interrupts:
          maxItems: 2
        ports:
          properties:
            port@0:
              description: MIPI CSI-2 RX 0
            port@1:
              description: MIPI CSI-2 RX 1
          required:
            - port@0
            - port@1

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/imx8mn-clock.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/power/imx8mn-power.h>

    isi@32e20000 {
        compatible = "fsl,imx8mn-isi";
        reg = <0x32e20000 0x100>;
        interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
                 <&clk IMX8MN_CLK_DISP_APB_ROOT>;
        clock-names = "axi", "apb";
        fsl,blk-ctrl = <&disp_blk_ctrl>;
        power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_ISI>;

        ports {
            #address-cells = <1>;
            #size-cells = <0>;

            port@0 {
                reg = <0>;
                isi_in: endpoint {
                    remote-endpoint = <&mipi_csi_out>;
                };
            };
        };
    };

  - |
    #include <dt-bindings/clock/imx8mp-clock.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>

    isi@32e00000 {
        compatible = "fsl,imx8mp-isi";
        reg = <0x32e00000 0x4000>;
        interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
                 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
        clock-names = "axi", "apb";
        fsl,blk-ctrl = <&media_blk_ctrl>;
        power-domains = <&mediamix_pd>;

        ports {
            #address-cells = <1>;
            #size-cells = <0>;

            port@0 {
                reg = <0>;
                isi_in_0: endpoint {
                    remote-endpoint = <&mipi_csi_0_out>;
                };
            };

            port@1 {
                reg = <1>;
                isi_in_1: endpoint {
                    remote-endpoint = <&mipi_csi_1_out>;
                };
            };
        };
    };
...