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git01.mediatek.com / filogic / uboot / 204f3dc486f2e7c0bd43f2d21e2beb718e0ca699 / . / arch / sandbox / dts / sandbox64.dts
blob: a39f94feec0cd046ebf4f3d99ed0923b06ac1810 [file] [log] [blame]
Mario Six61efece2018-02-12 08:05:57 +0100[diff] [blame]1/dts-v1/;
2
Simon Glass07bb5e72019-05-18 11:59:48 -0600[diff] [blame]3#include <config.h>
4
Mario Six61efece2018-02-12 08:05:57 +0100[diff] [blame]5/ {
6 #address-cells = <2>;
7 #size-cells = <2>;
8 model = "sandbox";
Heinrich Schuchardtdeaf2972019-11-09 09:39:01 +0100[diff] [blame]9 compatible = "sandbox";
Mario Six61efece2018-02-12 08:05:57 +0100[diff] [blame]10
11 aliases {
Mario Six61efece2018-02-12 08:05:57 +0100[diff] [blame]12 i2c0 = &i2c_0;
Tom Rini4a3ca482020-02-11 12:41:23 -0500[diff] [blame]13 pci0 = &pcic;
Mario Six61efece2018-02-12 08:05:57 +0100[diff] [blame]14 rtc0 = &rtc_0;
Simon Glass8964f862019-05-18 11:59:40 -0600[diff] [blame]15 axi0 = &axi;
Simon Glassed3698a2019-05-18 11:59:42 -0600[diff] [blame]16 spi0 = &spi;
Mario Six61efece2018-02-12 08:05:57 +0100[diff] [blame]17 };
18
Simon Glass07bb5e72019-05-18 11:59:48 -0600[diff] [blame]19 memory {
20 reg = /bits/ 64 <0 CONFIG_SYS_SDRAM_SIZE>;
21 };
22
Heinrich Schuchardtad935702020-03-14 12:13:39 +0100[diff] [blame]23 reserved-memory {
24 #address-cells = <2>;
25 #size-cells = <2>;
26 ranges;
27
28 reservation_test_size {
29 size = <0 0x4000>;
30 alignment = <0 0x2000>;
31 };
32
33 reservation_test@a000 {
34 reg = <0 0x00d0a000 0 0x2000>;
35 };
36
37 reservation_test@7000 {
38 reg = <0 0x00d07000 0 0x1000>;
39 };
40 };
41
42 /* ... */
Simon Glass699c9ca2018-10-01 12:22:08 -0600[diff] [blame]43 cros_ec: cros-ec {
Mario Six61efece2018-02-12 08:05:57 +0100[diff] [blame]44 reg = <0 0 0 0>;
Simon Glass8964f862019-05-18 11:59:40 -0600[diff] [blame]45 u-boot,dm-pre-reloc;
Mario Six61efece2018-02-12 08:05:57 +0100[diff] [blame]46 compatible = "google,cros-ec-sandbox";
Mario Six61efece2018-02-12 08:05:57 +0100[diff] [blame]47 };
48
Joe Hershberger89590c82018-07-02 14:47:54 -0500[diff] [blame]49 ethrawbus {
50 compatible = "sandbox,eth-raw-bus";
51 skip-localhost = <1>;
52 };
53
Mario Six61efece2018-02-12 08:05:57 +0100[diff] [blame]54 eth@10002000 {
55 compatible = "sandbox,eth";
56 reg = <0x0 0x10002000 0x0 0x1000>;
57 fake-host-hwaddr = [00 00 66 44 22 00];
58 };
59
Mario Six61efece2018-02-12 08:05:57 +0100[diff] [blame]60 i2c_0: i2c@0 {
61 #address-cells = <1>;
62 #size-cells = <0>;
63 reg = <0 0 0 0>;
64 compatible = "sandbox,i2c";
65 clock-frequency = <400000>;
66 pinctrl-names = "default";
67 pinctrl-0 = <&pinctrl_i2c0>;
Mario Six61efece2018-02-12 08:05:57 +0100[diff] [blame]68 };
69
Tom Rini4a3ca482020-02-11 12:41:23 -0500[diff] [blame]70 pcic: pci@0 {
Mario Six61efece2018-02-12 08:05:57 +0100[diff] [blame]71 compatible = "sandbox,pci";
72 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -0500[diff] [blame]73 bus-range = <0x00 0xff>;
Mario Six61efece2018-02-12 08:05:57 +0100[diff] [blame]74 #address-cells = <3>;
75 #size-cells = <2>;
76 ranges = <0x02000000 0 0x10000000 0 0x10000000 0 0x2000
77 0x01000000 0 0x20000000 0 0x20000000 0 0x2000>;
Mario Six61efece2018-02-12 08:05:57 +0100[diff] [blame]78 };
79
Simon Glassed3698a2019-05-18 11:59:42 -0600[diff] [blame]80 spi: spi@0 {
Simon Glass8964f862019-05-18 11:59:40 -0600[diff] [blame]81 u-boot,dm-pre-reloc;
Mario Six61efece2018-02-12 08:05:57 +0100[diff] [blame]82 #address-cells = <1>;
83 #size-cells = <0>;
84 reg = <0 0 0 0>;
85 compatible = "sandbox,spi";
86 cs-gpios = <0>, <&gpio_a 0>;
Mario Six61efece2018-02-12 08:05:57 +0100[diff] [blame]87 };
88
Mario Six61efece2018-02-12 08:05:57 +0100[diff] [blame]89};
90
Simon Glass28db4692019-05-18 11:59:41 -0600[diff] [blame]91#include "sandbox.dtsi"
Mario Six61efece2018-02-12 08:05:57 +0100[diff] [blame]92#include "cros-ec-keyboard.dtsi"
93#include "sandbox_pmic.dtsi"