| Leo Yu-Chi Liang | 5d0bbea | 2024-05-14 17:50:11 +0800 | [diff] [blame] | 1 | config RISCV_ANDES |
| Bin Meng | 4b284ad | 2018-12-12 06:12:28 -0800 | [diff] [blame] | 2 | bool |
| Rick Chen | 14a1075 | 2019-04-02 15:56:41 +0800 | [diff] [blame] | 3 | select ARCH_EARLY_INIT_R |
| Yu Chien Peter Lin | 9ae964b | 2024-04-11 17:29:45 +0800 | [diff] [blame] | 4 | select SYS_CACHE_SHIFT_6 |
| Rick Chen | 14a1075 | 2019-04-02 15:56:41 +0800 | [diff] [blame] | 5 | imply CPU |
| 6 | imply CPU_RISCV |
| Sean Anderson | 9baaaef | 2020-09-28 10:52:21 -0400 | [diff] [blame] | 7 | imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE) |
| Yu Chien Peter Lin | ac5e68f | 2023-09-29 12:03:07 +0800 | [diff] [blame] | 8 | imply ANDES_PLMT_TIMER |
| 9 | imply SPL_ANDES_PLMT_TIMER |
| Yu Chien Peter Lin | 739cd6f | 2022-10-25 23:03:50 +0800 | [diff] [blame] | 10 | imply ANDES_PLICSW if (RISCV_MMODE || SPL_RISCV_MMODE) |
| Leo Yu-Chi Liang | 5d0bbea | 2024-05-14 17:50:11 +0800 | [diff] [blame] | 11 | imply ANDES_L2_CACHE |
| Simon Glass | 2f00216 | 2021-03-15 18:11:18 +1300 | [diff] [blame] | 12 | imply SPL_CPU |
| Rick Chen | 276292a | 2019-11-14 13:52:21 +0800 | [diff] [blame] | 13 | imply SPL_OPENSBI |
| 14 | imply SPL_LOAD_FIT |
| Bin Meng | 4b284ad | 2018-12-12 06:12:28 -0800 | [diff] [blame] | 15 | help |
| 16 | Run U-Boot on AndeStar V5 platforms and use some specific features |
| 17 | which are provided by Andes Technology AndeStar V5 families. |