commit 739cd6fb9afd376de1d6825b0835397cae359ea7
author Yu Chien Peter Lin <peterlin@andestech.com> Tue Oct 25 23:03:50 2022 +0800
committer Leo Yu-Chi Liang <ycliang@andestech.com> Thu Nov 03 13:27:56 2022 +0800
tree 74a91e18cd008f381c12d615587912630530bed3
parent 12a195515fc31bc0c61ba40584bd78ce015b631c

riscv: Rename Andes PLIC to PLICSW

As PLICSW is used to trigger the software interrupt, we should rename
Andes PLIC configuration and file name to reflect the usage. This patch
also updates PLMT and PLICSW compatible strings to be consistent with
OpenSBI fdt driver.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>

arch/riscv/cpu/ax25/Kconfig

diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig
index 941d963..4a7295d 100644
--- a/arch/riscv/cpu/ax25/Kconfig
+++ b/arch/riscv/cpu/ax25/Kconfig
@@ -4,7 +4,7 @@
 	imply CPU
 	imply CPU_RISCV
 	imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
-	imply ANDES_PLIC if (RISCV_MMODE || SPL_RISCV_MMODE)
+	imply ANDES_PLICSW if (RISCV_MMODE || SPL_RISCV_MMODE)
 	imply ANDES_PLMT_TIMER if (RISCV_MMODE || SPL_RISCV_MMODE)
 	imply SPL_CPU
 	imply SPL_OPENSBI