blob: 21dcfb2142e4aaf2114cd9768812353b1825ab28 [file] [log] [blame]
Park, Aiden6e3cc362019-08-03 08:30:12 +00001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2019 Intel Corporation <www.intel.com>
4 */
5
6#include <common.h>
Simon Glass1fa70f82019-11-14 12:57:34 -07007#include <cpu_func.h>
Park, Aiden347f1b42019-08-03 08:30:52 +00008#include <asm/arch/slimbootloader.h>
9
10DECLARE_GLOBAL_DATA_PTR;
11
12/**
13 * This sets tsc_base and clock_rate for early_timer and tsc_timer.
14 * The performance info guid hob has all performance timestamp data, but
15 * the only tsc frequency info is used for the timer driver for now.
16 *
17 * Slim Bootloader already calibrated TSC and provides it to U-Boot.
18 * Therefore, U-Boot does not have to re-calibrate TSC.
19 * Configuring tsc_base and clock_rate here makes x86 tsc_timer driver
20 * bypass TSC calibration and use the provided TSC frequency.
21 */
22static void tsc_init(void)
23{
24 struct sbl_performance_info *data;
25 const efi_guid_t guid = SBL_PERFORMANCE_INFO_GUID;
26
27 if (!gd->arch.hob_list)
28 panic("hob list not found!");
29
30 gd->arch.tsc_base = rdtsc();
31 debug("tsc_base=0x%llx\n", gd->arch.tsc_base);
32
33 data = hob_get_guid_hob_data(gd->arch.hob_list, NULL, &guid);
34 if (!data) {
35 debug("performance info hob not found\n");
36 return;
37 }
38
39 /* frequency is in KHz, so to Hz */
40 gd->arch.clock_rate = data->frequency * 1000;
41 debug("freq=0x%lx\n", gd->arch.clock_rate);
42}
Park, Aiden6e3cc362019-08-03 08:30:12 +000043
44int arch_cpu_init(void)
45{
Park, Aiden347f1b42019-08-03 08:30:52 +000046 tsc_init();
47
Park, Aiden6e3cc362019-08-03 08:30:12 +000048 return x86_cpu_init_f();
49}
50
51int checkcpu(void)
52{
53 return 0;
54}
55
56int print_cpuinfo(void)
57{
58 return default_print_cpuinfo();
59}