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Park, Aiden6e3cc362019-08-03 08:30:12 +00001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2019 Intel Corporation <www.intel.com>
4 */
5
6#include <common.h>
Park, Aiden347f1b42019-08-03 08:30:52 +00007#include <asm/arch/slimbootloader.h>
8
9DECLARE_GLOBAL_DATA_PTR;
10
11/**
12 * This sets tsc_base and clock_rate for early_timer and tsc_timer.
13 * The performance info guid hob has all performance timestamp data, but
14 * the only tsc frequency info is used for the timer driver for now.
15 *
16 * Slim Bootloader already calibrated TSC and provides it to U-Boot.
17 * Therefore, U-Boot does not have to re-calibrate TSC.
18 * Configuring tsc_base and clock_rate here makes x86 tsc_timer driver
19 * bypass TSC calibration and use the provided TSC frequency.
20 */
21static void tsc_init(void)
22{
23 struct sbl_performance_info *data;
24 const efi_guid_t guid = SBL_PERFORMANCE_INFO_GUID;
25
26 if (!gd->arch.hob_list)
27 panic("hob list not found!");
28
29 gd->arch.tsc_base = rdtsc();
30 debug("tsc_base=0x%llx\n", gd->arch.tsc_base);
31
32 data = hob_get_guid_hob_data(gd->arch.hob_list, NULL, &guid);
33 if (!data) {
34 debug("performance info hob not found\n");
35 return;
36 }
37
38 /* frequency is in KHz, so to Hz */
39 gd->arch.clock_rate = data->frequency * 1000;
40 debug("freq=0x%lx\n", gd->arch.clock_rate);
41}
Park, Aiden6e3cc362019-08-03 08:30:12 +000042
43int arch_cpu_init(void)
44{
Park, Aiden347f1b42019-08-03 08:30:52 +000045 tsc_init();
46
Park, Aiden6e3cc362019-08-03 08:30:12 +000047 return x86_cpu_init_f();
48}
49
50int checkcpu(void)
51{
52 return 0;
53}
54
55int print_cpuinfo(void)
56{
57 return default_print_cpuinfo();
58}