Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 1 | /* |
| 2 | * WindRiver SBC8349 U-Boot configuration file. |
| 3 | * Copyright (c) 2006, 2007 Wind River Systems, Inc. |
| 4 | * |
| 5 | * Paul Gortmaker <paul.gortmaker@windriver.com> |
| 6 | * Based on the MPC8349EMDS config. |
| 7 | * |
Wolfgang Denk | bd8ec7e | 2013-10-07 13:07:26 +0200 | [diff] [blame] | 8 | * SPDX-License-Identifier: GPL-2.0+ |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 9 | */ |
| 10 | |
| 11 | /* |
| 12 | * sbc8349 board configuration file. |
| 13 | */ |
| 14 | |
| 15 | #ifndef __CONFIG_H |
| 16 | #define __CONFIG_H |
| 17 | |
Kim Phillips | d2f66b8 | 2015-03-17 12:00:45 -0500 | [diff] [blame] | 18 | #define CONFIG_SYS_GENERIC_BOARD |
| 19 | #define CONFIG_DISPLAY_BOARDINFO |
| 20 | |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 21 | /* |
| 22 | * High Level Configuration Options |
| 23 | */ |
| 24 | #define CONFIG_E300 1 /* E300 Family */ |
Peter Tyser | 72f2d39 | 2009-05-22 17:23:25 -0500 | [diff] [blame] | 25 | #define CONFIG_MPC834x 1 /* MPC834x family */ |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 26 | #define CONFIG_MPC8349 1 /* MPC8349 specific */ |
| 27 | #define CONFIG_SBC8349 1 /* WRS SBC8349 board specific */ |
| 28 | |
Wolfgang Denk | 291ba1b | 2010-10-06 09:05:45 +0200 | [diff] [blame] | 29 | #define CONFIG_SYS_TEXT_BASE 0xFF800000 |
| 30 | |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 31 | /* Don't enable PCI2 on sbc834x - it doesn't exist physically. */ |
| 32 | #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ |
| 33 | |
Paul Gortmaker | 0aaee14 | 2009-08-21 16:21:58 -0500 | [diff] [blame] | 34 | /* |
| 35 | * The default if PCI isn't enabled, or if no PCI clk setting is given |
| 36 | * is 66MHz; this is what the board defaults to when the PCI slot is |
| 37 | * physically empty. The board will automatically (i.e w/o jumpers) |
| 38 | * clock down to 33MHz if you insert a 33MHz PCI card. |
| 39 | */ |
Wolfgang Denk | 291ba1b | 2010-10-06 09:05:45 +0200 | [diff] [blame] | 40 | #ifdef CONFIG_PCI_33M |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 41 | #define CONFIG_83XX_CLKIN 33000000 /* in Hz */ |
Paul Gortmaker | 0aaee14 | 2009-08-21 16:21:58 -0500 | [diff] [blame] | 42 | #else /* 66M */ |
| 43 | #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 44 | #endif |
| 45 | |
| 46 | #ifndef CONFIG_SYS_CLK_FREQ |
Wolfgang Denk | 291ba1b | 2010-10-06 09:05:45 +0200 | [diff] [blame] | 47 | #ifdef CONFIG_PCI_33M |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 48 | #define CONFIG_SYS_CLK_FREQ 33000000 |
| 49 | #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 |
Paul Gortmaker | 0aaee14 | 2009-08-21 16:21:58 -0500 | [diff] [blame] | 50 | #else /* 66M */ |
| 51 | #define CONFIG_SYS_CLK_FREQ 66000000 |
| 52 | #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 53 | #endif |
| 54 | #endif |
| 55 | |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 56 | #undef CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ |
| 57 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 58 | #define CONFIG_SYS_IMMR 0xE0000000 |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 59 | |
Joe Hershberger | 10c2617 | 2011-10-11 23:57:25 -0500 | [diff] [blame] | 60 | #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 61 | #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ |
| 62 | #define CONFIG_SYS_MEMTEST_END 0x00100000 |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 63 | |
| 64 | /* |
| 65 | * DDR Setup |
| 66 | */ |
| 67 | #undef CONFIG_DDR_ECC /* only for ECC DDR module */ |
| 68 | #undef CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ |
| 69 | #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ |
Joe Hershberger | 10c2617 | 2011-10-11 23:57:25 -0500 | [diff] [blame] | 70 | #define CONFIG_SYS_83XX_DDR_USES_CS0 /* WRS; Fsl board uses CS2/CS3 */ |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 71 | |
| 72 | /* |
| 73 | * 32-bit data path mode. |
| 74 | * |
| 75 | * Please note that using this mode for devices with the real density of 64-bit |
| 76 | * effectively reduces the amount of available memory due to the effect of |
| 77 | * wrapping around while translating address to row/columns, for example in the |
| 78 | * 256MB module the upper 128MB get aliased with contents of the lower |
| 79 | * 128MB); normally this define should be used for devices with real 32-bit |
| 80 | * data path. |
| 81 | */ |
| 82 | #undef CONFIG_DDR_32BIT |
| 83 | |
Joe Hershberger | 10c2617 | 2011-10-11 23:57:25 -0500 | [diff] [blame] | 84 | #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 85 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE |
| 86 | #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE |
| 87 | #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 88 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) |
| 89 | #define CONFIG_DDR_2T_TIMING |
| 90 | |
| 91 | #if defined(CONFIG_SPD_EEPROM) |
| 92 | /* |
| 93 | * Determine DDR configuration from I2C interface. |
| 94 | */ |
| 95 | #define SPD_EEPROM_ADDRESS 0x52 /* DDR DIMM */ |
| 96 | |
| 97 | #else |
| 98 | /* |
| 99 | * Manually set up DDR parameters |
| 100 | * NB: manual DDR setup untested on sbc834x |
| 101 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 102 | #define CONFIG_SYS_DDR_SIZE 256 /* MB */ |
Joe Hershberger | 5ade390 | 2011-10-11 23:57:31 -0500 | [diff] [blame] | 103 | #define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \ |
Joe Hershberger | 10c2617 | 2011-10-11 23:57:25 -0500 | [diff] [blame] | 104 | | CSCONFIG_ROW_BIT_13 \ |
| 105 | | CSCONFIG_COL_BIT_10) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 106 | #define CONFIG_SYS_DDR_TIMING_1 0x36332321 |
| 107 | #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ |
Joe Hershberger | 10c2617 | 2011-10-11 23:57:25 -0500 | [diff] [blame] | 108 | #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 109 | #define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */ |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 110 | |
| 111 | #if defined(CONFIG_DDR_32BIT) |
| 112 | /* set burst length to 8 for 32-bit data path */ |
Joe Hershberger | 10c2617 | 2011-10-11 23:57:25 -0500 | [diff] [blame] | 113 | /* DLL,normal,seq,4/2.5, 8 burst len */ |
| 114 | #define CONFIG_SYS_DDR_MODE 0x00000023 |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 115 | #else |
| 116 | /* the default burst length is 4 - for 64-bit data path */ |
Joe Hershberger | 10c2617 | 2011-10-11 23:57:25 -0500 | [diff] [blame] | 117 | /* DLL,normal,seq,4/2.5, 4 burst len */ |
| 118 | #define CONFIG_SYS_DDR_MODE 0x00000022 |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 119 | #endif |
| 120 | #endif |
| 121 | |
| 122 | /* |
| 123 | * SDRAM on the Local Bus |
| 124 | */ |
Joe Hershberger | f05b933 | 2011-10-11 23:57:30 -0500 | [diff] [blame] | 125 | #define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */ |
| 126 | #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 127 | |
| 128 | /* |
| 129 | * FLASH on the Local Bus |
| 130 | */ |
Joe Hershberger | 10c2617 | 2011-10-11 23:57:25 -0500 | [diff] [blame] | 131 | #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ |
| 132 | #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 133 | #define CONFIG_SYS_FLASH_BASE 0xFF800000 /* start of FLASH */ |
| 134 | #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */ |
| 135 | /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 136 | |
Joe Hershberger | f05b933 | 2011-10-11 23:57:30 -0500 | [diff] [blame] | 137 | #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ |
| 138 | | BR_PS_16 /* 16 bit port */ \ |
| 139 | | BR_MS_GPCM /* MSEL = GPCM */ \ |
| 140 | | BR_V) /* valid */ |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 141 | |
Joe Hershberger | f05b933 | 2011-10-11 23:57:30 -0500 | [diff] [blame] | 142 | #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ |
| 143 | | OR_GPCM_XAM \ |
| 144 | | OR_GPCM_CSNT \ |
| 145 | | OR_GPCM_ACS_DIV2 \ |
| 146 | | OR_GPCM_XACS \ |
| 147 | | OR_GPCM_SCY_15 \ |
| 148 | | OR_GPCM_TRLX_SET \ |
| 149 | | OR_GPCM_EHTR_SET \ |
| 150 | | OR_GPCM_EAD) |
| 151 | /* 0xFF806FF7 */ |
| 152 | |
Joe Hershberger | 10c2617 | 2011-10-11 23:57:25 -0500 | [diff] [blame] | 153 | /* window base at flash base */ |
| 154 | #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE |
Joe Hershberger | f05b933 | 2011-10-11 23:57:30 -0500 | [diff] [blame] | 155 | #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB) |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 156 | |
Joe Hershberger | 10c2617 | 2011-10-11 23:57:25 -0500 | [diff] [blame] | 157 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
| 158 | #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */ |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 159 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 160 | #undef CONFIG_SYS_FLASH_CHECKSUM |
| 161 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
| 162 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 163 | |
Wolfgang Denk | 0708bc6 | 2010-10-07 21:51:12 +0200 | [diff] [blame] | 164 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 165 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 166 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
| 167 | #define CONFIG_SYS_RAMBOOT |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 168 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 169 | #undef CONFIG_SYS_RAMBOOT |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 170 | #endif |
| 171 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 172 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
Joe Hershberger | 10c2617 | 2011-10-11 23:57:25 -0500 | [diff] [blame] | 173 | /* Initial RAM address */ |
| 174 | #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 |
| 175 | /* Size of used area in RAM*/ |
| 176 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 177 | |
Joe Hershberger | 10c2617 | 2011-10-11 23:57:25 -0500 | [diff] [blame] | 178 | #define CONFIG_SYS_GBL_DATA_OFFSET \ |
| 179 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 180 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 181 | |
Joe Hershberger | 10c2617 | 2011-10-11 23:57:25 -0500 | [diff] [blame] | 182 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
Kim Phillips | 831d2f6 | 2012-06-30 18:29:20 -0500 | [diff] [blame] | 183 | #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 184 | |
| 185 | /* |
| 186 | * Local Bus LCRR and LBCR regs |
| 187 | * LCRR: DLL bypass, Clock divider is 4 |
| 188 | * External Local Bus rate is |
| 189 | * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV |
| 190 | */ |
Kim Phillips | 328040a | 2009-09-25 18:19:44 -0500 | [diff] [blame] | 191 | #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP |
| 192 | #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 193 | #define CONFIG_SYS_LBC_LBCR 0x00000000 |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 194 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 195 | #undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */ |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 196 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 197 | #ifdef CONFIG_SYS_LB_SDRAM |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 198 | /* Local bus BR2, OR2 definition for SDRAM if soldered on the board*/ |
| 199 | /* |
| 200 | * Base Register 2 and Option Register 2 configure SDRAM. |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 201 | * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 202 | * |
| 203 | * For BR2, need: |
| 204 | * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 |
| 205 | * port-size = 32-bits = BR2[19:20] = 11 |
| 206 | * no parity checking = BR2[21:22] = 00 |
| 207 | * SDRAM for MSEL = BR2[24:26] = 011 |
| 208 | * Valid = BR[31] = 1 |
| 209 | * |
| 210 | * 0 4 8 12 16 20 24 28 |
| 211 | * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 212 | */ |
| 213 | |
Joe Hershberger | f05b933 | 2011-10-11 23:57:30 -0500 | [diff] [blame] | 214 | #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LBC_SDRAM_BASE \ |
| 215 | | BR_PS_32 \ |
| 216 | | BR_MS_SDRAM \ |
| 217 | | BR_V) |
| 218 | /* 0xF0001861 */ |
| 219 | #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE |
| 220 | #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB) |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 221 | |
| 222 | /* |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 223 | * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 224 | * |
| 225 | * For OR2, need: |
| 226 | * 64MB mask for AM, OR2[0:7] = 1111 1100 |
| 227 | * XAM, OR2[17:18] = 11 |
| 228 | * 9 columns OR2[19-21] = 010 |
| 229 | * 13 rows OR2[23-25] = 100 |
| 230 | * EAD set for extra time OR[31] = 1 |
| 231 | * |
| 232 | * 0 4 8 12 16 20 24 28 |
| 233 | * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901 |
| 234 | */ |
| 235 | |
Joe Hershberger | f05b933 | 2011-10-11 23:57:30 -0500 | [diff] [blame] | 236 | #define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_LBC_SDRAM_SIZE) \ |
| 237 | | OR_SDRAM_XAM \ |
| 238 | | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \ |
| 239 | | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \ |
| 240 | | OR_SDRAM_EAD) |
| 241 | /* 0xFC006901 */ |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 242 | |
Joe Hershberger | 10c2617 | 2011-10-11 23:57:25 -0500 | [diff] [blame] | 243 | /* LB sdram refresh timer, about 6us */ |
| 244 | #define CONFIG_SYS_LBC_LSRT 0x32000000 |
| 245 | /* LB refresh timer prescal, 266MHz/32 */ |
| 246 | #define CONFIG_SYS_LBC_MRTPR 0x20000000 |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 247 | |
Joe Hershberger | 10c2617 | 2011-10-11 23:57:25 -0500 | [diff] [blame] | 248 | #define CONFIG_SYS_LBC_LSDMR_COMMON (LSDMR_RFEN \ |
| 249 | | LSDMR_BSMA1516 \ |
| 250 | | LSDMR_RFCR8 \ |
| 251 | | LSDMR_PRETOACT6 \ |
| 252 | | LSDMR_ACTTORW3 \ |
| 253 | | LSDMR_BL8 \ |
| 254 | | LSDMR_WRC3 \ |
| 255 | | LSDMR_CL3) |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 256 | |
| 257 | /* |
| 258 | * SDRAM Controller configuration sequence. |
| 259 | */ |
Kumar Gala | ac05b5e | 2009-03-26 01:34:39 -0500 | [diff] [blame] | 260 | #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) |
| 261 | #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) |
| 262 | #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) |
| 263 | #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) |
| 264 | #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 265 | #endif |
| 266 | |
| 267 | /* |
| 268 | * Serial Port |
| 269 | */ |
| 270 | #define CONFIG_CONS_INDEX 1 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 271 | #define CONFIG_SYS_NS16550 |
| 272 | #define CONFIG_SYS_NS16550_SERIAL |
| 273 | #define CONFIG_SYS_NS16550_REG_SIZE 1 |
| 274 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 275 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 276 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
Joe Hershberger | 10c2617 | 2011-10-11 23:57:25 -0500 | [diff] [blame] | 277 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 278 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 279 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) |
| 280 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 281 | |
Kim Phillips | f3c1478 | 2007-02-27 18:41:08 -0600 | [diff] [blame] | 282 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
Kim Phillips | 26c16d8 | 2010-04-15 17:36:05 -0500 | [diff] [blame] | 283 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 284 | /* Use the HUSH parser */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 285 | #define CONFIG_SYS_HUSH_PARSER |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 286 | |
| 287 | /* pass open firmware flat tree */ |
Paul Gortmaker | 61a608c | 2007-12-20 12:58:51 -0500 | [diff] [blame] | 288 | #define CONFIG_OF_LIBFDT 1 |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 289 | #define CONFIG_OF_BOARD_SETUP 1 |
Kim Phillips | fd47a74 | 2007-12-20 14:09:22 -0600 | [diff] [blame] | 290 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 291 | |
| 292 | /* I2C */ |
Heiko Schocher | f285074 | 2012-10-24 13:48:22 +0200 | [diff] [blame] | 293 | #define CONFIG_SYS_I2C |
| 294 | #define CONFIG_SYS_I2C_FSL |
| 295 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 |
| 296 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F |
| 297 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 |
| 298 | #define CONFIG_SYS_FSL_I2C2_SPEED 400000 |
| 299 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F |
| 300 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 |
| 301 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69}, {1, 0x69} } |
Paul Gortmaker | 04684f7 | 2009-10-02 18:54:20 -0400 | [diff] [blame] | 302 | /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */ |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 303 | |
| 304 | /* TSEC */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 305 | #define CONFIG_SYS_TSEC1_OFFSET 0x24000 |
Joe Hershberger | 10c2617 | 2011-10-11 23:57:25 -0500 | [diff] [blame] | 306 | #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 307 | #define CONFIG_SYS_TSEC2_OFFSET 0x25000 |
Joe Hershberger | 10c2617 | 2011-10-11 23:57:25 -0500 | [diff] [blame] | 308 | #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 309 | |
| 310 | /* |
| 311 | * General PCI |
| 312 | * Addresses are mapped 1-1. |
| 313 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 314 | #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 |
| 315 | #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE |
| 316 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ |
| 317 | #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 |
| 318 | #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE |
| 319 | #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ |
Joe Hershberger | 10c2617 | 2011-10-11 23:57:25 -0500 | [diff] [blame] | 320 | #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 |
| 321 | #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 |
| 322 | #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 323 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 324 | #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000 |
| 325 | #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE |
| 326 | #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ |
| 327 | #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000 |
| 328 | #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE |
| 329 | #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ |
Joe Hershberger | 10c2617 | 2011-10-11 23:57:25 -0500 | [diff] [blame] | 330 | #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 |
| 331 | #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000 |
| 332 | #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 333 | |
| 334 | #if defined(CONFIG_PCI) |
| 335 | |
| 336 | #define PCI_64BIT |
| 337 | #define PCI_ONE_PCI1 |
| 338 | #if defined(PCI_64BIT) |
| 339 | #undef PCI_ALL_PCI1 |
| 340 | #undef PCI_TWO_PCI1 |
| 341 | #undef PCI_ONE_PCI1 |
| 342 | #endif |
| 343 | |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 344 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
| 345 | |
| 346 | #undef CONFIG_EEPRO100 |
| 347 | #undef CONFIG_TULIP |
| 348 | |
| 349 | #if !defined(CONFIG_PCI_PNP) |
| 350 | #define PCI_ENET0_IOADDR 0xFIXME |
| 351 | #define PCI_ENET0_MEMADDR 0xFIXME |
| 352 | #define PCI_IDSEL_NUMBER 0xFIXME |
| 353 | #endif |
| 354 | |
| 355 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 356 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 357 | |
| 358 | #endif /* CONFIG_PCI */ |
| 359 | |
| 360 | /* |
| 361 | * TSEC configuration |
| 362 | */ |
| 363 | #define CONFIG_TSEC_ENET /* TSEC ethernet support */ |
| 364 | |
| 365 | #if defined(CONFIG_TSEC_ENET) |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 366 | |
Kim Phillips | 177e58f | 2007-05-16 16:52:19 -0500 | [diff] [blame] | 367 | #define CONFIG_TSEC1 1 |
| 368 | #define CONFIG_TSEC1_NAME "TSEC0" |
| 369 | #define CONFIG_TSEC2 1 |
| 370 | #define CONFIG_TSEC2_NAME "TSEC1" |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 371 | #define CONFIG_PHY_BCM5421S 1 |
| 372 | #define TSEC1_PHY_ADDR 0x19 |
| 373 | #define TSEC2_PHY_ADDR 0x1a |
| 374 | #define TSEC1_PHYIDX 0 |
| 375 | #define TSEC2_PHYIDX 0 |
Andy Fleming | 09b88df | 2007-08-15 20:03:25 -0500 | [diff] [blame] | 376 | #define TSEC1_FLAGS TSEC_GIGABIT |
| 377 | #define TSEC2_FLAGS TSEC_GIGABIT |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 378 | |
| 379 | /* Options are: TSEC[0-1] */ |
| 380 | #define CONFIG_ETHPRIME "TSEC0" |
| 381 | |
| 382 | #endif /* CONFIG_TSEC_ENET */ |
| 383 | |
| 384 | /* |
| 385 | * Environment |
| 386 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 387 | #ifndef CONFIG_SYS_RAMBOOT |
Jean-Christophe PLAGNIOL-VILLARD | 53db4cd | 2008-09-10 22:48:04 +0200 | [diff] [blame] | 388 | #define CONFIG_ENV_IS_IN_FLASH 1 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 389 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) |
Jean-Christophe PLAGNIOL-VILLARD | 7e1cda6 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 390 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ |
| 391 | #define CONFIG_ENV_SIZE 0x2000 |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 392 | |
| 393 | /* Address and size of Redundant Environment Sector */ |
Jean-Christophe PLAGNIOL-VILLARD | 7e1cda6 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 394 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) |
| 395 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 396 | |
| 397 | #else |
Joe Hershberger | 10c2617 | 2011-10-11 23:57:25 -0500 | [diff] [blame] | 398 | #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ |
Jean-Christophe PLAGNIOL-VILLARD | 68a8756 | 2008-09-10 22:48:00 +0200 | [diff] [blame] | 399 | #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 400 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
Jean-Christophe PLAGNIOL-VILLARD | 7e1cda6 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 401 | #define CONFIG_ENV_SIZE 0x2000 |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 402 | #endif |
| 403 | |
| 404 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 405 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 406 | |
Jon Loeliger | 1f166a2 | 2007-07-04 22:30:58 -0500 | [diff] [blame] | 407 | |
| 408 | /* |
Jon Loeliger | 5c4ddae | 2007-07-10 10:12:10 -0500 | [diff] [blame] | 409 | * BOOTP options |
| 410 | */ |
| 411 | #define CONFIG_BOOTP_BOOTFILESIZE |
| 412 | #define CONFIG_BOOTP_BOOTPATH |
| 413 | #define CONFIG_BOOTP_GATEWAY |
| 414 | #define CONFIG_BOOTP_HOSTNAME |
| 415 | |
| 416 | |
| 417 | /* |
Jon Loeliger | 1f166a2 | 2007-07-04 22:30:58 -0500 | [diff] [blame] | 418 | * Command line configuration. |
| 419 | */ |
| 420 | #include <config_cmd_default.h> |
| 421 | |
| 422 | #define CONFIG_CMD_I2C |
| 423 | #define CONFIG_CMD_MII |
| 424 | #define CONFIG_CMD_PING |
| 425 | |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 426 | #if defined(CONFIG_PCI) |
Paul Gortmaker | 61a608c | 2007-12-20 12:58:51 -0500 | [diff] [blame] | 427 | #define CONFIG_CMD_PCI |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 428 | #endif |
Jon Loeliger | 1f166a2 | 2007-07-04 22:30:58 -0500 | [diff] [blame] | 429 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 430 | #if defined(CONFIG_SYS_RAMBOOT) |
Mike Frysinger | 78dcaf4 | 2009-01-28 19:08:14 -0500 | [diff] [blame] | 431 | #undef CONFIG_CMD_SAVEENV |
Jon Loeliger | 1f166a2 | 2007-07-04 22:30:58 -0500 | [diff] [blame] | 432 | #undef CONFIG_CMD_LOADS |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 433 | #endif |
| 434 | |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 435 | |
| 436 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
| 437 | |
| 438 | /* |
| 439 | * Miscellaneous configurable options |
| 440 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 441 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
| 442 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 443 | |
Jon Loeliger | 1f166a2 | 2007-07-04 22:30:58 -0500 | [diff] [blame] | 444 | #if defined(CONFIG_CMD_KGDB) |
Joe Hershberger | 10c2617 | 2011-10-11 23:57:25 -0500 | [diff] [blame] | 445 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 446 | #else |
Joe Hershberger | 10c2617 | 2011-10-11 23:57:25 -0500 | [diff] [blame] | 447 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 448 | #endif |
| 449 | |
Joe Hershberger | 10c2617 | 2011-10-11 23:57:25 -0500 | [diff] [blame] | 450 | /* Print Buffer Size */ |
| 451 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) |
| 452 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
| 453 | /* Boot Argument Buffer Size */ |
| 454 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 455 | |
| 456 | /* |
| 457 | * For booting Linux, the board info and command line data |
Ira W. Snyder | c5a22d0 | 2010-09-10 15:42:32 -0700 | [diff] [blame] | 458 | * have to be in the first 256 MB of memory, since this is |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 459 | * the maximum mapped by the Linux kernel during initialization. |
| 460 | */ |
Joe Hershberger | 10c2617 | 2011-10-11 23:57:25 -0500 | [diff] [blame] | 461 | /* Initial Memory map for Linux*/ |
| 462 | #define CONFIG_SYS_BOOTMAPSZ (256 << 20) |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 463 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 464 | #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 465 | |
| 466 | #if 1 /*528/264*/ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 467 | #define CONFIG_SYS_HRCW_LOW (\ |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 468 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
| 469 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ |
| 470 | HRCWL_CSB_TO_CLKIN |\ |
| 471 | HRCWL_VCO_1X2 |\ |
| 472 | HRCWL_CORE_TO_CSB_2X1) |
| 473 | #elif 0 /*396/132*/ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 474 | #define CONFIG_SYS_HRCW_LOW (\ |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 475 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
| 476 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ |
| 477 | HRCWL_CSB_TO_CLKIN |\ |
| 478 | HRCWL_VCO_1X4 |\ |
| 479 | HRCWL_CORE_TO_CSB_3X1) |
| 480 | #elif 0 /*264/132*/ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 481 | #define CONFIG_SYS_HRCW_LOW (\ |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 482 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
| 483 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ |
| 484 | HRCWL_CSB_TO_CLKIN |\ |
| 485 | HRCWL_VCO_1X4 |\ |
| 486 | HRCWL_CORE_TO_CSB_2X1) |
| 487 | #elif 0 /*132/132*/ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 488 | #define CONFIG_SYS_HRCW_LOW (\ |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 489 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
| 490 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ |
| 491 | HRCWL_CSB_TO_CLKIN |\ |
| 492 | HRCWL_VCO_1X4 |\ |
| 493 | HRCWL_CORE_TO_CSB_1X1) |
| 494 | #elif 0 /*264/264 */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 495 | #define CONFIG_SYS_HRCW_LOW (\ |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 496 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
| 497 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ |
| 498 | HRCWL_CSB_TO_CLKIN |\ |
| 499 | HRCWL_VCO_1X4 |\ |
| 500 | HRCWL_CORE_TO_CSB_1X1) |
| 501 | #endif |
| 502 | |
| 503 | #if defined(PCI_64BIT) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 504 | #define CONFIG_SYS_HRCW_HIGH (\ |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 505 | HRCWH_PCI_HOST |\ |
| 506 | HRCWH_64_BIT_PCI |\ |
| 507 | HRCWH_PCI1_ARBITER_ENABLE |\ |
| 508 | HRCWH_PCI2_ARBITER_DISABLE |\ |
| 509 | HRCWH_CORE_ENABLE |\ |
| 510 | HRCWH_FROM_0X00000100 |\ |
| 511 | HRCWH_BOOTSEQ_DISABLE |\ |
| 512 | HRCWH_SW_WATCHDOG_DISABLE |\ |
| 513 | HRCWH_ROM_LOC_LOCAL_16BIT |\ |
| 514 | HRCWH_TSEC1M_IN_GMII |\ |
Joe Hershberger | 10c2617 | 2011-10-11 23:57:25 -0500 | [diff] [blame] | 515 | HRCWH_TSEC2M_IN_GMII) |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 516 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 517 | #define CONFIG_SYS_HRCW_HIGH (\ |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 518 | HRCWH_PCI_HOST |\ |
| 519 | HRCWH_32_BIT_PCI |\ |
| 520 | HRCWH_PCI1_ARBITER_ENABLE |\ |
| 521 | HRCWH_PCI2_ARBITER_ENABLE |\ |
| 522 | HRCWH_CORE_ENABLE |\ |
| 523 | HRCWH_FROM_0X00000100 |\ |
| 524 | HRCWH_BOOTSEQ_DISABLE |\ |
| 525 | HRCWH_SW_WATCHDOG_DISABLE |\ |
| 526 | HRCWH_ROM_LOC_LOCAL_16BIT |\ |
| 527 | HRCWH_TSEC1M_IN_GMII |\ |
Joe Hershberger | 10c2617 | 2011-10-11 23:57:25 -0500 | [diff] [blame] | 528 | HRCWH_TSEC2M_IN_GMII) |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 529 | #endif |
| 530 | |
| 531 | /* System IO Config */ |
Kim Phillips | f91cad6 | 2009-06-05 14:11:33 -0500 | [diff] [blame] | 532 | #define CONFIG_SYS_SICRH 0 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 533 | #define CONFIG_SYS_SICRL SICRL_LDP_A |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 534 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 535 | #define CONFIG_SYS_HID0_INIT 0x000000000 |
Joe Hershberger | 10c2617 | 2011-10-11 23:57:25 -0500 | [diff] [blame] | 536 | #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \ |
| 537 | | HID0_ENABLE_INSTRUCTION_CACHE) |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 538 | |
Joe Hershberger | 10c2617 | 2011-10-11 23:57:25 -0500 | [diff] [blame] | 539 | /* #define CONFIG_SYS_HID0_FINAL (\ |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 540 | HID0_ENABLE_INSTRUCTION_CACHE |\ |
| 541 | HID0_ENABLE_M_BIT |\ |
Joe Hershberger | 10c2617 | 2011-10-11 23:57:25 -0500 | [diff] [blame] | 542 | HID0_ENABLE_ADDRESS_BROADCAST) */ |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 543 | |
| 544 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 545 | #define CONFIG_SYS_HID2 HID2_HBE |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 546 | |
Becky Bruce | 03ea1be | 2008-05-08 19:02:12 -0500 | [diff] [blame] | 547 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
| 548 | |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 549 | /* DDR @ 0x00000000 */ |
Joe Hershberger | 10c2617 | 2011-10-11 23:57:25 -0500 | [diff] [blame] | 550 | #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ |
Joe Hershberger | bfd8973 | 2011-10-11 23:57:28 -0500 | [diff] [blame] | 551 | | BATL_PP_RW \ |
Joe Hershberger | 10c2617 | 2011-10-11 23:57:25 -0500 | [diff] [blame] | 552 | | BATL_MEMCOHERENCE) |
| 553 | #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ |
| 554 | | BATU_BL_256M \ |
| 555 | | BATU_VS \ |
| 556 | | BATU_VP) |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 557 | |
| 558 | /* PCI @ 0x80000000 */ |
| 559 | #ifdef CONFIG_PCI |
Gabor Juhos | b445873 | 2013-05-30 07:06:12 +0000 | [diff] [blame] | 560 | #define CONFIG_PCI_INDIRECT_BRIDGE |
Joe Hershberger | 10c2617 | 2011-10-11 23:57:25 -0500 | [diff] [blame] | 561 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \ |
Joe Hershberger | bfd8973 | 2011-10-11 23:57:28 -0500 | [diff] [blame] | 562 | | BATL_PP_RW \ |
Joe Hershberger | 10c2617 | 2011-10-11 23:57:25 -0500 | [diff] [blame] | 563 | | BATL_MEMCOHERENCE) |
| 564 | #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ |
| 565 | | BATU_BL_256M \ |
| 566 | | BATU_VS \ |
| 567 | | BATU_VP) |
| 568 | #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ |
Joe Hershberger | bfd8973 | 2011-10-11 23:57:28 -0500 | [diff] [blame] | 569 | | BATL_PP_RW \ |
Joe Hershberger | 10c2617 | 2011-10-11 23:57:25 -0500 | [diff] [blame] | 570 | | BATL_CACHEINHIBIT \ |
| 571 | | BATL_GUARDEDSTORAGE) |
| 572 | #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ |
| 573 | | BATU_BL_256M \ |
| 574 | | BATU_VS \ |
| 575 | | BATU_VP) |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 576 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 577 | #define CONFIG_SYS_IBAT1L (0) |
| 578 | #define CONFIG_SYS_IBAT1U (0) |
| 579 | #define CONFIG_SYS_IBAT2L (0) |
| 580 | #define CONFIG_SYS_IBAT2U (0) |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 581 | #endif |
| 582 | |
| 583 | #ifdef CONFIG_MPC83XX_PCI2 |
Joe Hershberger | 10c2617 | 2011-10-11 23:57:25 -0500 | [diff] [blame] | 584 | #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \ |
Joe Hershberger | bfd8973 | 2011-10-11 23:57:28 -0500 | [diff] [blame] | 585 | | BATL_PP_RW \ |
Joe Hershberger | 10c2617 | 2011-10-11 23:57:25 -0500 | [diff] [blame] | 586 | | BATL_MEMCOHERENCE) |
| 587 | #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \ |
| 588 | | BATU_BL_256M \ |
| 589 | | BATU_VS \ |
| 590 | | BATU_VP) |
| 591 | #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \ |
Joe Hershberger | bfd8973 | 2011-10-11 23:57:28 -0500 | [diff] [blame] | 592 | | BATL_PP_RW \ |
Joe Hershberger | 10c2617 | 2011-10-11 23:57:25 -0500 | [diff] [blame] | 593 | | BATL_CACHEINHIBIT \ |
| 594 | | BATL_GUARDEDSTORAGE) |
| 595 | #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \ |
| 596 | | BATU_BL_256M \ |
| 597 | | BATU_VS \ |
| 598 | | BATU_VP) |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 599 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 600 | #define CONFIG_SYS_IBAT3L (0) |
| 601 | #define CONFIG_SYS_IBAT3U (0) |
| 602 | #define CONFIG_SYS_IBAT4L (0) |
| 603 | #define CONFIG_SYS_IBAT4U (0) |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 604 | #endif |
| 605 | |
| 606 | /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */ |
Joe Hershberger | 10c2617 | 2011-10-11 23:57:25 -0500 | [diff] [blame] | 607 | #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ |
Joe Hershberger | bfd8973 | 2011-10-11 23:57:28 -0500 | [diff] [blame] | 608 | | BATL_PP_RW \ |
Joe Hershberger | 10c2617 | 2011-10-11 23:57:25 -0500 | [diff] [blame] | 609 | | BATL_CACHEINHIBIT \ |
| 610 | | BATL_GUARDEDSTORAGE) |
| 611 | #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ |
| 612 | | BATU_BL_256M \ |
| 613 | | BATU_VS \ |
| 614 | | BATU_VP) |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 615 | |
Joe Hershberger | f05b933 | 2011-10-11 23:57:30 -0500 | [diff] [blame] | 616 | /* LBC SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ |
| 617 | #define CONFIG_SYS_IBAT6L (CONFIG_SYS_LBC_SDRAM_BASE \ |
Joe Hershberger | bfd8973 | 2011-10-11 23:57:28 -0500 | [diff] [blame] | 618 | | BATL_PP_RW \ |
Joe Hershberger | 10c2617 | 2011-10-11 23:57:25 -0500 | [diff] [blame] | 619 | | BATL_MEMCOHERENCE \ |
| 620 | | BATL_GUARDEDSTORAGE) |
Joe Hershberger | f05b933 | 2011-10-11 23:57:30 -0500 | [diff] [blame] | 621 | #define CONFIG_SYS_IBAT6U (CONFIG_SYS_LBC_SDRAM_BASE \ |
| 622 | | BATU_BL_256M \ |
| 623 | | BATU_VS \ |
| 624 | | BATU_VP) |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 625 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 626 | #define CONFIG_SYS_IBAT7L (0) |
| 627 | #define CONFIG_SYS_IBAT7U (0) |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 628 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 629 | #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L |
| 630 | #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U |
| 631 | #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L |
| 632 | #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U |
| 633 | #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L |
| 634 | #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U |
| 635 | #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L |
| 636 | #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U |
| 637 | #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L |
| 638 | #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U |
| 639 | #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L |
| 640 | #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U |
| 641 | #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L |
| 642 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U |
| 643 | #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L |
| 644 | #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 645 | |
Jon Loeliger | 1f166a2 | 2007-07-04 22:30:58 -0500 | [diff] [blame] | 646 | #if defined(CONFIG_CMD_KGDB) |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 647 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 648 | #endif |
| 649 | |
| 650 | /* |
| 651 | * Environment Configuration |
| 652 | */ |
| 653 | #define CONFIG_ENV_OVERWRITE |
| 654 | |
| 655 | #if defined(CONFIG_TSEC_ENET) |
Andy Fleming | 458c389 | 2007-08-16 16:35:02 -0500 | [diff] [blame] | 656 | #define CONFIG_HAS_ETH0 |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 657 | #define CONFIG_HAS_ETH1 |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 658 | #endif |
| 659 | |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 660 | #define CONFIG_HOSTNAME SBC8349 |
Joe Hershberger | 257ff78 | 2011-10-13 13:03:47 +0000 | [diff] [blame] | 661 | #define CONFIG_ROOTPATH "/tftpboot/rootfs" |
Joe Hershberger | e4da248 | 2011-10-13 13:03:48 +0000 | [diff] [blame] | 662 | #define CONFIG_BOOTFILE "uImage" |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 663 | |
Joe Hershberger | 10c2617 | 2011-10-11 23:57:25 -0500 | [diff] [blame] | 664 | /* default location for tftp and bootm */ |
| 665 | #define CONFIG_LOADADDR 800000 |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 666 | |
| 667 | #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ |
Joe Hershberger | 10c2617 | 2011-10-11 23:57:25 -0500 | [diff] [blame] | 668 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 669 | |
| 670 | #define CONFIG_BAUDRATE 115200 |
| 671 | |
| 672 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 673 | "netdev=eth0\0" \ |
Detlev Zundel | 027fa49 | 2008-04-18 14:50:01 +0200 | [diff] [blame] | 674 | "hostname=sbc8349\0" \ |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 675 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ |
| 676 | "nfsroot=${serverip}:${rootpath}\0" \ |
| 677 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ |
| 678 | "addip=setenv bootargs ${bootargs} " \ |
| 679 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ |
| 680 | ":${hostname}:${netdev}:off panic=1\0" \ |
| 681 | "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ |
| 682 | "flash_nfs=run nfsargs addip addtty;" \ |
| 683 | "bootm ${kernel_addr}\0" \ |
| 684 | "flash_self=run ramargs addip addtty;" \ |
| 685 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ |
| 686 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ |
| 687 | "bootm\0" \ |
| 688 | "load=tftp 100000 /tftpboot/sbc8349/u-boot.bin\0" \ |
Paul Gortmaker | 80b4bb7 | 2009-07-23 17:10:55 -0400 | [diff] [blame] | 689 | "update=protect off ff800000 ff83ffff; " \ |
Joe Hershberger | 10c2617 | 2011-10-11 23:57:25 -0500 | [diff] [blame] | 690 | "era ff800000 ff83ffff; cp.b 100000 ff800000 ${filesize}\0" \ |
Detlev Zundel | 406e578 | 2008-03-06 16:45:53 +0100 | [diff] [blame] | 691 | "upd=run load update\0" \ |
Kim Phillips | fd3a3fc | 2009-08-21 16:34:38 -0500 | [diff] [blame] | 692 | "fdtaddr=780000\0" \ |
Detlev Zundel | 027fa49 | 2008-04-18 14:50:01 +0200 | [diff] [blame] | 693 | "fdtfile=sbc8349.dtb\0" \ |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 694 | "" |
| 695 | |
Joe Hershberger | 10c2617 | 2011-10-11 23:57:25 -0500 | [diff] [blame] | 696 | #define CONFIG_NFSBOOTCOMMAND \ |
| 697 | "setenv bootargs root=/dev/nfs rw " \ |
| 698 | "nfsroot=$serverip:$rootpath " \ |
| 699 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ |
| 700 | "$netdev:off " \ |
| 701 | "console=$consoledev,$baudrate $othbootargs;" \ |
| 702 | "tftp $loadaddr $bootfile;" \ |
| 703 | "tftp $fdtaddr $fdtfile;" \ |
| 704 | "bootm $loadaddr - $fdtaddr" |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 705 | |
| 706 | #define CONFIG_RAMBOOTCOMMAND \ |
Joe Hershberger | 10c2617 | 2011-10-11 23:57:25 -0500 | [diff] [blame] | 707 | "setenv bootargs root=/dev/ram rw " \ |
| 708 | "console=$consoledev,$baudrate $othbootargs;" \ |
| 709 | "tftp $ramdiskaddr $ramdiskfile;" \ |
| 710 | "tftp $loadaddr $bootfile;" \ |
| 711 | "tftp $fdtaddr $fdtfile;" \ |
| 712 | "bootm $loadaddr $ramdiskaddr $fdtaddr" |
Paul Gortmaker | 2bd9f1b | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 713 | |
| 714 | #define CONFIG_BOOTCOMMAND "run flash_self" |
| 715 | |
| 716 | #endif /* __CONFIG_H */ |