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Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -05001/*
2 * WindRiver SBC8349 U-Boot configuration file.
3 * Copyright (c) 2006, 2007 Wind River Systems, Inc.
4 *
5 * Paul Gortmaker <paul.gortmaker@windriver.com>
6 * Based on the MPC8349EMDS config.
7 *
Wolfgang Denkbd8ec7e2013-10-07 13:07:26 +02008 * SPDX-License-Identifier: GPL-2.0+
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -05009 */
10
11/*
12 * sbc8349 board configuration file.
13 */
14
15#ifndef __CONFIG_H
16#define __CONFIG_H
17
Kim Phillipsd2f66b82015-03-17 12:00:45 -050018#define CONFIG_SYS_GENERIC_BOARD
19#define CONFIG_DISPLAY_BOARDINFO
20
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -050021/*
22 * High Level Configuration Options
23 */
24#define CONFIG_E300 1 /* E300 Family */
Peter Tyser72f2d392009-05-22 17:23:25 -050025#define CONFIG_MPC834x 1 /* MPC834x family */
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -050026#define CONFIG_MPC8349 1 /* MPC8349 specific */
27#define CONFIG_SBC8349 1 /* WRS SBC8349 board specific */
28
Wolfgang Denk291ba1b2010-10-06 09:05:45 +020029#define CONFIG_SYS_TEXT_BASE 0xFF800000
30
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -050031/* Don't enable PCI2 on sbc834x - it doesn't exist physically. */
32#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
33
Paul Gortmaker0aaee142009-08-21 16:21:58 -050034/*
35 * The default if PCI isn't enabled, or if no PCI clk setting is given
36 * is 66MHz; this is what the board defaults to when the PCI slot is
37 * physically empty. The board will automatically (i.e w/o jumpers)
38 * clock down to 33MHz if you insert a 33MHz PCI card.
39 */
Wolfgang Denk291ba1b2010-10-06 09:05:45 +020040#ifdef CONFIG_PCI_33M
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -050041#define CONFIG_83XX_CLKIN 33000000 /* in Hz */
Paul Gortmaker0aaee142009-08-21 16:21:58 -050042#else /* 66M */
43#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -050044#endif
45
46#ifndef CONFIG_SYS_CLK_FREQ
Wolfgang Denk291ba1b2010-10-06 09:05:45 +020047#ifdef CONFIG_PCI_33M
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -050048#define CONFIG_SYS_CLK_FREQ 33000000
49#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1
Paul Gortmaker0aaee142009-08-21 16:21:58 -050050#else /* 66M */
51#define CONFIG_SYS_CLK_FREQ 66000000
52#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -050053#endif
54#endif
55
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -050056#undef CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
57
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020058#define CONFIG_SYS_IMMR 0xE0000000
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -050059
Joe Hershberger10c26172011-10-11 23:57:25 -050060#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020061#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
62#define CONFIG_SYS_MEMTEST_END 0x00100000
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -050063
64/*
65 * DDR Setup
66 */
67#undef CONFIG_DDR_ECC /* only for ECC DDR module */
68#undef CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
69#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
Joe Hershberger10c26172011-10-11 23:57:25 -050070#define CONFIG_SYS_83XX_DDR_USES_CS0 /* WRS; Fsl board uses CS2/CS3 */
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -050071
72/*
73 * 32-bit data path mode.
74 *
75 * Please note that using this mode for devices with the real density of 64-bit
76 * effectively reduces the amount of available memory due to the effect of
77 * wrapping around while translating address to row/columns, for example in the
78 * 256MB module the upper 128MB get aliased with contents of the lower
79 * 128MB); normally this define should be used for devices with real 32-bit
80 * data path.
81 */
82#undef CONFIG_DDR_32BIT
83
Joe Hershberger10c26172011-10-11 23:57:25 -050084#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020085#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
86#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
87#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -050088 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
89#define CONFIG_DDR_2T_TIMING
90
91#if defined(CONFIG_SPD_EEPROM)
92/*
93 * Determine DDR configuration from I2C interface.
94 */
95#define SPD_EEPROM_ADDRESS 0x52 /* DDR DIMM */
96
97#else
98/*
99 * Manually set up DDR parameters
100 * NB: manual DDR setup untested on sbc834x
101 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200102#define CONFIG_SYS_DDR_SIZE 256 /* MB */
Joe Hershberger5ade3902011-10-11 23:57:31 -0500103#define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \
Joe Hershberger10c26172011-10-11 23:57:25 -0500104 | CSCONFIG_ROW_BIT_13 \
105 | CSCONFIG_COL_BIT_10)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200106#define CONFIG_SYS_DDR_TIMING_1 0x36332321
107#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
Joe Hershberger10c26172011-10-11 23:57:25 -0500108#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200109#define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500110
111#if defined(CONFIG_DDR_32BIT)
112/* set burst length to 8 for 32-bit data path */
Joe Hershberger10c26172011-10-11 23:57:25 -0500113 /* DLL,normal,seq,4/2.5, 8 burst len */
114#define CONFIG_SYS_DDR_MODE 0x00000023
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500115#else
116/* the default burst length is 4 - for 64-bit data path */
Joe Hershberger10c26172011-10-11 23:57:25 -0500117 /* DLL,normal,seq,4/2.5, 4 burst len */
118#define CONFIG_SYS_DDR_MODE 0x00000022
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500119#endif
120#endif
121
122/*
123 * SDRAM on the Local Bus
124 */
Joe Hershbergerf05b9332011-10-11 23:57:30 -0500125#define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */
126#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500127
128/*
129 * FLASH on the Local Bus
130 */
Joe Hershberger10c26172011-10-11 23:57:25 -0500131#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
132#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200133#define CONFIG_SYS_FLASH_BASE 0xFF800000 /* start of FLASH */
134#define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */
135/* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500136
Joe Hershbergerf05b9332011-10-11 23:57:30 -0500137#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
138 | BR_PS_16 /* 16 bit port */ \
139 | BR_MS_GPCM /* MSEL = GPCM */ \
140 | BR_V) /* valid */
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500141
Joe Hershbergerf05b9332011-10-11 23:57:30 -0500142#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
143 | OR_GPCM_XAM \
144 | OR_GPCM_CSNT \
145 | OR_GPCM_ACS_DIV2 \
146 | OR_GPCM_XACS \
147 | OR_GPCM_SCY_15 \
148 | OR_GPCM_TRLX_SET \
149 | OR_GPCM_EHTR_SET \
150 | OR_GPCM_EAD)
151 /* 0xFF806FF7 */
152
Joe Hershberger10c26172011-10-11 23:57:25 -0500153 /* window base at flash base */
154#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
Joe Hershbergerf05b9332011-10-11 23:57:30 -0500155#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB)
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500156
Joe Hershberger10c26172011-10-11 23:57:25 -0500157#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
158#define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500159
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200160#undef CONFIG_SYS_FLASH_CHECKSUM
161#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
162#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500163
Wolfgang Denk0708bc62010-10-07 21:51:12 +0200164#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500165
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200166#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
167#define CONFIG_SYS_RAMBOOT
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500168#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200169#undef CONFIG_SYS_RAMBOOT
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500170#endif
171
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200172#define CONFIG_SYS_INIT_RAM_LOCK 1
Joe Hershberger10c26172011-10-11 23:57:25 -0500173 /* Initial RAM address */
174#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000
175 /* Size of used area in RAM*/
176#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500177
Joe Hershberger10c26172011-10-11 23:57:25 -0500178#define CONFIG_SYS_GBL_DATA_OFFSET \
179 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200180#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500181
Joe Hershberger10c26172011-10-11 23:57:25 -0500182#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
Kim Phillips831d2f62012-06-30 18:29:20 -0500183#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500184
185/*
186 * Local Bus LCRR and LBCR regs
187 * LCRR: DLL bypass, Clock divider is 4
188 * External Local Bus rate is
189 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
190 */
Kim Phillips328040a2009-09-25 18:19:44 -0500191#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
192#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200193#define CONFIG_SYS_LBC_LBCR 0x00000000
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500194
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200195#undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500196
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200197#ifdef CONFIG_SYS_LB_SDRAM
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500198/* Local bus BR2, OR2 definition for SDRAM if soldered on the board*/
199/*
200 * Base Register 2 and Option Register 2 configure SDRAM.
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200201 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500202 *
203 * For BR2, need:
204 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
205 * port-size = 32-bits = BR2[19:20] = 11
206 * no parity checking = BR2[21:22] = 00
207 * SDRAM for MSEL = BR2[24:26] = 011
208 * Valid = BR[31] = 1
209 *
210 * 0 4 8 12 16 20 24 28
211 * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500212 */
213
Joe Hershbergerf05b9332011-10-11 23:57:30 -0500214#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LBC_SDRAM_BASE \
215 | BR_PS_32 \
216 | BR_MS_SDRAM \
217 | BR_V)
218 /* 0xF0001861 */
219#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE
220#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB)
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500221
222/*
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200223 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500224 *
225 * For OR2, need:
226 * 64MB mask for AM, OR2[0:7] = 1111 1100
227 * XAM, OR2[17:18] = 11
228 * 9 columns OR2[19-21] = 010
229 * 13 rows OR2[23-25] = 100
230 * EAD set for extra time OR[31] = 1
231 *
232 * 0 4 8 12 16 20 24 28
233 * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
234 */
235
Joe Hershbergerf05b9332011-10-11 23:57:30 -0500236#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_LBC_SDRAM_SIZE) \
237 | OR_SDRAM_XAM \
238 | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \
239 | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \
240 | OR_SDRAM_EAD)
241 /* 0xFC006901 */
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500242
Joe Hershberger10c26172011-10-11 23:57:25 -0500243 /* LB sdram refresh timer, about 6us */
244#define CONFIG_SYS_LBC_LSRT 0x32000000
245 /* LB refresh timer prescal, 266MHz/32 */
246#define CONFIG_SYS_LBC_MRTPR 0x20000000
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500247
Joe Hershberger10c26172011-10-11 23:57:25 -0500248#define CONFIG_SYS_LBC_LSDMR_COMMON (LSDMR_RFEN \
249 | LSDMR_BSMA1516 \
250 | LSDMR_RFCR8 \
251 | LSDMR_PRETOACT6 \
252 | LSDMR_ACTTORW3 \
253 | LSDMR_BL8 \
254 | LSDMR_WRC3 \
255 | LSDMR_CL3)
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500256
257/*
258 * SDRAM Controller configuration sequence.
259 */
Kumar Galaac05b5e2009-03-26 01:34:39 -0500260#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
261#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
262#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
263#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
264#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500265#endif
266
267/*
268 * Serial Port
269 */
270#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200271#define CONFIG_SYS_NS16550
272#define CONFIG_SYS_NS16550_SERIAL
273#define CONFIG_SYS_NS16550_REG_SIZE 1
274#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500275
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200276#define CONFIG_SYS_BAUDRATE_TABLE \
Joe Hershberger10c26172011-10-11 23:57:25 -0500277 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500278
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200279#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
280#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500281
Kim Phillipsf3c14782007-02-27 18:41:08 -0600282#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Kim Phillips26c16d82010-04-15 17:36:05 -0500283#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500284/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200285#define CONFIG_SYS_HUSH_PARSER
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500286
287/* pass open firmware flat tree */
Paul Gortmaker61a608c2007-12-20 12:58:51 -0500288#define CONFIG_OF_LIBFDT 1
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500289#define CONFIG_OF_BOARD_SETUP 1
Kim Phillipsfd47a742007-12-20 14:09:22 -0600290#define CONFIG_OF_STDOUT_VIA_ALIAS 1
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500291
292/* I2C */
Heiko Schocherf2850742012-10-24 13:48:22 +0200293#define CONFIG_SYS_I2C
294#define CONFIG_SYS_I2C_FSL
295#define CONFIG_SYS_FSL_I2C_SPEED 400000
296#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
297#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
298#define CONFIG_SYS_FSL_I2C2_SPEED 400000
299#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
300#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
301#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69}, {1, 0x69} }
Paul Gortmaker04684f72009-10-02 18:54:20 -0400302/* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500303
304/* TSEC */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200305#define CONFIG_SYS_TSEC1_OFFSET 0x24000
Joe Hershberger10c26172011-10-11 23:57:25 -0500306#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200307#define CONFIG_SYS_TSEC2_OFFSET 0x25000
Joe Hershberger10c26172011-10-11 23:57:25 -0500308#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500309
310/*
311 * General PCI
312 * Addresses are mapped 1-1.
313 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200314#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
315#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
316#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
317#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
318#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
319#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
Joe Hershberger10c26172011-10-11 23:57:25 -0500320#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
321#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
322#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500323
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200324#define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
325#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
326#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
327#define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
328#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
329#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
Joe Hershberger10c26172011-10-11 23:57:25 -0500330#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
331#define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
332#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500333
334#if defined(CONFIG_PCI)
335
336#define PCI_64BIT
337#define PCI_ONE_PCI1
338#if defined(PCI_64BIT)
339#undef PCI_ALL_PCI1
340#undef PCI_TWO_PCI1
341#undef PCI_ONE_PCI1
342#endif
343
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500344#define CONFIG_PCI_PNP /* do pci plug-and-play */
345
346#undef CONFIG_EEPRO100
347#undef CONFIG_TULIP
348
349#if !defined(CONFIG_PCI_PNP)
350 #define PCI_ENET0_IOADDR 0xFIXME
351 #define PCI_ENET0_MEMADDR 0xFIXME
352 #define PCI_IDSEL_NUMBER 0xFIXME
353#endif
354
355#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200356#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500357
358#endif /* CONFIG_PCI */
359
360/*
361 * TSEC configuration
362 */
363#define CONFIG_TSEC_ENET /* TSEC ethernet support */
364
365#if defined(CONFIG_TSEC_ENET)
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500366
Kim Phillips177e58f2007-05-16 16:52:19 -0500367#define CONFIG_TSEC1 1
368#define CONFIG_TSEC1_NAME "TSEC0"
369#define CONFIG_TSEC2 1
370#define CONFIG_TSEC2_NAME "TSEC1"
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500371#define CONFIG_PHY_BCM5421S 1
372#define TSEC1_PHY_ADDR 0x19
373#define TSEC2_PHY_ADDR 0x1a
374#define TSEC1_PHYIDX 0
375#define TSEC2_PHYIDX 0
Andy Fleming09b88df2007-08-15 20:03:25 -0500376#define TSEC1_FLAGS TSEC_GIGABIT
377#define TSEC2_FLAGS TSEC_GIGABIT
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500378
379/* Options are: TSEC[0-1] */
380#define CONFIG_ETHPRIME "TSEC0"
381
382#endif /* CONFIG_TSEC_ENET */
383
384/*
385 * Environment
386 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200387#ifndef CONFIG_SYS_RAMBOOT
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200388 #define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200389 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200390 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
391 #define CONFIG_ENV_SIZE 0x2000
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500392
393/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200394#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
395#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500396
397#else
Joe Hershberger10c26172011-10-11 23:57:25 -0500398 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
Jean-Christophe PLAGNIOL-VILLARD68a87562008-09-10 22:48:00 +0200399 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200400 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200401 #define CONFIG_ENV_SIZE 0x2000
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500402#endif
403
404#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200405#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500406
Jon Loeliger1f166a22007-07-04 22:30:58 -0500407
408/*
Jon Loeliger5c4ddae2007-07-10 10:12:10 -0500409 * BOOTP options
410 */
411#define CONFIG_BOOTP_BOOTFILESIZE
412#define CONFIG_BOOTP_BOOTPATH
413#define CONFIG_BOOTP_GATEWAY
414#define CONFIG_BOOTP_HOSTNAME
415
416
417/*
Jon Loeliger1f166a22007-07-04 22:30:58 -0500418 * Command line configuration.
419 */
420#include <config_cmd_default.h>
421
422#define CONFIG_CMD_I2C
423#define CONFIG_CMD_MII
424#define CONFIG_CMD_PING
425
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500426#if defined(CONFIG_PCI)
Paul Gortmaker61a608c2007-12-20 12:58:51 -0500427 #define CONFIG_CMD_PCI
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500428#endif
Jon Loeliger1f166a22007-07-04 22:30:58 -0500429
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200430#if defined(CONFIG_SYS_RAMBOOT)
Mike Frysinger78dcaf42009-01-28 19:08:14 -0500431 #undef CONFIG_CMD_SAVEENV
Jon Loeliger1f166a22007-07-04 22:30:58 -0500432 #undef CONFIG_CMD_LOADS
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500433#endif
434
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500435
436#undef CONFIG_WATCHDOG /* watchdog disabled */
437
438/*
439 * Miscellaneous configurable options
440 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200441#define CONFIG_SYS_LONGHELP /* undef to save memory */
442#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500443
Jon Loeliger1f166a22007-07-04 22:30:58 -0500444#if defined(CONFIG_CMD_KGDB)
Joe Hershberger10c26172011-10-11 23:57:25 -0500445 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500446#else
Joe Hershberger10c26172011-10-11 23:57:25 -0500447 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500448#endif
449
Joe Hershberger10c26172011-10-11 23:57:25 -0500450 /* Print Buffer Size */
451#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
452#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
453 /* Boot Argument Buffer Size */
454#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500455
456/*
457 * For booting Linux, the board info and command line data
Ira W. Snyderc5a22d02010-09-10 15:42:32 -0700458 * have to be in the first 256 MB of memory, since this is
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500459 * the maximum mapped by the Linux kernel during initialization.
460 */
Joe Hershberger10c26172011-10-11 23:57:25 -0500461 /* Initial Memory map for Linux*/
462#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500463
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200464#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500465
466#if 1 /*528/264*/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200467#define CONFIG_SYS_HRCW_LOW (\
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500468 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
469 HRCWL_DDR_TO_SCB_CLK_1X1 |\
470 HRCWL_CSB_TO_CLKIN |\
471 HRCWL_VCO_1X2 |\
472 HRCWL_CORE_TO_CSB_2X1)
473#elif 0 /*396/132*/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200474#define CONFIG_SYS_HRCW_LOW (\
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500475 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
476 HRCWL_DDR_TO_SCB_CLK_1X1 |\
477 HRCWL_CSB_TO_CLKIN |\
478 HRCWL_VCO_1X4 |\
479 HRCWL_CORE_TO_CSB_3X1)
480#elif 0 /*264/132*/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200481#define CONFIG_SYS_HRCW_LOW (\
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500482 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
483 HRCWL_DDR_TO_SCB_CLK_1X1 |\
484 HRCWL_CSB_TO_CLKIN |\
485 HRCWL_VCO_1X4 |\
486 HRCWL_CORE_TO_CSB_2X1)
487#elif 0 /*132/132*/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200488#define CONFIG_SYS_HRCW_LOW (\
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500489 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
490 HRCWL_DDR_TO_SCB_CLK_1X1 |\
491 HRCWL_CSB_TO_CLKIN |\
492 HRCWL_VCO_1X4 |\
493 HRCWL_CORE_TO_CSB_1X1)
494#elif 0 /*264/264 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200495#define CONFIG_SYS_HRCW_LOW (\
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500496 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
497 HRCWL_DDR_TO_SCB_CLK_1X1 |\
498 HRCWL_CSB_TO_CLKIN |\
499 HRCWL_VCO_1X4 |\
500 HRCWL_CORE_TO_CSB_1X1)
501#endif
502
503#if defined(PCI_64BIT)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200504#define CONFIG_SYS_HRCW_HIGH (\
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500505 HRCWH_PCI_HOST |\
506 HRCWH_64_BIT_PCI |\
507 HRCWH_PCI1_ARBITER_ENABLE |\
508 HRCWH_PCI2_ARBITER_DISABLE |\
509 HRCWH_CORE_ENABLE |\
510 HRCWH_FROM_0X00000100 |\
511 HRCWH_BOOTSEQ_DISABLE |\
512 HRCWH_SW_WATCHDOG_DISABLE |\
513 HRCWH_ROM_LOC_LOCAL_16BIT |\
514 HRCWH_TSEC1M_IN_GMII |\
Joe Hershberger10c26172011-10-11 23:57:25 -0500515 HRCWH_TSEC2M_IN_GMII)
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500516#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200517#define CONFIG_SYS_HRCW_HIGH (\
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500518 HRCWH_PCI_HOST |\
519 HRCWH_32_BIT_PCI |\
520 HRCWH_PCI1_ARBITER_ENABLE |\
521 HRCWH_PCI2_ARBITER_ENABLE |\
522 HRCWH_CORE_ENABLE |\
523 HRCWH_FROM_0X00000100 |\
524 HRCWH_BOOTSEQ_DISABLE |\
525 HRCWH_SW_WATCHDOG_DISABLE |\
526 HRCWH_ROM_LOC_LOCAL_16BIT |\
527 HRCWH_TSEC1M_IN_GMII |\
Joe Hershberger10c26172011-10-11 23:57:25 -0500528 HRCWH_TSEC2M_IN_GMII)
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500529#endif
530
531/* System IO Config */
Kim Phillipsf91cad62009-06-05 14:11:33 -0500532#define CONFIG_SYS_SICRH 0
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200533#define CONFIG_SYS_SICRL SICRL_LDP_A
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500534
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200535#define CONFIG_SYS_HID0_INIT 0x000000000
Joe Hershberger10c26172011-10-11 23:57:25 -0500536#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \
537 | HID0_ENABLE_INSTRUCTION_CACHE)
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500538
Joe Hershberger10c26172011-10-11 23:57:25 -0500539/* #define CONFIG_SYS_HID0_FINAL (\
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500540 HID0_ENABLE_INSTRUCTION_CACHE |\
541 HID0_ENABLE_M_BIT |\
Joe Hershberger10c26172011-10-11 23:57:25 -0500542 HID0_ENABLE_ADDRESS_BROADCAST) */
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500543
544
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200545#define CONFIG_SYS_HID2 HID2_HBE
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500546
Becky Bruce03ea1be2008-05-08 19:02:12 -0500547#define CONFIG_HIGH_BATS 1 /* High BATs supported */
548
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500549/* DDR @ 0x00000000 */
Joe Hershberger10c26172011-10-11 23:57:25 -0500550#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
Joe Hershbergerbfd89732011-10-11 23:57:28 -0500551 | BATL_PP_RW \
Joe Hershberger10c26172011-10-11 23:57:25 -0500552 | BATL_MEMCOHERENCE)
553#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
554 | BATU_BL_256M \
555 | BATU_VS \
556 | BATU_VP)
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500557
558/* PCI @ 0x80000000 */
559#ifdef CONFIG_PCI
Gabor Juhosb4458732013-05-30 07:06:12 +0000560#define CONFIG_PCI_INDIRECT_BRIDGE
Joe Hershberger10c26172011-10-11 23:57:25 -0500561#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \
Joe Hershbergerbfd89732011-10-11 23:57:28 -0500562 | BATL_PP_RW \
Joe Hershberger10c26172011-10-11 23:57:25 -0500563 | BATL_MEMCOHERENCE)
564#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
565 | BATU_BL_256M \
566 | BATU_VS \
567 | BATU_VP)
568#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
Joe Hershbergerbfd89732011-10-11 23:57:28 -0500569 | BATL_PP_RW \
Joe Hershberger10c26172011-10-11 23:57:25 -0500570 | BATL_CACHEINHIBIT \
571 | BATL_GUARDEDSTORAGE)
572#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
573 | BATU_BL_256M \
574 | BATU_VS \
575 | BATU_VP)
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500576#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200577#define CONFIG_SYS_IBAT1L (0)
578#define CONFIG_SYS_IBAT1U (0)
579#define CONFIG_SYS_IBAT2L (0)
580#define CONFIG_SYS_IBAT2U (0)
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500581#endif
582
583#ifdef CONFIG_MPC83XX_PCI2
Joe Hershberger10c26172011-10-11 23:57:25 -0500584#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \
Joe Hershbergerbfd89732011-10-11 23:57:28 -0500585 | BATL_PP_RW \
Joe Hershberger10c26172011-10-11 23:57:25 -0500586 | BATL_MEMCOHERENCE)
587#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \
588 | BATU_BL_256M \
589 | BATU_VS \
590 | BATU_VP)
591#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \
Joe Hershbergerbfd89732011-10-11 23:57:28 -0500592 | BATL_PP_RW \
Joe Hershberger10c26172011-10-11 23:57:25 -0500593 | BATL_CACHEINHIBIT \
594 | BATL_GUARDEDSTORAGE)
595#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \
596 | BATU_BL_256M \
597 | BATU_VS \
598 | BATU_VP)
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500599#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200600#define CONFIG_SYS_IBAT3L (0)
601#define CONFIG_SYS_IBAT3U (0)
602#define CONFIG_SYS_IBAT4L (0)
603#define CONFIG_SYS_IBAT4U (0)
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500604#endif
605
606/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
Joe Hershberger10c26172011-10-11 23:57:25 -0500607#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
Joe Hershbergerbfd89732011-10-11 23:57:28 -0500608 | BATL_PP_RW \
Joe Hershberger10c26172011-10-11 23:57:25 -0500609 | BATL_CACHEINHIBIT \
610 | BATL_GUARDEDSTORAGE)
611#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
612 | BATU_BL_256M \
613 | BATU_VS \
614 | BATU_VP)
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500615
Joe Hershbergerf05b9332011-10-11 23:57:30 -0500616/* LBC SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
617#define CONFIG_SYS_IBAT6L (CONFIG_SYS_LBC_SDRAM_BASE \
Joe Hershbergerbfd89732011-10-11 23:57:28 -0500618 | BATL_PP_RW \
Joe Hershberger10c26172011-10-11 23:57:25 -0500619 | BATL_MEMCOHERENCE \
620 | BATL_GUARDEDSTORAGE)
Joe Hershbergerf05b9332011-10-11 23:57:30 -0500621#define CONFIG_SYS_IBAT6U (CONFIG_SYS_LBC_SDRAM_BASE \
622 | BATU_BL_256M \
623 | BATU_VS \
624 | BATU_VP)
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500625
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200626#define CONFIG_SYS_IBAT7L (0)
627#define CONFIG_SYS_IBAT7U (0)
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500628
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200629#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
630#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
631#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
632#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
633#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
634#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
635#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
636#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
637#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
638#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
639#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
640#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
641#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
642#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
643#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
644#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500645
Jon Loeliger1f166a22007-07-04 22:30:58 -0500646#if defined(CONFIG_CMD_KGDB)
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500647#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500648#endif
649
650/*
651 * Environment Configuration
652 */
653#define CONFIG_ENV_OVERWRITE
654
655#if defined(CONFIG_TSEC_ENET)
Andy Fleming458c3892007-08-16 16:35:02 -0500656#define CONFIG_HAS_ETH0
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500657#define CONFIG_HAS_ETH1
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500658#endif
659
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500660#define CONFIG_HOSTNAME SBC8349
Joe Hershberger257ff782011-10-13 13:03:47 +0000661#define CONFIG_ROOTPATH "/tftpboot/rootfs"
Joe Hershbergere4da2482011-10-13 13:03:48 +0000662#define CONFIG_BOOTFILE "uImage"
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500663
Joe Hershberger10c26172011-10-11 23:57:25 -0500664 /* default location for tftp and bootm */
665#define CONFIG_LOADADDR 800000
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500666
667#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
Joe Hershberger10c26172011-10-11 23:57:25 -0500668#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500669
670#define CONFIG_BAUDRATE 115200
671
672#define CONFIG_EXTRA_ENV_SETTINGS \
673 "netdev=eth0\0" \
Detlev Zundel027fa492008-04-18 14:50:01 +0200674 "hostname=sbc8349\0" \
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500675 "nfsargs=setenv bootargs root=/dev/nfs rw " \
676 "nfsroot=${serverip}:${rootpath}\0" \
677 "ramargs=setenv bootargs root=/dev/ram rw\0" \
678 "addip=setenv bootargs ${bootargs} " \
679 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
680 ":${hostname}:${netdev}:off panic=1\0" \
681 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
682 "flash_nfs=run nfsargs addip addtty;" \
683 "bootm ${kernel_addr}\0" \
684 "flash_self=run ramargs addip addtty;" \
685 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
686 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
687 "bootm\0" \
688 "load=tftp 100000 /tftpboot/sbc8349/u-boot.bin\0" \
Paul Gortmaker80b4bb72009-07-23 17:10:55 -0400689 "update=protect off ff800000 ff83ffff; " \
Joe Hershberger10c26172011-10-11 23:57:25 -0500690 "era ff800000 ff83ffff; cp.b 100000 ff800000 ${filesize}\0" \
Detlev Zundel406e5782008-03-06 16:45:53 +0100691 "upd=run load update\0" \
Kim Phillipsfd3a3fc2009-08-21 16:34:38 -0500692 "fdtaddr=780000\0" \
Detlev Zundel027fa492008-04-18 14:50:01 +0200693 "fdtfile=sbc8349.dtb\0" \
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500694 ""
695
Joe Hershberger10c26172011-10-11 23:57:25 -0500696#define CONFIG_NFSBOOTCOMMAND \
697 "setenv bootargs root=/dev/nfs rw " \
698 "nfsroot=$serverip:$rootpath " \
699 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
700 "$netdev:off " \
701 "console=$consoledev,$baudrate $othbootargs;" \
702 "tftp $loadaddr $bootfile;" \
703 "tftp $fdtaddr $fdtfile;" \
704 "bootm $loadaddr - $fdtaddr"
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500705
706#define CONFIG_RAMBOOTCOMMAND \
Joe Hershberger10c26172011-10-11 23:57:25 -0500707 "setenv bootargs root=/dev/ram rw " \
708 "console=$consoledev,$baudrate $othbootargs;" \
709 "tftp $ramdiskaddr $ramdiskfile;" \
710 "tftp $loadaddr $bootfile;" \
711 "tftp $fdtaddr $fdtfile;" \
712 "bootm $loadaddr $ramdiskaddr $fdtaddr"
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500713
714#define CONFIG_BOOTCOMMAND "run flash_self"
715
716#endif /* __CONFIG_H */