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git01.mediatek.com / filogic / uboot / 1f5a510b6878e737ffd997eb8ea38e8a257cf417 / . / arch / arm / dts / zynqmp-e-a2197-00-revA.dts
blob: bf7569c6dda57124d8b852ff0bbb1700e1be3dcf [file] [log] [blame]
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * dts file for Xilinx Versal a2197 RevA System Controller
4 *
Saeed Nowshadi1aed3dd2023-09-11 16:10:48 +0200[diff] [blame]5 * (C) Copyright 2019 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]7 *
Michal Simeka8c94362023-07-10 14:35:49 +0200[diff] [blame]8 * Michal Simek <michal.simek@amd.com>
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]9 */
10/dts-v1/;
11
12#include "zynqmp.dtsi"
13#include "zynqmp-clk-ccf.dtsi"
14#include <dt-bindings/gpio/gpio.h>
15#include <dt-bindings/phy/phy.h>
16
17/ {
18 model = "Versal System Controller on a2197 Eval board RevA"; /* VCK190/VMK180 */
19 compatible = "xlnx,zynqmp-e-a2197-00-revA", "xlnx,zynqmp-a2197-revA",
20 "xlnx,zynqmp-a2197", "xlnx,zynqmp";
21
22 aliases {
23 ethernet0 = &gem0;
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]24 i2c0 = &i2c0;
25 i2c1 = &i2c1;
26 mmc0 = &sdhci1;
Michal Simek53b145d2021-06-03 11:46:50 +0200[diff] [blame]27 nvmem0 = &eeprom;
Michal Simek9f6222f2021-09-24 15:04:57 +0200[diff] [blame]28 nvmem1 = &eeprom_ebm;
29 nvmem2 = &eeprom_fmc1;
30 nvmem3 = &eeprom_fmc2;
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]31 rtc0 = &rtc;
32 serial0 = &uart0;
33 serial1 = &dcc;
34 };
35
36 chosen {
37 bootargs = "earlycon";
38 stdout-path = "serial0:115200n8";
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]39 };
40
41 memory@0 {
42 device_type = "memory";
43 reg = <0x0 0x0 0x0 0x80000000>;
44 };
45
Michal Simek51321682022-05-11 11:52:52 +0200[diff] [blame]46 si5332_1: si5332_1 { /* u142 - GEM0 */
47 compatible = "fixed-clock";
48 #clock-cells = <0>;
49 clock-frequency = <125000000>;
50 };
51
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]52 ina226-vccint {
53 compatible = "iio-hwmon";
54 io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;
55 };
56 ina226-vcc-soc {
57 compatible = "iio-hwmon";
58 io-channels = <&vcc_soc 0>, <&vcc_soc 1>, <&vcc_soc 2>, <&vcc_soc 3>;
59 };
60 ina226-vcc-pmc {
61 compatible = "iio-hwmon";
62 io-channels = <&vcc_pmc 0>, <&vcc_pmc 1>, <&vcc_pmc 2>, <&vcc_pmc 3>;
63 };
64 ina226-vcc-ram {
65 compatible = "iio-hwmon";
66 io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>;
67 };
68 ina226-vcc-pslp {
69 compatible = "iio-hwmon";
70 io-channels = <&vcc_pslp 0>, <&vcc_pslp 1>, <&vcc_pslp 2>, <&vcc_pslp 3>;
71 };
72 ina226-vcc-psfp {
73 compatible = "iio-hwmon";
74 io-channels = <&vcc_psfp 0>, <&vcc_psfp 1>, <&vcc_psfp 2>, <&vcc_psfp 3>;
75 };
76 ina226-vccaux {
77 compatible = "iio-hwmon";
78 io-channels = <&vccaux 0>, <&vccaux 1>, <&vccaux 2>, <&vccaux 3>;
79 };
80 ina226-vccaux-pmc {
81 compatible = "iio-hwmon";
82 io-channels = <&vccaux_pmc 0>, <&vccaux_pmc 1>, <&vccaux_pmc 2>, <&vccaux_pmc 3>;
83 };
84 ina226-vcco-500 {
85 compatible = "iio-hwmon";
86 io-channels = <&vcco_500 0>, <&vcco_500 1>, <&vcco_500 2>, <&vcco_500 3>;
87 };
88 ina226-vcco-501 {
89 compatible = "iio-hwmon";
90 io-channels = <&vcco_501 0>, <&vcco_501 1>, <&vcco_501 2>, <&vcco_501 3>;
91 };
92 ina226-vcco-502 {
93 compatible = "iio-hwmon";
94 io-channels = <&vcco_502 0>, <&vcco_502 1>, <&vcco_502 2>, <&vcco_502 3>;
95 };
96 ina226-vcco-503 {
97 compatible = "iio-hwmon";
98 io-channels = <&vcco_503 0>, <&vcco_503 1>, <&vcco_503 2>, <&vcco_503 3>;
99 };
100 ina226-vcc-1v8 {
101 compatible = "iio-hwmon";
102 io-channels = <&vcc_1v8 0>, <&vcc_1v8 1>, <&vcc_1v8 2>, <&vcc_1v8 3>;
103 };
104 ina226-vcc-3v3 {
105 compatible = "iio-hwmon";
106 io-channels = <&vcc_3v3 0>, <&vcc_3v3 1>, <&vcc_3v3 2>, <&vcc_3v3 3>;
107 };
108 ina226-vcc-1v2-ddr4 {
109 compatible = "iio-hwmon";
110 io-channels = <&vcc_1v2_ddr4 0>, <&vcc_1v2_ddr4 1>, <&vcc_1v2_ddr4 2>, <&vcc_1v2_ddr4 3>;
111 };
112 ina226-vcc-1v1-lp4 {
113 compatible = "iio-hwmon";
114 io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>;
115 };
116 ina226-vadj-fmc {
117 compatible = "iio-hwmon";
118 io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;
119 };
120 ina226-mgtyavcc {
121 compatible = "iio-hwmon";
122 io-channels = <&mgtyavcc 0>, <&mgtyavcc 1>, <&mgtyavcc 2>, <&mgtyavcc 3>;
123 };
124 ina226-mgtyavtt {
125 compatible = "iio-hwmon";
126 io-channels = <&mgtyavtt 0>, <&mgtyavtt 1>, <&mgtyavtt 2>, <&mgtyavtt 3>;
127 };
128 ina226-mgtyvccaux {
129 compatible = "iio-hwmon";
130 io-channels = <&mgtyvccaux 0>, <&mgtyvccaux 1>, <&mgtyvccaux 2>, <&mgtyvccaux 3>;
131 };
132};
133
134&uart0 { /* uart0 MIO38-39 */
135 status = "okay";
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]136};
137
138&sdhci1 { /* sd1 MIO45-51 cd in place */
139 status = "okay";
140 no-1-8-v;
141 disable-wp;
Michal Simek3b662642020-07-22 17:42:43 +0200[diff] [blame]142 xlnx,mio-bank = <1>;
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]143};
144
Michal Simek51321682022-05-11 11:52:52 +0200[diff] [blame]145/* GEM SGMII */
146&psgtr {
147 status = "okay";
148 /* gem0 */
149 clocks = <&si5332_1>;
150 clock-names = "ref0";
151};
152
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]153&gem0 {
154 status = "okay";
Michal Simek51321682022-05-11 11:52:52 +0200[diff] [blame]155 phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>;
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]156 phy-handle = <&phy0>;
157 phy-mode = "sgmii";
158 is-internal-pcspma;
Michal Simek8acb6b72022-09-06 12:39:11 +0200[diff] [blame]159 mdio: mdio {
160 #address-cells = <1>;
161 #size-cells = <0>;
162 phy0: ethernet-phy@0 { /* u131 M88E1512 */
163 reg = <0>;
164 };
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]165 };
166};
167
168&gpio {
169 status = "okay";
170 gpio-line-names = "", "", "", "", "", /* 0 - 4 */
171 "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */
172 "DC_SYS_CTRL3", "ZU4_TRIGGER", "SYSCTLR_PB", "", "", /* 10 - 14 */
173 "", "", "", "", "", /* 15 - 19 */
174 "", "", "", "", "", /* 20 - 24 */
175 "", "", "", "", "", /* 25 - 29 */
176 "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */
177 "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */
178 "", "", "ETH_RESET_B", "", "", /* 40 - 44 */
179 "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */
180 "SD1_CMD", "SD1_CLK", "", "", "", /* 50 - 54 */
181 "", "", "", "", "", /* 55 - 59 */
182 "", "", "", "", "", /* 60 - 64 */
183 "", "", "", "", "", /* 65 - 69 */
184 "", "", "", "", "", /* 70 - 74 */
185 "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */
Saeed Nowshadi893180e2020-03-27 08:12:20 -0700[diff] [blame]186 "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */
Saeed Nowshadi342c3cd2021-04-13 16:01:42 -0700[diff] [blame]187 "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "", /* 80 - 84 */
188 "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "", /* 85 - 89 */
189 "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */
190 "SYSCTLR_GPIO5", "", "", "", "", /* 95 - 99 */
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]191 "", "", "", "", "", /* 100 - 104 */
192 "", "", "", "", "", /* 105 - 109 */
193 "", "", "", "", "", /* 110 - 114 */
194 "", "", "", "", "", /* 115 - 119 */
195 "", "", "", "", "", /* 120 - 124 */
196 "", "", "", "", "", /* 125 - 129 */
Saeed Nowshadi342c3cd2021-04-13 16:01:42 -0700[diff] [blame]197 "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "", "", "", /* 130 - 134 */
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]198 "", "", "", "", "", /* 135 - 139 */
Saeed Nowshadi342c3cd2021-04-13 16:01:42 -0700[diff] [blame]199 "PMBUS_ALERT", "", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */
200 "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]201 "", "", "", "", "", /* 150 - 154 */
202 "", "", "", "", "", /* 155 - 159 */
203 "", "", "", "", "", /* 160 - 164 */
204 "", "", "", "", "", /* 165 - 169 */
Michal Simekfdf3fc62023-07-10 14:37:31 +0200[diff] [blame]205 "", "", "", ""; /* 170 - 173 */
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]206};
207
208&i2c0 { /* MIO 34-35 - can't stay here */
209 status = "okay";
210 clock-frequency = <400000>;
Michal Simeka43fdcd2022-08-23 15:00:25 +0200[diff] [blame]211
212 tca6416_u233: gpio@20 { /* u233 */
213 compatible = "ti,tca6416";
214 reg = <0x20>;
215 gpio-controller; /* interrupt not connected */
216 #gpio-cells = <2>;
217 gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "", "", /* 0 - 3 */
218 "PMBUS2_INA226_ALERT", "", "", "MAX6643_FULLSPD", /* 4 - 7 */
219 "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 10 - 13 */
220 "VCCINT_VRHOT_B", "8A34001_EXP_RST_B", "PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */
221 };
222
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]223 i2c-mux@74 { /* u33 */
224 compatible = "nxp,pca9548";
225 #address-cells = <1>;
226 #size-cells = <0>;
227 reg = <0x74>;
228 /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
229 i2c@0 { /* PMBUS */
230 #address-cells = <1>;
231 #size-cells = <0>;
232 reg = <0>;
233 /* u152 IR35215 0x16/0x46 vcc_soc */
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]234 /* u179 ir38164 0x19/0x49 vcco_500 */
235 /* u181 ir38164 0x1a/0x4a vcco_501 */
236 /* u183 ir38164 0x1b/0x4b vcco_502 */
237 /* u185 ir38164 0x1e/0x4e vadj_fmc */
238 /* u187 ir38164 0x1F/0x4f mgtyavcc */
239 /* u189 ir38164 0x20/0x50 mgtyavtt */
240 /* u194 ir38164 0x13/0x43 vdd1_1v8_lp4 */
241 /* u195 ir38164 0x14/0x44 vdd2_1v8_lp4 */
Michal Simek3514e4e2020-03-30 11:35:38 +0200[diff] [blame]242
243 irps5401_47: irps5401@47 { /* IRPS5401 - u160 */
244 compatible = "infineon,irps5401";
245 reg = <0x47>; /* pmbus / i2c 0x17 */
246 };
247 irps5401_4c: irps5401@4c { /* IRPS5401 - u167 */
248 compatible = "infineon,irps5401";
249 reg = <0x4c>; /* pmbus / i2c 0x1c */
250 };
251 irps5401_4d: irps5401@4d { /* IRPS5401 - u175 */
252 compatible = "infineon,irps5401";
253 reg = <0x4d>; /* pmbus / i2c 0x1d */
254 };
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]255 };
256 i2c@1 { /* PMBUS1_INA226 */
257 #address-cells = <1>;
258 #size-cells = <0>;
259 reg = <1>;
260 /* FIXME check alerts coming to SC */
261 vccint: ina226@40 { /* u65 */
262 compatible = "ti,ina226";
263 #io-channel-cells = <1>;
264 label = "ina226-vccint";
265 reg = <0x40>;
Saeed Nowshadi34cd5f82020-08-03 23:24:05 -0700[diff] [blame]266 shunt-resistor = <500>; /* R440 */
267 /* 0.80V @ 32A 1 of 6 Phases*/
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]268 };
269 vcc_soc: ina226@41 { /* u161 */
270 compatible = "ti,ina226";
271 #io-channel-cells = <1>;
272 label = "ina226-vcc-soc";
273 reg = <0x41>;
Saeed Nowshadi34cd5f82020-08-03 23:24:05 -0700[diff] [blame]274 shunt-resistor = <500>; /* R1702 */
275 /* 0.80V @ 18A */
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]276 };
277 vcc_pmc: ina226@42 { /* u163 */
278 compatible = "ti,ina226";
279 #io-channel-cells = <1>;
280 label = "ina226-vcc-pmc";
281 reg = <0x42>;
282 shunt-resistor = <5000>; /* R1214 */
283 /* 0.78V @ 500mA */
284 };
285 vcc_ram: ina226@43 { /* u162 */
286 compatible = "ti,ina226";
287 #io-channel-cells = <1>;
288 label = "ina226-vcc-ram";
289 reg = <0x43>;
290 shunt-resistor = <5000>; /* r1221 */
291 /* 0.78V @ 4A */
292 };
293 vcc_pslp: ina226@44 { /* u165 */
294 compatible = "ti,ina226";
295 #io-channel-cells = <1>;
296 label = "ina226-vcc-pslp";
297 reg = <0x44>;
298 shunt-resistor = <5000>; /* R1216 */
299 /* 0.78V @ 1A */
300 };
301 vcc_psfp: ina226@45 { /* u164 */
302 compatible = "ti,ina226";
303 #io-channel-cells = <1>;
304 label = "ina226-vcc-psfp";
305 reg = <0x45>;
306 shunt-resistor = <5000>; /* R1219 */
307 /* 0.78V @ 2A */
308 };
309 };
310 i2c@2 { /* PCIE_CLK */
311 #address-cells = <1>;
312 #size-cells = <0>;
313 reg = <2>;
Michal Simekd42dec02022-06-15 11:56:54 +0200[diff] [blame]314 clock_8t49n287: clock-generator@6c { /* u39 8T49N240 */
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]315 #clock-cells = <1>; /* author David Cater <david.cater@idt.com>*/
316 compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */
Michal Simekd42dec02022-06-15 11:56:54 +0200[diff] [blame]317 reg = <0x6c>;
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]318 /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */
319 /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */
320 };
321 };
322 i2c@3 { /* PMBUS2_INA226 */
323 #address-cells = <1>;
324 #size-cells = <0>;
325 reg = <3>;
326 /* FIXME check alerts coming to SC */
327 vccaux: ina226@40 { /* u166 */
328 compatible = "ti,ina226";
329 #io-channel-cells = <1>;
330 label = "ina226-vccaux";
331 reg = <0x40>;
332 shunt-resistor = <5000>; /* R382 */
333 /* 1.5V @ 3A */
334 };
335 vccaux_pmc: ina226@41 { /* u168 */
336 compatible = "ti,ina226";
337 #io-channel-cells = <1>;
338 label = "ina226-vccaux-pmc";
339 reg = <0x41>;
340 shunt-resistor = <5000>; /* R1246 */
341 /* 1.5V @ 500mA */
342 };
343 vcco_500: ina226@42 { /* u178 */
344 compatible = "ti,ina226";
345 #io-channel-cells = <1>;
346 label = "ina226-vcco-500";
347 reg = <0x42>;
348 shunt-resistor = <2000>; /* R1300 */
349 /* 3.3V @ 5A */
350 };
351 vcco_501: ina226@43 { /* u180 */
352 compatible = "ti,ina226";
353 #io-channel-cells = <1>;
354 label = "ina226-vcco-501";
355 reg = <0x43>;
356 shunt-resistor = <2000>; /* R1313 */
357 /* 3.3V @ 5A */
358 };
359 vcco_502: ina226@44 { /* u182 */
360 compatible = "ti,ina226";
361 #io-channel-cells = <1>;
362 label = "ina226-vcco-502";
363 reg = <0x44>;
364 shunt-resistor = <2000>; /* R1330 */
365 /* 3.3V @ 5A */
366 };
367 vcco_503: ina226@45 { /* u172 */
368 compatible = "ti,ina226";
369 #io-channel-cells = <1>;
370 label = "ina226-vcco-503";
371 reg = <0x45>;
372 shunt-resistor = <5000>; /* R1229 */
373 /* 1.8V @ 2A */
374 };
375 vcc_1v8: ina226@46 { /* u173 */
376 compatible = "ti,ina226";
377 #io-channel-cells = <1>;
378 label = "ina226-vcc-1v8";
379 reg = <0x46>;
380 shunt-resistor = <5000>; /* R400 */
381 /* 1.8V @ 6A */
382 };
383 vcc_3v3: ina226@47 { /* u174 */
384 compatible = "ti,ina226";
385 #io-channel-cells = <1>;
386 label = "ina226-vcc-3v3";
387 reg = <0x47>;
388 shunt-resistor = <5000>; /* R1232 */
389 /* 3.3V @ 500mA */
390 };
391 vcc_1v2_ddr4: ina226@48 { /* u176 */
392 compatible = "ti,ina226";
393 #io-channel-cells = <1>;
394 label = "ina226-vcc-1v2-ddr4";
395 reg = <0x48>;
396 shunt-resistor = <5000>; /* R1275 */
397 /* 1.2V @ 4A */
398 };
399 vcc1v1_lp4: ina226@49 { /* u177 */
400 compatible = "ti,ina226";
401 #io-channel-cells = <1>;
402 label = "ina226-vcc1v1-lp4";
403 reg = <0x49>;
404 shunt-resistor = <5000>; /* R1286 */
405 /* 1.1V @ 4A */
406 };
407 vadj_fmc: ina226@4a { /* u184 */
408 compatible = "ti,ina226";
409 #io-channel-cells = <1>;
410 label = "ina226-vadj-fmc";
411 reg = <0x4a>;
412 shunt-resistor = <2000>; /* R1350 */
413 /* 1.5V @ 10A */
414 };
415 mgtyavcc: ina226@4b { /* u186 */
416 compatible = "ti,ina226";
417 #io-channel-cells = <1>;
418 label = "ina226-mgtyavcc";
419 reg = <0x4b>;
420 shunt-resistor = <2000>; /* R1367 */
421 /* 0.88V @ 6A */
422 };
423 mgtyavtt: ina226@4c { /* u188 */
424 compatible = "ti,ina226";
425 #io-channel-cells = <1>;
426 label = "ina226-mgtyavtt";
427 reg = <0x4c>;
428 shunt-resistor = <2000>; /* R1384 */
429 /* 1.2V @ 10A */
430 };
431 mgtyvccaux: ina226@4d { /* u234 */
432 compatible = "ti,ina226";
433 #io-channel-cells = <1>;
434 label = "ina226-mgtyvccaux";
435 reg = <0x4d>;
436 shunt-resistor = <5000>; /* r1679 */
437 /* 1.5V @ 500mA */
438 };
439 };
440 i2c@4 { /* LP_I2C_SM */
441 #address-cells = <1>;
442 #size-cells = <0>;
443 reg = <4>;
444 /* FIXME wires ready but chip is missing */
445 };
446 i2c@5 { /* zSFP_SI570 */
447 #address-cells = <1>;
448 #size-cells = <0>;
449 reg = <5>;
450 si570_zsfp: clock-generator@5d { /* u192 */
451 #clock-cells = <0>;
452 compatible = "silabs,si570";
453 reg = <0x5d>;
454 temperature-stability = <50>;
455 factory-fout = <156250000>;
456 clock-frequency = <156250000>;
Saeed Nowshadi9a34a4b2020-03-04 10:21:34 -0800[diff] [blame]457 clock-output-names = "si570_zsfp_clk";
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]458 };
459 };
460 i2c@6 { /* USER_SI570_1 */
461 #address-cells = <1>;
462 #size-cells = <0>;
463 reg = <6>;
Saeed Nowshadi1aed3dd2023-09-11 16:10:48 +0200[diff] [blame]464 si570_user1: clock-generator@5f { /* u205 */
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]465 #clock-cells = <0>;
466 compatible = "silabs,si570";
Saeed Nowshadi1aed3dd2023-09-11 16:10:48 +0200[diff] [blame]467 reg = <0x5f>;
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]468 temperature-stability = <50>;
469 factory-fout = <100000000>;
470 clock-frequency = <100000000>;
471 clock-output-names = "si570_user1";
472 };
473
474 };
475 i2c@7 { /* USER_SI570_2 */
476 #address-cells = <1>;
477 #size-cells = <0>;
478 reg = <7>;
479 /* FIXME wires ready but chip is missing */
480 };
481 };
482};
483
484&i2c1 { /* i2c1 MIO 36-37 */
485 status = "okay";
486 clock-frequency = <400000>;
487
488 i2c-mux@74 { /* u35 */
489 compatible = "nxp,pca9548";
490 #address-cells = <1>;
491 #size-cells = <0>;
492 reg = <0x74>;
Raviteja Narayanam574fa192021-04-01 07:14:10 -0600[diff] [blame]493 i2c-mux-idle-disconnect;
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]494 /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */
495 dc_i2c: i2c@0 { /* DC_I2C */
496 #address-cells = <1>;
497 #size-cells = <0>;
498 reg = <0>;
499 /* Use for storing information about SC board */
500 eeprom: eeprom@54 { /* u34 - m24128 16kB */
501 compatible = "st,24c128", "atmel,24c128";
502 reg = <0x54>; /* 0x5c too */
503 };
504 si570_ref_clk: clock-generator@5d { /* u32 */
505 #clock-cells = <0>;
506 compatible = "silabs,si570";
507 reg = <0x5d>;
508 temperature-stability = <50>;
509 factory-fout = <33333333>;
510 clock-frequency = <33333333>;
511 clock-output-names = "ref_clk";
Michal Simekf86d2b52021-03-09 12:43:42 +0100[diff] [blame]512 silabs,skip-recall;
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]513 };
514 /* and connector J212D */
Michal Simek9f6222f2021-09-24 15:04:57 +0200[diff] [blame]515 eeprom_ebm: eeprom@52 { /* x-ebm module */
516 compatible = "st,24c128", "atmel,24c128";
517 reg = <0x52>;
518 };
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]519 };
520 fmc1: i2c@1 { /* FMCP1_IIC */
521 #address-cells = <1>;
522 #size-cells = <0>;
523 reg = <1>;
524 /* FIXME connection to Samtec J51C */
525 /* expected eeprom 0x50 FMC cards */
Michal Simek9f6222f2021-09-24 15:04:57 +0200[diff] [blame]526 eeprom_fmc1: eeprom@50 {
527 compatible = "st,24c128", "atmel,24c128";
528 reg = <0x50>;
529 };
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]530 };
531 fmc2: i2c@2 { /* FMCP2_IIC */
532 #address-cells = <1>;
533 #size-cells = <0>;
534 reg = <2>;
535 /* FIXME connection to Samtec J53C */
536 /* expected eeprom 0x50 FMC cards */
Michal Simek9f6222f2021-09-24 15:04:57 +0200[diff] [blame]537 eeprom_fmc2: eeprom@50 {
538 compatible = "st,24c128", "atmel,24c128";
539 reg = <0x50>;
540 };
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]541 };
542 i2c@3 { /* DDR4_DIMM1 */
543 #address-cells = <1>;
544 #size-cells = <0>;
545 reg = <3>;
546 si570_ddr_dimm1: clock-generator@60 { /* u2 */
547 #clock-cells = <0>;
548 compatible = "silabs,si570";
549 reg = <0x60>;
550 temperature-stability = <50>;
551 factory-fout = <200000000>;
552 clock-frequency = <200000000>;
553 clock-output-names = "si570_ddrdimm1_clk";
Saeed Nowshadi35a2cd62021-03-22 11:58:38 -0700[diff] [blame]554 silabs,skip-recall;
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]555 };
556 };
557 i2c@4 { /* LPDDR4_SI570_CLK2 */
558 #address-cells = <1>;
559 #size-cells = <0>;
560 reg = <4>;
Saeed Nowshadi9a34a4b2020-03-04 10:21:34 -0800[diff] [blame]561 si570_lpddr4clk2: clock-generator@60 { /* u3 */
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]562 #clock-cells = <0>;
563 compatible = "silabs,si570";
564 reg = <0x60>;
565 temperature-stability = <50>;
566 factory-fout = <200000000>;
567 clock-frequency = <200000000>;
568 clock-output-names = "si570_lpddr4_clk2";
569 };
570 };
571 i2c@5 { /* LPDDR4_SI570_CLK1 */
572 #address-cells = <1>;
573 #size-cells = <0>;
574 reg = <5>;
Saeed Nowshadi9a34a4b2020-03-04 10:21:34 -0800[diff] [blame]575 si570_lpddr4clk1: clock-generator@60 { /* u4 */
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]576 #clock-cells = <0>;
577 compatible = "silabs,si570";
578 reg = <0x60>;
579 temperature-stability = <50>;
580 factory-fout = <200000000>;
581 clock-frequency = <200000000>;
582 clock-output-names = "si570_lpddr4_clk1";
583 };
584 };
585 i2c@6 { /* HSDP_SI570 */
586 #address-cells = <1>;
587 #size-cells = <0>;
588 reg = <6>;
589 si570_hsdp: clock-generator@5d { /* u5 */
590 #clock-cells = <0>;
591 compatible = "silabs,si570";
592 reg = <0x5d>;
593 temperature-stability = <50>;
594 factory-fout = <156250000>;
595 clock-frequency = <156250000>;
596 clock-output-names = "si570_hsdp_clk";
597 };
598 };
599 i2c@7 { /* 8A34001 - U219B and J310 connector */
600 #address-cells = <1>;
601 #size-cells = <0>;
602 reg = <7>;
603 };
604 };
Saeed Nowshadic06192e2020-08-03 23:24:04 -0700[diff] [blame]605 i2c-mux@75 { /* u214 */
606 compatible = "nxp,pca9548";
607 #address-cells = <1>;
608 #size-cells = <0>;
609 reg = <0x75>;
Raviteja Narayanam574fa192021-04-01 07:14:10 -0600[diff] [blame]610 i2c-mux-idle-disconnect;
Saeed Nowshadic06192e2020-08-03 23:24:04 -0700[diff] [blame]611 i2c@0 { /* SFP0_IIC */
612 #address-cells = <1>;
613 #size-cells = <0>;
614 reg = <0>;
615 /* SFP0 */
616 };
617 i2c@1 { /* SFP1_IIC */
618 #address-cells = <1>;
619 #size-cells = <0>;
620 reg = <1>;
621 /* SFP1 */
622 };
623 i2c@2 { /* QSFP1_I2C */
624 #address-cells = <1>;
625 #size-cells = <0>;
626 reg = <2>;
627 /* QSFP1 */
628 };
629 /* 3 - 7 unused */
630 };
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]631};
632
633&xilinx_ams {
634 status = "okay";
635};
636
637&ams_ps {
638 status = "okay";
639};
640
641&ams_pl {
642 status = "okay";
643};