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git01.mediatek.com / filogic / uboot / 1f5a510b6878e737ffd997eb8ea38e8a257cf417 / . / arch / arm / dts / imx8mm-cl-iot-gate-u-boot.dtsi
blob: 219504f61105d12854cd17a05051bb60d54587b8 [file] [log] [blame]
Ying-Chun Liu (PaulLiu)01600c12021-04-22 04:50:30 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2019 NXP
4 */
5
Marcel Ziswiler9888e122021-10-23 01:15:12 +0200[diff] [blame]6#include "imx8mm-u-boot.dtsi"
7
Ying-Chun Liu (PaulLiu)01600c12021-04-22 04:50:30 +0800[diff] [blame]8/ {
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]9 wdt-reboot {
10 compatible = "wdt-reboot";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]11 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]12 wdt = <&wdog1>;
13 };
Ying-Chun Liu (PaulLiu)01600c12021-04-22 04:50:30 +0800[diff] [blame]14};
15
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]16&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b} {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]17 bootph-pre-ram;
Ying-Chun Liu (PaulLiu)01600c12021-04-22 04:50:30 +0800[diff] [blame]18};
19
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]20&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b/regulators} {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]21 bootph-pre-ram;
Ying-Chun Liu (PaulLiu)01600c12021-04-22 04:50:30 +0800[diff] [blame]22};
23
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]24&fec1 {
25 phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
26};
27
28&gpio1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]29 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]30};
31
32&gpio2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]33 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]34};
35
36&gpio3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]37 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]38};
39
40&gpio4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]41 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]42};
43
44&gpio5 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]45 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]46};
47
48&i2c1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]49 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]50};
51
52&i2c2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]53 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]54};
55
56&pinctrl_i2c2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]57 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]58};
59
60&pinctrl_pmic {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]61 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]62};
63
64&pinctrl_uart3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]65 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]66};
67
68&pinctrl_usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]69 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]70};
71
72&pinctrl_usdhc2_gpio {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]73 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]74};
75
76&pinctrl_usdhc3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]77 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]78};
79
Peng Fan83a9b282022-06-11 20:21:03 +0800[diff] [blame]80&pinctrl_wdog {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]81 bootph-pre-ram;
Peng Fan83a9b282022-06-11 20:21:03 +0800[diff] [blame]82};
83
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]84&uart3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]85 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]86};
87
88&usdhc1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]89 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]90};
91
92&usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]93 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]94};
95
96&usdhc3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]97 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]98};
99
100&wdog1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]101 bootph-pre-ram;
Marcel Ziswilerec7b9e82021-10-23 01:15:11 +0200[diff] [blame]102};