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Bo Shen42aafb32012-07-05 17:21:46 +00001/*
2 * Copyright (C) 2012 Atmel Corporation
3 *
4 * Configuation settings for the AT91SAM9X5EK board.
5 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Bo Shen42aafb32012-07-05 17:21:46 +00007 */
8
9#ifndef __CONFIG_H__
10#define __CONFIG_H__
11
12#include <asm/hardware.h>
13
Bo Shen337a2d82013-08-13 14:50:49 +080014#define CONFIG_SYS_TEXT_BASE 0x26f00000
15
Bo Shen42aafb32012-07-05 17:21:46 +000016/* ARM asynchronous clock */
17#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
18#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
Bo Shen42aafb32012-07-05 17:21:46 +000019
20#define CONFIG_AT91SAM9X5EK
Bo Shen42aafb32012-07-05 17:21:46 +000021
Bo Shen42aafb32012-07-05 17:21:46 +000022#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
23#define CONFIG_SETUP_MEMORY_TAGS
24#define CONFIG_INITRD_TAG
25#define CONFIG_SKIP_LOWLEVEL_INIT
Bo Shen42aafb32012-07-05 17:21:46 +000026
27/* general purpose I/O */
28#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
Bo Shen42aafb32012-07-05 17:21:46 +000029
30/* LCD */
Bo Shen42aafb32012-07-05 17:21:46 +000031#define LCD_BPP LCD_COLOR16
32#define LCD_OUTPUT_BPP 24
33#define CONFIG_LCD_LOGO
Bo Shen42aafb32012-07-05 17:21:46 +000034#define CONFIG_LCD_INFO
35#define CONFIG_LCD_INFO_BELOW_LOGO
Bo Shen42aafb32012-07-05 17:21:46 +000036#define CONFIG_ATMEL_HLCD
37#define CONFIG_ATMEL_LCD_RGB565
Bo Shen42aafb32012-07-05 17:21:46 +000038
Bo Shen42aafb32012-07-05 17:21:46 +000039
40/*
41 * BOOTP options
42 */
43#define CONFIG_BOOTP_BOOTFILESIZE
44#define CONFIG_BOOTP_BOOTPATH
45#define CONFIG_BOOTP_GATEWAY
46#define CONFIG_BOOTP_HOSTNAME
47
48/*
Tom Riniceed5d22017-05-12 22:33:27 -040049 * define CONFIG_USB_EHCI_HCD to enable USB Hi-Speed (aka 2.0)
Richard Genoud1e34e832012-11-29 23:18:34 +000050 * NB: in this case, USB 1.1 devices won't be recognized.
51 */
52
Bo Shen42aafb32012-07-05 17:21:46 +000053/* SDRAM */
54#define CONFIG_NR_DRAM_BANKS 1
55#define CONFIG_SYS_SDRAM_BASE 0x20000000
56#define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */
57
58#define CONFIG_SYS_INIT_SP_ADDR \
Wenyou Yangf345e282017-04-18 14:51:54 +080059 (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
Bo Shen42aafb32012-07-05 17:21:46 +000060
61/* DataFlash */
Bo Shen4a73e582012-08-19 20:32:24 +000062#ifdef CONFIG_CMD_SF
Bo Shen4a73e582012-08-19 20:32:24 +000063#define CONFIG_SF_DEFAULT_SPEED 30000000
Bo Shen42aafb32012-07-05 17:21:46 +000064#endif
65
Bo Shen42aafb32012-07-05 17:21:46 +000066/* NAND flash */
67#ifdef CONFIG_CMD_NAND
68#define CONFIG_NAND_ATMEL
69#define CONFIG_SYS_MAX_NAND_DEVICE 1
70#define CONFIG_SYS_NAND_BASE 0x40000000
71#define CONFIG_SYS_NAND_DBW_8 1
72/* our ALE is AD21 */
73#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
74/* our CLE is AD22 */
75#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
76#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4
77#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5
78
Tom Rini00448d22017-07-28 21:31:42 -040079#define CONFIG_MTD_DEVICE
80#define CONFIG_MTD_PARTITIONS
81#endif
82
Wu, Joshdd359a12012-08-23 00:05:38 +000083/* PMECC & PMERRLOC */
84#define CONFIG_ATMEL_NAND_HWECC 1
85#define CONFIG_ATMEL_NAND_HW_PMECC 1
86#define CONFIG_PMECC_CAP 2
87#define CONFIG_PMECC_SECTOR_SIZE 512
Wu, Joshdd359a12012-08-23 00:05:38 +000088
Richard Genoud1e34e832012-11-29 23:18:34 +000089/* USB */
90#ifdef CONFIG_CMD_USB
Tom Riniceed5d22017-05-12 22:33:27 -040091#ifndef CONFIG_USB_EHCI_HCD
Bo Shen4a985df2013-10-21 16:14:00 +080092#define CONFIG_USB_ATMEL
93#define CONFIG_USB_ATMEL_CLK_SEL_UPLL
Richard Genoud1e34e832012-11-29 23:18:34 +000094#define CONFIG_USB_OHCI_NEW
95#define CONFIG_SYS_USB_OHCI_CPU_INIT
96#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI
97#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9x5"
98#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3
99#endif
Richard Genoud1e34e832012-11-29 23:18:34 +0000100#endif
101
Bo Shen42aafb32012-07-05 17:21:46 +0000102#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
103
104#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
105#define CONFIG_SYS_MEMTEST_END 0x26e00000
106
107#ifdef CONFIG_SYS_USE_NANDFLASH
108/* bootstrap + u-boot + env + linux in nandflash */
Wenyou Yangf345e282017-04-18 14:51:54 +0800109#define CONFIG_ENV_OFFSET 0x120000
Bo Shen42aafb32012-07-05 17:21:46 +0000110#define CONFIG_ENV_OFFSET_REDUND 0x100000
111#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
112#define CONFIG_BOOTCOMMAND "nand read " \
113 "0x22000000 0x200000 0x300000; " \
114 "bootm 0x22000000"
Wu, Josh9d681892012-11-02 00:17:27 +0000115#elif defined(CONFIG_SYS_USE_SPIFLASH)
Bo Shen4a73e582012-08-19 20:32:24 +0000116/* bootstrap + u-boot + env + linux in spi flash */
Bo Shen4a73e582012-08-19 20:32:24 +0000117#define CONFIG_ENV_OFFSET 0x5000
118#define CONFIG_ENV_SIZE 0x3000
119#define CONFIG_ENV_SECT_SIZE 0x1000
120#define CONFIG_ENV_SPI_MAX_HZ 30000000
121#define CONFIG_BOOTCOMMAND "sf probe 0; " \
122 "sf read 0x22000000 0x100000 0x300000; " \
123 "bootm 0x22000000"
Bo Shen0a9f8ac2012-12-06 21:37:04 +0000124#elif defined(CONFIG_SYS_USE_DATAFLASH)
125/* bootstrap + u-boot + env + linux in data flash */
Bo Shen0a9f8ac2012-12-06 21:37:04 +0000126#define CONFIG_ENV_OFFSET 0x4200
127#define CONFIG_ENV_SIZE 0x4200
128#define CONFIG_ENV_SECT_SIZE 0x210
129#define CONFIG_ENV_SPI_MAX_HZ 30000000
130#define CONFIG_BOOTCOMMAND "sf probe 0; " \
131 "sf read 0x22000000 0x84000 0x294000; " \
132 "bootm 0x22000000"
Wu, Josh9d681892012-11-02 00:17:27 +0000133#else /* CONFIG_SYS_USE_MMC */
134/* bootstrap + u-boot + env + linux in mmc */
Wu, Joshdf0ef742015-01-20 10:33:33 +0800135#define CONFIG_ENV_SIZE 0x4000
Bo Shen42aafb32012-07-05 17:21:46 +0000136#endif
137
Wu, Josh9d681892012-11-02 00:17:27 +0000138#ifdef CONFIG_SYS_USE_MMC
Bo Shen42aafb32012-07-05 17:21:46 +0000139#define CONFIG_BOOTARGS "mem=128M console=ttyS0,115200 " \
140 "mtdparts=atmel_nand:" \
141 "8M(bootstrap/uboot/kernel)ro,-(rootfs) " \
Wu, Josh9d681892012-11-02 00:17:27 +0000142 "root=/dev/mmcblk0p2 " \
143 "rw rootfstype=ext4 rootwait"
144#else
Bo Shena8fd0632013-02-20 00:16:25 +0000145#define CONFIG_BOOTARGS \
146 "console=ttyS0,115200 earlyprintk " \
147 "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \
148 "256k(env),256k(env_redundant),256k(spare)," \
149 "512k(dtb),6M(kernel)ro,-(rootfs) " \
150 "rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs rw"
Wu, Josh9d681892012-11-02 00:17:27 +0000151#endif
Bo Shen42aafb32012-07-05 17:21:46 +0000152
Bo Shen42aafb32012-07-05 17:21:46 +0000153#define CONFIG_SYS_CBSIZE 256
154#define CONFIG_SYS_MAXARGS 16
Bo Shen42aafb32012-07-05 17:21:46 +0000155#define CONFIG_SYS_LONGHELP
156#define CONFIG_CMDLINE_EDITING
157#define CONFIG_AUTO_COMPLETE
Bo Shen42aafb32012-07-05 17:21:46 +0000158
159/*
160 * Size of malloc() pool
161 */
162#define CONFIG_SYS_MALLOC_LEN (512 * 1024 + 0x1000)
163
Bo Shen9a3b1fe2015-03-27 14:23:35 +0800164/* SPL */
165#define CONFIG_SPL_FRAMEWORK
166#define CONFIG_SPL_TEXT_BASE 0x300000
167#define CONFIG_SPL_MAX_SIZE 0x6000
168#define CONFIG_SPL_STACK 0x308000
169
170#define CONFIG_SPL_BSS_START_ADDR 0x20000000
171#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
172#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
173#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
174
Bo Shen9a3b1fe2015-03-27 14:23:35 +0800175#define CONFIG_SYS_MONITOR_LEN (512 << 10)
176
177#define CONFIG_SYS_MASTER_CLOCK 132096000
178#define CONFIG_SYS_AT91_PLLA 0x20c73f03
179#define CONFIG_SYS_MCKR 0x1301
180#define CONFIG_SYS_MCKR_CSS 0x1302
181
Bo Shen9a3b1fe2015-03-27 14:23:35 +0800182#ifdef CONFIG_SYS_USE_MMC
183#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
Bo Shen9a3b1fe2015-03-27 14:23:35 +0800184#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
185#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
Bo Shen9a3b1fe2015-03-27 14:23:35 +0800186
187#elif CONFIG_SYS_USE_NANDFLASH
Bo Shen9a3b1fe2015-03-27 14:23:35 +0800188#define CONFIG_SPL_NAND_DRIVERS
189#define CONFIG_SPL_NAND_BASE
190#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
191#define CONFIG_SYS_NAND_5_ADDR_CYCLE
192#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
193#define CONFIG_SYS_NAND_PAGE_COUNT 64
194#define CONFIG_SYS_NAND_OOBSIZE 64
195#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
196#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
197#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
198
199#elif CONFIG_SYS_USE_SPIFLASH
Bo Shen9a3b1fe2015-03-27 14:23:35 +0800200#define CONFIG_SPL_SPI_LOAD
201#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8400
202
203#endif
204
Bo Shen42aafb32012-07-05 17:21:46 +0000205#endif