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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Albert Aribaudacc41ff2010-06-17 19:38:21 +05302/*
Albert ARIBAUD340983d2011-04-22 19:41:02 +02003 * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
Albert Aribaudacc41ff2010-06-17 19:38:21 +05304 *
5 * Based on original Kirkwood support which is
6 * (C) Copyright 2009
7 * Marvell Semiconductor <www.marvell.com>
8 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
Albert Aribaudacc41ff2010-06-17 19:38:21 +05309 */
10
11#ifndef _CONFIG_EDMINIV2_H
12#define _CONFIG_EDMINIV2_H
13
14/*
Albert ARIBAUD2ac37922015-01-31 22:55:38 +010015 * SPL
16 */
17
Albert ARIBAUD2ac37922015-01-31 22:55:38 +010018#define CONFIG_SPL_MAX_SIZE 0x0000fff0
19#define CONFIG_SPL_STACK 0x00020000
20#define CONFIG_SPL_BSS_START_ADDR 0x00020000
21#define CONFIG_SPL_BSS_MAX_SIZE 0x0001ffff
22#define CONFIG_SYS_SPL_MALLOC_START 0x00040000
23#define CONFIG_SYS_SPL_MALLOC_SIZE 0x0001ffff
Albert ARIBAUD2ac37922015-01-31 22:55:38 +010024#define CONFIG_SYS_UBOOT_BASE 0xfff90000
25#define CONFIG_SYS_UBOOT_START 0x00800000
Albert ARIBAUD2ac37922015-01-31 22:55:38 +010026
27/*
Albert Aribaudacc41ff2010-06-17 19:38:21 +053028 * High Level Configuration Options (easy to change)
29 */
30
Lei Wen749941a2011-10-24 16:27:32 +000031#include <asm/arch/orion5x.h>
Albert Aribaudacc41ff2010-06-17 19:38:21 +053032/*
33 * CLKs configurations
34 */
35
Albert Aribaudacc41ff2010-06-17 19:38:21 +053036/*
37 * Board-specific values for Orion5x MPP low level init:
38 * - MPPs 12 to 15 are SATA LEDs (mode 5)
39 * - Others are GPIO/unused (mode 3 for MPP0, mode 5 for
40 * MPP16 to MPP19, mode 0 for others
41 */
42
43#define ORION5X_MPP0_7 0x00000003
44#define ORION5X_MPP8_15 0x55550000
Albert Aribaud26137d02010-08-08 05:17:06 +053045#define ORION5X_MPP16_23 0x00005555
Albert Aribaudacc41ff2010-06-17 19:38:21 +053046
47/*
48 * Board-specific values for Orion5x GPIO low level init:
49 * - GPIO3 is input (RTC interrupt)
50 * - GPIO16 is Power LED control (0 = on, 1 = off)
51 * - GPIO17 is Power LED source select (0 = CPLD, 1 = GPIO16)
52 * - GPIO18 is Power Button status (0 = Released, 1 = Pressed)
Albert ARIBAUDdea1cfb2012-08-16 06:35:21 +000053 * - GPIO19 is SATA disk power toggle (toggles on 0-to-1)
54 * - GPIO22 is SATA disk power status ()
55 * - GPIO23 is supply status for SATA disk ()
56 * - GPIO24 is supply control for board (write 1 to power off)
57 * Last GPIO is 25, further bits are supposed to be 0.
Albert Aribaudacc41ff2010-06-17 19:38:21 +053058 * Enable mask has ones for INPUT, 0 for OUTPUT.
Albert ARIBAUDdea1cfb2012-08-16 06:35:21 +000059 * Default is LED ON, board ON :)
Albert Aribaudacc41ff2010-06-17 19:38:21 +053060 */
61
Albert ARIBAUDdea1cfb2012-08-16 06:35:21 +000062#define ORION5X_GPIO_OUT_ENABLE 0xfef4f0ca
63#define ORION5X_GPIO_OUT_VALUE 0x00000000
64#define ORION5X_GPIO_IN_POLARITY 0x000000d0
Albert Aribaudacc41ff2010-06-17 19:38:21 +053065
66/*
67 * NS16550 Configuration
68 */
69
Albert Aribaudacc41ff2010-06-17 19:38:21 +053070#define CONFIG_SYS_NS16550_SERIAL
71#define CONFIG_SYS_NS16550_REG_SIZE (-4)
72#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK
73#define CONFIG_SYS_NS16550_COM1 ORION5X_UART0_BASE
74
75/*
76 * Serial Port configuration
77 * The following definitions let you select what serial you want to use
78 * for your console driver.
79 */
80
Albert Aribaudacc41ff2010-06-17 19:38:21 +053081#define CONFIG_SYS_BAUDRATE_TABLE \
82 { 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 }
83
84/*
85 * FLASH configuration
86 */
87
Albert Aribaudacc41ff2010-06-17 19:38:21 +053088#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
89#define CONFIG_SYS_MAX_FLASH_SECT 11 /* max num of sects on one chip */
90#define CONFIG_SYS_FLASH_BASE 0xfff80000
Albert Aribaudacc41ff2010-06-17 19:38:21 +053091
92/* auto boot */
Albert Aribaudacc41ff2010-06-17 19:38:21 +053093
Albert Aribaudacc41ff2010-06-17 19:38:21 +053094#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */
Albert Aribaudc5b205b2010-07-12 22:24:30 +020095
Albert Aribaudacc41ff2010-06-17 19:38:21 +053096/*
Albert Aribaudc5b205b2010-07-12 22:24:30 +020097 * Network
Albert Aribaudacc41ff2010-06-17 19:38:21 +053098 */
Albert Aribaudc5b205b2010-07-12 22:24:30 +020099
100#ifdef CONFIG_CMD_NET
Albert Aribaudc5b205b2010-07-12 22:24:30 +0200101#define CONFIG_MVGBE_PORTS {1} /* enable port 0 only */
102#define CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION /* don't randomize MAC */
103#define CONFIG_PHY_BASE_ADR 0x8
104#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */
Albert Aribaudc5b205b2010-07-12 22:24:30 +0200105#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
Albert Aribaudc5b205b2010-07-12 22:24:30 +0200106#endif
Albert Aribaudacc41ff2010-06-17 19:38:21 +0530107
108/*
Albert Aribaud26137d02010-08-08 05:17:06 +0530109 * IDE
110 */
Simon Glassb569a012017-05-17 03:25:30 -0600111#ifdef CONFIG_IDE
Albert Aribaud26137d02010-08-08 05:17:06 +0530112#define __io
Albert Aribaud26137d02010-08-08 05:17:06 +0530113/* Data, registers and alternate blocks are at the same offset */
114#define CONFIG_SYS_ATA_DATA_OFFSET (0x0100)
115#define CONFIG_SYS_ATA_REG_OFFSET (0x0100)
116#define CONFIG_SYS_ATA_ALT_OFFSET (0x0100)
117/* Each 8-bit ATA register is aligned to a 4-bytes address */
118#define CONFIG_SYS_ATA_STRIDE 4
119/* Controller supports 48-bits LBA addressing */
120#define CONFIG_LBA48
121/* A single bus, a single device */
122#define CONFIG_SYS_IDE_MAXBUS 1
123#define CONFIG_SYS_IDE_MAXDEVICE 1
124/* ATA registers base is at SATA controller base */
125#define CONFIG_SYS_ATA_BASE_ADDR ORION5X_SATA_BASE
126/* ATA bus 0 is orion5x port 1 on ED Mini V2 */
127#define CONFIG_SYS_ATA_IDE0_OFFSET ORION5X_SATA_PORT1_OFFSET
128/* end of IDE defines */
129#endif /* CMD_IDE */
130
131/*
Albert ARIBAUD90bdece2012-01-15 22:08:41 +0000132 * Common USB/EHCI configuration
133 */
134#ifdef CONFIG_CMD_USB
Albert ARIBAUD90bdece2012-01-15 22:08:41 +0000135#define ORION5X_USB20_HOST_PORT_BASE ORION5X_USB20_PORT0_BASE
Albert ARIBAUD90bdece2012-01-15 22:08:41 +0000136#endif /* CONFIG_CMD_USB */
137
138/*
Albert Aribaud81c99812010-08-27 18:26:06 +0200139 * I2C related stuff
140 */
141#ifdef CONFIG_CMD_I2C
Paul Kocialkowski2fae3e72015-04-10 23:09:51 +0200142#define CONFIG_I2C_MVTWSI_BASE0 ORION5X_TWSI_BASE
Albert Aribaud81c99812010-08-27 18:26:06 +0200143#endif
144
145/*
Albert Aribaudacc41ff2010-06-17 19:38:21 +0530146 * Environment variables configurations
147 */
Albert Aribaudacc41ff2010-06-17 19:38:21 +0530148
Albert ARIBAUDc4d48a62012-02-06 20:32:19 +0530149/* Enable command line editing */
Albert ARIBAUDc4d48a62012-02-06 20:32:19 +0530150
151/* provide extensive help */
Albert ARIBAUDc4d48a62012-02-06 20:32:19 +0530152
Albert Aribauda2ddee42010-10-11 13:13:29 +0200153/* additions for new relocation code, must be added to all boards */
154#define CONFIG_SYS_SDRAM_BASE 0
155#define CONFIG_SYS_INIT_SP_ADDR \
Wolfgang Denk0191e472010-10-26 14:34:52 +0200156 (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
Albert Aribauda2ddee42010-10-11 13:13:29 +0200157
Albert Aribaudacc41ff2010-06-17 19:38:21 +0530158#endif /* _CONFIG_EDMINIV2_H */