blob: 9a34e5444b1c00c586cc5d074715017d0dcdbb73 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Kim Phillips1cb07e62008-01-16 00:38:05 -06002/*
3 * Copyright (C) 2007 Freescale Semiconductor, Inc.
4 * Kevin Lam <kevin.lam@freescale.com>
5 * Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
Kim Phillips1cb07e62008-01-16 00:38:05 -06006 */
7
8#ifndef __CONFIG_H
9#define __CONFIG_H
10
Simon Glassfb64e362020-05-10 11:40:09 -060011#include <linux/stringify.h>
12
Kim Phillips1cb07e62008-01-16 00:38:05 -060013/*
14 * High Level Configuration Options
15 */
16#define CONFIG_E300 1 /* E300 family */
Kim Phillips1cb07e62008-01-16 00:38:05 -060017
Anton Vorontsov3628a932009-06-10 00:25:30 +040018#define CONFIG_HWCONFIG
Timur Tabi3e1d49a2008-02-08 13:15:55 -060019
20/*
21 * On-board devices
22 */
Timur Tabi3e1d49a2008-02-08 13:15:55 -060023#define CONFIG_VSC7385_ENET
24
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020025/* System performance - define the value i.e. CONFIG_SYS_XXX
Kim Phillips1cb07e62008-01-16 00:38:05 -060026*/
27
Kim Phillips1cb07e62008-01-16 00:38:05 -060028/* System Clock Configuration Register */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020029#define CONFIG_SYS_SCCR_TSEC1CM 1 /* eTSEC1 clock mode (0-3) */
30#define CONFIG_SYS_SCCR_TSEC2CM 1 /* eTSEC2 clock mode (0-3) */
Joe Hershberger93831bb2011-10-11 23:57:19 -050031#define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* SATA1-4 clock mode (0-3) */
Kim Phillips1cb07e62008-01-16 00:38:05 -060032
33/*
34 * System IO Config
35 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020036#define CONFIG_SYS_SICRH 0x08200000
37#define CONFIG_SYS_SICRL 0x00000000
Kim Phillips1cb07e62008-01-16 00:38:05 -060038
39/*
40 * Output Buffer Impedance
41 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020042#define CONFIG_SYS_OBIR 0x30100000
Kim Phillips1cb07e62008-01-16 00:38:05 -060043
44/*
Timur Tabi3e1d49a2008-02-08 13:15:55 -060045 * Device configurations
46 */
47
48/* Vitesse 7385 */
49
50#ifdef CONFIG_VSC7385_ENET
51
52#define CONFIG_TSEC2
53
54/* The flash address and size of the VSC7385 firmware image */
55#define CONFIG_VSC7385_IMAGE 0xFE7FE000
56#define CONFIG_VSC7385_IMAGE_SIZE 8192
57
58#endif
59
60/*
Kim Phillips1cb07e62008-01-16 00:38:05 -060061 * DDR Setup
62 */
Mario Sixc9f92772019-01-21 09:18:15 +010063#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020064#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000
65#define CONFIG_SYS_83XX_DDR_USES_CS0
Kim Phillips1cb07e62008-01-16 00:38:05 -060066
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020067#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN)
Kim Phillips1cb07e62008-01-16 00:38:05 -060068
Kim Phillips1cb07e62008-01-16 00:38:05 -060069#undef CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */
70
71/*
72 * Manually set up DDR parameters
73 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020074#define CONFIG_SYS_DDR_SIZE 256 /* MB */
Joe Hershbergercc03b802011-10-11 23:57:29 -050075#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
76#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
77 | CSCONFIG_ODT_WR_ONLY_CURRENT \
78 | CSCONFIG_ROW_BIT_13 \
79 | CSCONFIG_COL_BIT_10)
Kim Phillips1cb07e62008-01-16 00:38:05 -060080
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020081#define CONFIG_SYS_DDR_TIMING_3 0x00000000
82#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
Kim Phillips1cb07e62008-01-16 00:38:05 -060083 | (0 << TIMING_CFG0_WRT_SHIFT) \
84 | (0 << TIMING_CFG0_RRT_SHIFT) \
85 | (0 << TIMING_CFG0_WWT_SHIFT) \
86 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
87 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
88 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
89 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
Kim Phillips1cb07e62008-01-16 00:38:05 -060090 /* 0x00260802 */ /* DDR400 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020091#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
Kim Phillips1cb07e62008-01-16 00:38:05 -060092 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
93 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
94 | (7 << TIMING_CFG1_CASLAT_SHIFT) \
95 | (13 << TIMING_CFG1_REFREC_SHIFT) \
96 | (3 << TIMING_CFG1_WRREC_SHIFT) \
97 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
98 | (2 << TIMING_CFG1_WRTORD_SHIFT))
Kim Phillips1cb07e62008-01-16 00:38:05 -060099 /* 0x3937d322 */
Joe Hershbergercc03b802011-10-11 23:57:29 -0500100#define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
101 | (5 << TIMING_CFG2_CPO_SHIFT) \
102 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
103 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
104 | (3 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
105 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
106 | (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
107 /* 0x02984cc8 */
Kim Phillips1cb07e62008-01-16 00:38:05 -0600108
Kim Phillips5202ba32009-08-21 16:33:15 -0500109#define CONFIG_SYS_DDR_INTERVAL ((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \
110 | (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
Kim Phillips1cb07e62008-01-16 00:38:05 -0600111 /* 0x06090100 */
112
Joe Hershberger93831bb2011-10-11 23:57:19 -0500113#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
Joe Hershbergercc03b802011-10-11 23:57:29 -0500114 | SDRAM_CFG_SDRAM_TYPE_DDR2)
Joe Hershberger93831bb2011-10-11 23:57:19 -0500115 /* 0x43000000 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200116#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */
Kim Phillips5202ba32009-08-21 16:33:15 -0500117#define CONFIG_SYS_DDR_MODE ((0x0406 << SDRAM_MODE_ESD_SHIFT) \
Joe Hershberger93831bb2011-10-11 23:57:19 -0500118 | (0x0442 << SDRAM_MODE_SD_SHIFT))
119 /* 0x04400442 */ /* DDR400 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200120#define CONFIG_SYS_DDR_MODE2 0x00000000
Kim Phillips1cb07e62008-01-16 00:38:05 -0600121
122/*
123 * Memory test
124 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200125#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
Kim Phillips1cb07e62008-01-16 00:38:05 -0600126
127/*
128 * The reserved memory
129 */
Wolfgang Denk0708bc62010-10-07 21:51:12 +0200130#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Kim Phillips1cb07e62008-01-16 00:38:05 -0600131
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200132#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
133#define CONFIG_SYS_RAMBOOT
Kim Phillips1cb07e62008-01-16 00:38:05 -0600134#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200135#undef CONFIG_SYS_RAMBOOT
Kim Phillips1cb07e62008-01-16 00:38:05 -0600136#endif
137
Kevin Hao349a0152016-07-08 11:25:14 +0800138#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
Kim Phillips1cb07e62008-01-16 00:38:05 -0600139
140/*
141 * Initial RAM Base Address Setup
142 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200143#define CONFIG_SYS_INIT_RAM_LOCK 1
144#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200145#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
Joe Hershberger93831bb2011-10-11 23:57:19 -0500146#define CONFIG_SYS_GBL_DATA_OFFSET \
147 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Kim Phillips1cb07e62008-01-16 00:38:05 -0600148
Kim Phillips1cb07e62008-01-16 00:38:05 -0600149/*
150 * FLASH on the Local Bus
151 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200152#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
153#define CONFIG_SYS_FLASH_SIZE 8 /* max FLASH size is 32M */
Kim Phillips1cb07e62008-01-16 00:38:05 -0600154
Joe Hershberger93831bb2011-10-11 23:57:19 -0500155#define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
Kim Phillips1cb07e62008-01-16 00:38:05 -0600156
Kim Phillips1cb07e62008-01-16 00:38:05 -0600157
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200158#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
159#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
Kim Phillips1cb07e62008-01-16 00:38:05 -0600160
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200161#undef CONFIG_SYS_FLASH_CHECKSUM
162#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
163#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Kim Phillips1cb07e62008-01-16 00:38:05 -0600164
Anton Vorontsovaf170452008-03-24 17:40:23 +0300165/*
166 * NAND Flash on the Local Bus
167 */
Joe Hershbergerf05b9332011-10-11 23:57:30 -0500168#define CONFIG_SYS_NAND_BASE 0xE0600000
Mario Sixc1e29d92019-01-21 09:18:01 +0100169
Mario Sixc1e29d92019-01-21 09:18:01 +0100170
Timur Tabi3e1d49a2008-02-08 13:15:55 -0600171/* Vitesse 7385 */
172
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200173#define CONFIG_SYS_VSC7385_BASE 0xF0000000
Kim Phillips1cb07e62008-01-16 00:38:05 -0600174
Kim Phillips1cb07e62008-01-16 00:38:05 -0600175/*
176 * Serial Port
177 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200178#define CONFIG_SYS_NS16550_SERIAL
179#define CONFIG_SYS_NS16550_REG_SIZE 1
180#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Kim Phillips1cb07e62008-01-16 00:38:05 -0600181
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200182#define CONFIG_SYS_BAUDRATE_TABLE \
Joe Hershberger93831bb2011-10-11 23:57:19 -0500183 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
Kim Phillips1cb07e62008-01-16 00:38:05 -0600184
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200185#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
186#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
Kim Phillips1cb07e62008-01-16 00:38:05 -0600187
Anton Vorontsov2b3c0042008-03-24 17:40:43 +0300188/* SERDES */
189#define CONFIG_FSL_SERDES
190#define CONFIG_FSL_SERDES1 0xe3000
191#define CONFIG_FSL_SERDES2 0xe3100
192
Kim Phillips1cb07e62008-01-16 00:38:05 -0600193/* I2C */
Heiko Schocherf2850742012-10-24 13:48:22 +0200194#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
Kim Phillips1cb07e62008-01-16 00:38:05 -0600195
196/*
197 * Config on-board RTC
198 */
199#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200200#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
Kim Phillips1cb07e62008-01-16 00:38:05 -0600201
202/*
203 * General PCI
204 * Addresses are mapped 1-1.
205 */
Joe Hershberger93831bb2011-10-11 23:57:19 -0500206#define CONFIG_SYS_PCI_MEM_BASE 0x80000000
207#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
208#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200209#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
210#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
211#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
212#define CONFIG_SYS_PCI_IO_BASE 0x00000000
213#define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
214#define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */
Kim Phillips1cb07e62008-01-16 00:38:05 -0600215
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200216#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
217#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
218#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
Kim Phillips1cb07e62008-01-16 00:38:05 -0600219
Anton Vorontsov45a30ee2009-02-19 18:20:52 +0300220#define CONFIG_SYS_PCIE1_BASE 0xA0000000
221#define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000
222#define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000
223#define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000
224#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000
225#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
226#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
227#define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000
228#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
229
230#define CONFIG_SYS_PCIE2_BASE 0xC0000000
231#define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000
232#define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000
233#define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000
234#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000
235#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
236#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
237#define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000
238#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
239
Kim Phillips1cb07e62008-01-16 00:38:05 -0600240#ifdef CONFIG_PCI
Kim Phillips1cb07e62008-01-16 00:38:05 -0600241#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Kim Phillips1cb07e62008-01-16 00:38:05 -0600242#endif /* CONFIG_PCI */
243
Kim Phillips1cb07e62008-01-16 00:38:05 -0600244/*
245 * TSEC
246 */
Timur Tabi3e1d49a2008-02-08 13:15:55 -0600247#ifdef CONFIG_TSEC_ENET
Kim Phillips1cb07e62008-01-16 00:38:05 -0600248
Timur Tabi3e1d49a2008-02-08 13:15:55 -0600249#define CONFIG_GMII /* MII PHY management */
250
251#define CONFIG_TSEC1
252
253#ifdef CONFIG_TSEC1
254#define CONFIG_HAS_ETH0
Kim Phillips1cb07e62008-01-16 00:38:05 -0600255#define CONFIG_TSEC1_NAME "TSEC0"
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200256#define CONFIG_SYS_TSEC1_OFFSET 0x24000
Kim Phillips1cb07e62008-01-16 00:38:05 -0600257#define TSEC1_PHY_ADDR 2
Kim Phillips1cb07e62008-01-16 00:38:05 -0600258#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
Kim Phillips1cb07e62008-01-16 00:38:05 -0600259#define TSEC1_PHYIDX 0
Timur Tabi3e1d49a2008-02-08 13:15:55 -0600260#endif
Kim Phillips1cb07e62008-01-16 00:38:05 -0600261
Timur Tabi3e1d49a2008-02-08 13:15:55 -0600262#ifdef CONFIG_TSEC2
263#define CONFIG_HAS_ETH1
264#define CONFIG_TSEC2_NAME "TSEC1"
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200265#define CONFIG_SYS_TSEC2_OFFSET 0x25000
Timur Tabi3e1d49a2008-02-08 13:15:55 -0600266#define TSEC2_PHY_ADDR 0x1c
267#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
268#define TSEC2_PHYIDX 0
269#endif
Kim Phillips1cb07e62008-01-16 00:38:05 -0600270
271/* Options are: TSEC[0-1] */
272#define CONFIG_ETHPRIME "TSEC0"
273
Timur Tabi3e1d49a2008-02-08 13:15:55 -0600274#endif
275
Kim Phillips1cb07e62008-01-16 00:38:05 -0600276/*
Kim Phillips0daba0e2008-03-28 14:31:23 -0500277 * SATA
278 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200279#define CONFIG_SYS_SATA_MAX_DEVICE 2
Kim Phillips0daba0e2008-03-28 14:31:23 -0500280#define CONFIG_SATA1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200281#define CONFIG_SYS_SATA1_OFFSET 0x18000
Joe Hershberger93831bb2011-10-11 23:57:19 -0500282#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
283#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
Kim Phillips0daba0e2008-03-28 14:31:23 -0500284#define CONFIG_SATA2
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200285#define CONFIG_SYS_SATA2_OFFSET 0x19000
Joe Hershberger93831bb2011-10-11 23:57:19 -0500286#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
287#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
Kim Phillips0daba0e2008-03-28 14:31:23 -0500288
289#ifdef CONFIG_FSL_SATA
290#define CONFIG_LBA48
Kim Phillips0daba0e2008-03-28 14:31:23 -0500291#endif
292
293/*
Kim Phillips1cb07e62008-01-16 00:38:05 -0600294 * Environment
295 */
Kim Phillips1cb07e62008-01-16 00:38:05 -0600296
297#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200298#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Kim Phillips1cb07e62008-01-16 00:38:05 -0600299
300/*
301 * BOOTP options
302 */
303#define CONFIG_BOOTP_BOOTFILESIZE
Kim Phillips1cb07e62008-01-16 00:38:05 -0600304
Anton Vorontsov3628a932009-06-10 00:25:30 +0400305#ifdef CONFIG_MMC
Chenhui Zhao025eab02011-01-04 17:23:05 +0800306#define CONFIG_FSL_ESDHC_PIN_MUX
Anton Vorontsov3628a932009-06-10 00:25:30 +0400307#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
Anton Vorontsov3628a932009-06-10 00:25:30 +0400308#endif
309
Kim Phillips1cb07e62008-01-16 00:38:05 -0600310/*
311 * Miscellaneous configurable options
312 */
Kim Phillips1cb07e62008-01-16 00:38:05 -0600313
Kim Phillips1cb07e62008-01-16 00:38:05 -0600314/*
315 * For booting Linux, the board info and command line data
Ira W. Snyderc5a22d02010-09-10 15:42:32 -0700316 * have to be in the first 256 MB of memory, since this is
Kim Phillips1cb07e62008-01-16 00:38:05 -0600317 * the maximum mapped by the Linux kernel during initialization.
318 */
Joe Hershberger93831bb2011-10-11 23:57:19 -0500319#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
Kevin Hao9c747962016-07-08 11:25:15 +0800320#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
Kim Phillips1cb07e62008-01-16 00:38:05 -0600321
Kim Phillips1cb07e62008-01-16 00:38:05 -0600322/*
323 * Environment Configuration
324 */
Kim Phillips1cb07e62008-01-16 00:38:05 -0600325
Anton Vorontsov07e60912008-03-14 23:20:18 +0300326#define CONFIG_HAS_FSL_DR_USB
Nikhil Badolac4cff522014-10-20 16:31:01 +0530327#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
Anton Vorontsov07e60912008-03-14 23:20:18 +0300328
Joe Hershberger93831bb2011-10-11 23:57:19 -0500329#define CONFIG_NETDEV "eth1"
Kim Phillips1cb07e62008-01-16 00:38:05 -0600330
Mario Six790d8442018-03-28 14:38:20 +0200331#define CONFIG_HOSTNAME "mpc837x_rdb"
Joe Hershberger257ff782011-10-13 13:03:47 +0000332#define CONFIG_ROOTPATH "/nfsroot"
Joe Hershberger93831bb2011-10-11 23:57:19 -0500333#define CONFIG_RAMDISKFILE "rootfs.ext2.gz.uboot"
Joe Hershbergere4da2482011-10-13 13:03:48 +0000334#define CONFIG_BOOTFILE "uImage"
Joe Hershberger93831bb2011-10-11 23:57:19 -0500335 /* U-Boot image on TFTP server */
336#define CONFIG_UBOOTPATH "u-boot.bin"
337#define CONFIG_FDTFILE "mpc8379_rdb.dtb"
Kim Phillips1cb07e62008-01-16 00:38:05 -0600338
Kim Phillips1cb07e62008-01-16 00:38:05 -0600339#define CONFIG_EXTRA_ENV_SETTINGS \
Joe Hershberger93831bb2011-10-11 23:57:19 -0500340 "netdev=" CONFIG_NETDEV "\0" \
341 "uboot=" CONFIG_UBOOTPATH "\0" \
Kim Phillips1cb07e62008-01-16 00:38:05 -0600342 "tftpflash=tftp $loadaddr $uboot;" \
Marek Vasut0b3176c2012-09-23 17:41:24 +0200343 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
344 " +$filesize; " \
345 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
346 " +$filesize; " \
347 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
348 " $filesize; " \
349 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
350 " +$filesize; " \
351 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
352 " $filesize\0" \
Kim Phillipsfd3a3fc2009-08-21 16:34:38 -0500353 "fdtaddr=780000\0" \
Joe Hershberger93831bb2011-10-11 23:57:19 -0500354 "fdtfile=" CONFIG_FDTFILE "\0" \
Kim Phillips1cb07e62008-01-16 00:38:05 -0600355 "ramdiskaddr=1000000\0" \
Joe Hershberger93831bb2011-10-11 23:57:19 -0500356 "ramdiskfile=" CONFIG_RAMDISKFILE "\0" \
Kim Phillips1cb07e62008-01-16 00:38:05 -0600357 "console=ttyS0\0" \
358 "setbootargs=setenv bootargs " \
359 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
360 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
Joe Hershberger93831bb2011-10-11 23:57:19 -0500361 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
362 "$netdev:off " \
Kim Phillips1cb07e62008-01-16 00:38:05 -0600363 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
364
Kim Phillips1cb07e62008-01-16 00:38:05 -0600365#endif /* __CONFIG_H */