Heiko Schocher | a1d7c2d | 2008-01-11 15:15:15 +0100 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2007 |
| 3 | * Heiko Schocher, DENX Software Engineering, hs@denx.de. |
| 4 | * |
Wolfgang Denk | bd8ec7e | 2013-10-07 13:07:26 +0200 | [diff] [blame] | 5 | * SPDX-License-Identifier: GPL-2.0+ |
Heiko Schocher | a1d7c2d | 2008-01-11 15:15:15 +0100 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #ifndef __CONFIG_H |
| 9 | #define __CONFIG_H |
| 10 | /* |
| 11 | * High Level Configuration Options |
| 12 | * (easy to change) |
| 13 | */ |
Masahiro Yamada | 608ed2c | 2014-01-16 11:03:07 +0900 | [diff] [blame] | 14 | #define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ |
Heiko Schocher | a1d7c2d | 2008-01-11 15:15:15 +0100 | [diff] [blame] | 15 | #define CONFIG_MPC5200_DDR 1 /* (with DDR-SDRAM) */ |
| 16 | #define CONFIG_MUNICES 1 /* ... on MUNICes board */ |
Wolfgang Denk | 291ba1b | 2010-10-06 09:05:45 +0200 | [diff] [blame] | 17 | |
| 18 | #ifndef CONFIG_SYS_TEXT_BASE |
| 19 | #define CONFIG_SYS_TEXT_BASE 0xFFF00000 |
| 20 | #endif |
| 21 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 22 | #define CONFIG_SYS_MPC5XXX_CLKIN 33333333 /* ... running at 33.333333MHz */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 23 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ |
Becky Bruce | 03ea1be | 2008-05-08 19:02:12 -0500 | [diff] [blame] | 24 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
Heiko Schocher | a1d7c2d | 2008-01-11 15:15:15 +0100 | [diff] [blame] | 25 | |
| 26 | /* |
| 27 | * Command line configuration. |
| 28 | */ |
Heiko Schocher | a1d7c2d | 2008-01-11 15:15:15 +0100 | [diff] [blame] | 29 | #define CONFIG_CMD_REGINFO |
| 30 | |
Jean-Christophe PLAGNIOL-VILLARD | 4134872 | 2008-01-25 07:54:47 +0100 | [diff] [blame] | 31 | #if defined(CONFIG_CMD_KGDB) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 32 | # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
Heiko Schocher | a1d7c2d | 2008-01-11 15:15:15 +0100 | [diff] [blame] | 33 | #endif |
| 34 | |
| 35 | /* |
| 36 | * Serial console configuration |
| 37 | */ |
| 38 | #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 39 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } |
Heiko Schocher | a1d7c2d | 2008-01-11 15:15:15 +0100 | [diff] [blame] | 40 | |
| 41 | #define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */ |
Heiko Schocher | a1d7c2d | 2008-01-11 15:15:15 +0100 | [diff] [blame] | 42 | #undef CONFIG_BOOTARGS |
| 43 | |
| 44 | #define CONFIG_PREBOOT "echo;" \ |
| 45 | "echo Type \"run net_nfs\" to load Kernel over TFTP and to mount root filesystem over NFS;" \ |
| 46 | "echo" |
| 47 | |
| 48 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 49 | "netdev=eth0\0" \ |
| 50 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ |
| 51 | "nfsroot=$(serverip):$(rootpath)\0" \ |
| 52 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ |
| 53 | "addip=setenv bootargs $(bootargs) " \ |
| 54 | "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ |
| 55 | ":$(hostname):$(netdev):off panic=5\0" \ |
| 56 | "flash_nfs=run nfsargs addip;" \ |
| 57 | "bootm $(kernel_addr)\0" \ |
| 58 | "flash_self=run ramargs addip;" \ |
| 59 | "bootm $(kernel_addr) $(ramdisk_addr)\0" \ |
| 60 | "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \ |
| 61 | "rootpath=/opt/eldk/ppc_6xx\0" \ |
| 62 | "bootfile=/tftpboot/munices/u-boot.bin\0" \ |
| 63 | "update=tftpboot 200000 ${bootfile};protect off fff00000 fff3ffff;" \ |
| 64 | "erase fff00000 fff3ffff; cp.b 200000 FFF00000 ${filesize}\0" \ |
| 65 | "" |
| 66 | #define CONFIG_BOOTCOMMAND "run net_nfs" |
| 67 | |
| 68 | /* |
| 69 | * IPB Bus clocking configuration. |
| 70 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 71 | #define CONFIG_SYS_IPBSPEED_133 /* define for 133MHz speed */ |
| 72 | #if defined(CONFIG_SYS_IPBSPEED_133) |
Heiko Schocher | a1d7c2d | 2008-01-11 15:15:15 +0100 | [diff] [blame] | 73 | /* |
| 74 | * PCI Bus clocking configuration |
| 75 | * |
| 76 | * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 77 | * CONFIG_SYS_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't |
Heiko Schocher | a1d7c2d | 2008-01-11 15:15:15 +0100 | [diff] [blame] | 78 | * been tested with a IPB Bus Clock of 66 MHz. |
| 79 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 80 | #define CONFIG_SYS_PCISPEED_66 /* define for 66MHz speed */ |
Heiko Schocher | a1d7c2d | 2008-01-11 15:15:15 +0100 | [diff] [blame] | 81 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 82 | #undef CONFIG_SYS_PCISPEED_66 /* for 33MHz speed */ |
Heiko Schocher | a1d7c2d | 2008-01-11 15:15:15 +0100 | [diff] [blame] | 83 | #endif |
| 84 | |
| 85 | /* |
| 86 | * Memory map |
| 87 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 88 | #define CONFIG_SYS_MBAR 0xF0000000 /* MBAR hast to be switched by other bootloader or debugger config */ |
Heiko Schocher | 9a8118b | 2008-01-11 15:15:16 +0100 | [diff] [blame] | 89 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 90 | #define CONFIG_SYS_DEFAULT_MBAR 0x80000000 |
| 91 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
Heiko Schocher | a1d7c2d | 2008-01-11 15:15:15 +0100 | [diff] [blame] | 92 | /* Use SRAM until RAM will be available */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 93 | #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM |
Wolfgang Denk | 1c2e98e | 2010-10-26 13:32:32 +0200 | [diff] [blame] | 94 | #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */ |
Wolfgang Denk | 0191e47 | 2010-10-26 14:34:52 +0200 | [diff] [blame] | 95 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 96 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
Heiko Schocher | a1d7c2d | 2008-01-11 15:15:15 +0100 | [diff] [blame] | 97 | |
Wolfgang Denk | 0708bc6 | 2010-10-07 21:51:12 +0200 | [diff] [blame] | 98 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 99 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
| 100 | # define CONFIG_SYS_RAMBOOT 1 |
Heiko Schocher | a1d7c2d | 2008-01-11 15:15:15 +0100 | [diff] [blame] | 101 | #endif |
| 102 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 103 | #define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ |
| 104 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
| 105 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
Heiko Schocher | a1d7c2d | 2008-01-11 15:15:15 +0100 | [diff] [blame] | 106 | |
| 107 | /* |
| 108 | * Flash configuration |
| 109 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 110 | #define CONFIG_SYS_FLASH_BASE 0xFF000000 |
| 111 | #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ |
Jean-Christophe PLAGNIOL-VILLARD | 8d94c23 | 2008-08-13 01:40:42 +0200 | [diff] [blame] | 112 | #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 113 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } |
| 114 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
| 115 | #define CONFIG_SYS_FLASH_SIZE 0x01000000 /* 16 MByte */ |
| 116 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ |
| 117 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks (= chip selects) */ |
| 118 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* not supported yet for AMD */ |
Heiko Schocher | a1d7c2d | 2008-01-11 15:15:15 +0100 | [diff] [blame] | 119 | |
| 120 | /* |
| 121 | * Chip selects configuration |
| 122 | */ |
| 123 | /* Boot Chipselect */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 124 | #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE |
| 125 | #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE |
| 126 | #define CONFIG_SYS_BOOTCS_CFG 0x00047800 |
Heiko Schocher | a1d7c2d | 2008-01-11 15:15:15 +0100 | [diff] [blame] | 127 | |
| 128 | /* |
| 129 | * Environment settings |
| 130 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 53db4cd | 2008-09-10 22:48:04 +0200 | [diff] [blame] | 131 | #define CONFIG_ENV_IS_IN_FLASH 1 |
Jean-Christophe PLAGNIOL-VILLARD | 7e1cda6 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 132 | #define CONFIG_ENV_OFFSET 0x40000 |
Wolfgang Denk | 0708bc6 | 2010-10-07 21:51:12 +0200 | [diff] [blame] | 133 | #define CONFIG_ENV_ADDR (CONFIG_SYS_TEXT_BASE + CONFIG_ENV_OFFSET) |
Jean-Christophe PLAGNIOL-VILLARD | 7e1cda6 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 134 | #define CONFIG_ENV_SECT_SIZE 0x20000 |
| 135 | #define CONFIG_ENV_SIZE 0x4000 |
| 136 | #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE) |
Wolfgang Denk | 0708bc6 | 2010-10-07 21:51:12 +0200 | [diff] [blame] | 137 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_TEXT_BASE + CONFIG_ENV_OFFSET_REDUND) |
Jean-Christophe PLAGNIOL-VILLARD | 7e1cda6 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 138 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) |
Heiko Schocher | a1d7c2d | 2008-01-11 15:15:15 +0100 | [diff] [blame] | 139 | #define CONFIG_ENV_OVERWRITE 1 |
| 140 | |
| 141 | /* |
| 142 | * Ethernet configuration |
| 143 | */ |
| 144 | #define CONFIG_MPC5xxx_FEC 1 |
Ben Warren | bc1b917 | 2009-02-05 23:58:25 -0800 | [diff] [blame] | 145 | #define CONFIG_MPC5xxx_FEC_MII100 |
Heiko Schocher | a1d7c2d | 2008-01-11 15:15:15 +0100 | [diff] [blame] | 146 | #define CONFIG_PHY_ADDR 0x01 |
| 147 | #define CONFIG_MII 1 |
| 148 | |
| 149 | /* |
| 150 | * GPIO configuration |
| 151 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 152 | #define CONFIG_SYS_GPS_PORT_CONFIG 0x00058044 /* PSC1=UART, PSC2=UART ; Ether=100MBit with MD |
Heiko Schocher | a1d7c2d | 2008-01-11 15:15:15 +0100 | [diff] [blame] | 153 | no PCI */ |
| 154 | |
| 155 | /* |
| 156 | * Miscellaneous configurable options |
| 157 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 158 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 159 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
| 160 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
| 161 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
| 162 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
Heiko Schocher | a1d7c2d | 2008-01-11 15:15:15 +0100 | [diff] [blame] | 163 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 164 | #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ |
| 165 | #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ |
Heiko Schocher | a1d7c2d | 2008-01-11 15:15:15 +0100 | [diff] [blame] | 166 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 167 | #define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */ |
Heiko Schocher | a1d7c2d | 2008-01-11 15:15:15 +0100 | [diff] [blame] | 168 | |
Heiko Schocher | a1d7c2d | 2008-01-11 15:15:15 +0100 | [diff] [blame] | 169 | #define CONFIG_CMDLINE_EDITING 1 |
| 170 | |
| 171 | /* |
| 172 | * Various low-level settings |
| 173 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 174 | #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI |
| 175 | #define CONFIG_SYS_HID0_FINAL HID0_ICE |
Heiko Schocher | a1d7c2d | 2008-01-11 15:15:15 +0100 | [diff] [blame] | 176 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 177 | #define CONFIG_SYS_CS_BURST 0x00000000 |
| 178 | #define CONFIG_SYS_CS_DEADCYCLE 0x33333333 |
| 179 | #define CONFIG_SYS_RESET_ADDRESS 0xff000000 |
Heiko Schocher | a1d7c2d | 2008-01-11 15:15:15 +0100 | [diff] [blame] | 180 | |
Heiko Schocher | a1d7c2d | 2008-01-11 15:15:15 +0100 | [diff] [blame] | 181 | #define OF_CPU "PowerPC,5200@0" |
| 182 | #define OF_TBCLK (bd->bi_busfreq / 4) |
| 183 | #define OF_SOC "soc5200@f0000000" |
| 184 | #define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000" |
| 185 | |
| 186 | #endif /* __CONFIG_H */ |