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Heiko Schochera1d7c2d2008-01-11 15:15:15 +01001/*
2 * (C) Copyright 2007
3 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#ifndef __CONFIG_H
25#define __CONFIG_H
26/*
27 * High Level Configuration Options
28 * (easy to change)
29 */
30#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
31#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
32#define CONFIG_MPC5200_DDR 1 /* (with DDR-SDRAM) */
33#define CONFIG_MUNICES 1 /* ... on MUNICes board */
Wolfgang Denk291ba1b2010-10-06 09:05:45 +020034
35#ifndef CONFIG_SYS_TEXT_BASE
36#define CONFIG_SYS_TEXT_BASE 0xFFF00000
37#endif
38
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020039#define CONFIG_SYS_MPC5XXX_CLKIN 33333333 /* ... running at 33.333333MHz */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020040#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
Becky Bruce03ea1be2008-05-08 19:02:12 -050041#define CONFIG_HIGH_BATS 1 /* High BATs supported */
Heiko Schochera1d7c2d2008-01-11 15:15:15 +010042
43/*
44 * Command line configuration.
45 */
46#include <config_cmd_default.h>
47
48#define CONFIG_CMD_ASKENV
49#define CONFIG_CMD_ELF
50#define CONFIG_CMD_IMMAP
51#define CONFIG_CMD_NET
52#define CONFIG_CMD_PING
53#define CONFIG_CMD_REGINFO
54
Jean-Christophe PLAGNIOL-VILLARD41348722008-01-25 07:54:47 +010055#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020056# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
Heiko Schochera1d7c2d2008-01-11 15:15:15 +010057#endif
58
59/*
60 * Serial console configuration
61 */
62#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
63#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020064#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
Heiko Schochera1d7c2d2008-01-11 15:15:15 +010065
66#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */
67#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
68#undef CONFIG_BOOTARGS
69
70#define CONFIG_PREBOOT "echo;" \
71 "echo Type \"run net_nfs\" to load Kernel over TFTP and to mount root filesystem over NFS;" \
72 "echo"
73
74#define CONFIG_EXTRA_ENV_SETTINGS \
75 "netdev=eth0\0" \
76 "nfsargs=setenv bootargs root=/dev/nfs rw " \
77 "nfsroot=$(serverip):$(rootpath)\0" \
78 "ramargs=setenv bootargs root=/dev/ram rw\0" \
79 "addip=setenv bootargs $(bootargs) " \
80 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
81 ":$(hostname):$(netdev):off panic=5\0" \
82 "flash_nfs=run nfsargs addip;" \
83 "bootm $(kernel_addr)\0" \
84 "flash_self=run ramargs addip;" \
85 "bootm $(kernel_addr) $(ramdisk_addr)\0" \
86 "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
87 "rootpath=/opt/eldk/ppc_6xx\0" \
88 "bootfile=/tftpboot/munices/u-boot.bin\0" \
89 "update=tftpboot 200000 ${bootfile};protect off fff00000 fff3ffff;" \
90 "erase fff00000 fff3ffff; cp.b 200000 FFF00000 ${filesize}\0" \
91 ""
92#define CONFIG_BOOTCOMMAND "run net_nfs"
93
94/*
95 * IPB Bus clocking configuration.
96 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020097#define CONFIG_SYS_IPBSPEED_133 /* define for 133MHz speed */
98#if defined(CONFIG_SYS_IPBSPEED_133)
Heiko Schochera1d7c2d2008-01-11 15:15:15 +010099/*
100 * PCI Bus clocking configuration
101 *
102 * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200103 * CONFIG_SYS_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
Heiko Schochera1d7c2d2008-01-11 15:15:15 +0100104 * been tested with a IPB Bus Clock of 66 MHz.
105 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200106#define CONFIG_SYS_PCISPEED_66 /* define for 66MHz speed */
Heiko Schochera1d7c2d2008-01-11 15:15:15 +0100107#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200108#undef CONFIG_SYS_PCISPEED_66 /* for 33MHz speed */
Heiko Schochera1d7c2d2008-01-11 15:15:15 +0100109#endif
110
111/*
112 * Memory map
113 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200114#define CONFIG_SYS_MBAR 0xF0000000 /* MBAR hast to be switched by other bootloader or debugger config */
Heiko Schocher9a8118b2008-01-11 15:15:16 +0100115
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200116#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
117#define CONFIG_SYS_SDRAM_BASE 0x00000000
Heiko Schochera1d7c2d2008-01-11 15:15:15 +0100118/* Use SRAM until RAM will be available */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200119#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200120#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200121#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200122#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200123#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Heiko Schochera1d7c2d2008-01-11 15:15:15 +0100124
Wolfgang Denk0708bc62010-10-07 21:51:12 +0200125#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200126#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
127# define CONFIG_SYS_RAMBOOT 1
Heiko Schochera1d7c2d2008-01-11 15:15:15 +0100128#endif
129
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200130#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
131#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
132#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Heiko Schochera1d7c2d2008-01-11 15:15:15 +0100133
134/*
135 * Flash configuration
136 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200137#define CONFIG_SYS_FLASH_BASE 0xFF000000
138#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
Jean-Christophe PLAGNIOL-VILLARD8d94c232008-08-13 01:40:42 +0200139#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200140#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
141#define CONFIG_SYS_FLASH_EMPTY_INFO
142#define CONFIG_SYS_FLASH_SIZE 0x01000000 /* 16 MByte */
143#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
144#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks (= chip selects) */
145#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* not supported yet for AMD */
Heiko Schochera1d7c2d2008-01-11 15:15:15 +0100146
147/*
148 * Chip selects configuration
149 */
150/* Boot Chipselect */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200151#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
152#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
153#define CONFIG_SYS_BOOTCS_CFG 0x00047800
Heiko Schochera1d7c2d2008-01-11 15:15:15 +0100154
155/*
156 * Environment settings
157 */
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200158#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200159#define CONFIG_ENV_OFFSET 0x40000
Wolfgang Denk0708bc62010-10-07 21:51:12 +0200160#define CONFIG_ENV_ADDR (CONFIG_SYS_TEXT_BASE + CONFIG_ENV_OFFSET)
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200161#define CONFIG_ENV_SECT_SIZE 0x20000
162#define CONFIG_ENV_SIZE 0x4000
163#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
Wolfgang Denk0708bc62010-10-07 21:51:12 +0200164#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_TEXT_BASE + CONFIG_ENV_OFFSET_REDUND)
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200165#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Heiko Schochera1d7c2d2008-01-11 15:15:15 +0100166#define CONFIG_ENV_OVERWRITE 1
167
168/*
169 * Ethernet configuration
170 */
171#define CONFIG_MPC5xxx_FEC 1
Ben Warrenbc1b9172009-02-05 23:58:25 -0800172#define CONFIG_MPC5xxx_FEC_MII100
Heiko Schochera1d7c2d2008-01-11 15:15:15 +0100173#define CONFIG_PHY_ADDR 0x01
174#define CONFIG_MII 1
175
176/*
177 * GPIO configuration
178 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200179#define CONFIG_SYS_GPS_PORT_CONFIG 0x00058044 /* PSC1=UART, PSC2=UART ; Ether=100MBit with MD
Heiko Schochera1d7c2d2008-01-11 15:15:15 +0100180 no PCI */
181
182/*
183 * Miscellaneous configurable options
184 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200185#define CONFIG_SYS_LONGHELP /* undef to save memory */
186#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
187#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
188#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
189#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
190#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Heiko Schochera1d7c2d2008-01-11 15:15:15 +0100191
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200192#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
193#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
Heiko Schochera1d7c2d2008-01-11 15:15:15 +0100194
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200195#define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */
196#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
Heiko Schochera1d7c2d2008-01-11 15:15:15 +0100197
198#define CONFIG_DISPLAY_BOARDINFO 1
199#define CONFIG_CMDLINE_EDITING 1
200
201/*
202 * Various low-level settings
203 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200204#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
205#define CONFIG_SYS_HID0_FINAL HID0_ICE
Heiko Schochera1d7c2d2008-01-11 15:15:15 +0100206
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200207#define CONFIG_SYS_CS_BURST 0x00000000
208#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
209#define CONFIG_SYS_RESET_ADDRESS 0xff000000
Heiko Schochera1d7c2d2008-01-11 15:15:15 +0100210
211/* pass open firmware flat tree */
212#define CONFIG_OF_LIBFDT 1
213#define CONFIG_OF_BOARD_SETUP 1
214
215#define OF_CPU "PowerPC,5200@0"
216#define OF_TBCLK (bd->bi_busfreq / 4)
217#define OF_SOC "soc5200@f0000000"
218#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
219
220#endif /* __CONFIG_H */