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Timur Tabi9b45b5a2010-06-14 15:28:24 -05001/*
ramneek mehresh3d339632012-04-18 19:39:53 +00002 * Copyright 2010-2012 Freescale Semiconductor, Inc.
Timur Tabi9b45b5a2010-06-14 15:28:24 -05003 * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
4 * Timur Tabi <timur@freescale.com>
5 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Timur Tabi9b45b5a2010-06-14 15:28:24 -05007 */
8
9#ifndef __CONFIG_H
10#define __CONFIG_H
11
12#include "../board/freescale/common/ics307_clk.h"
13
Matthew McClintockc4253e92012-05-18 06:04:17 +000014#ifdef CONFIG_SDCARD
Ying Zhangdfb2b152013-08-16 15:16:12 +080015#define CONFIG_SPL_MMC_MINIMAL
16#define CONFIG_SPL_FLUSH_IMAGE
17#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
Ying Zhangdfb2b152013-08-16 15:16:12 +080018#define CONFIG_SYS_TEXT_BASE 0x11001000
19#define CONFIG_SPL_TEXT_BASE 0xf8f81000
Ying Zhang25daf572014-01-24 15:50:06 +080020#define CONFIG_SPL_PAD_TO 0x20000
21#define CONFIG_SPL_MAX_SIZE (128 * 1024)
Prabhakar Kushwahaf2036562014-01-14 11:34:26 +053022#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
Ying Zhangdfb2b152013-08-16 15:16:12 +080023#define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
24#define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
Ying Zhang25daf572014-01-24 15:50:06 +080025#define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10)
Ying Zhangdfb2b152013-08-16 15:16:12 +080026#define CONFIG_SYS_MPC85XX_NO_RESETVEC
27#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
28#define CONFIG_SPL_MMC_BOOT
29#ifdef CONFIG_SPL_BUILD
30#define CONFIG_SPL_COMMON_INIT_DDR
31#endif
Matthew McClintockc4253e92012-05-18 06:04:17 +000032#endif
33
34#ifdef CONFIG_SPIFLASH
Ying Zhang9b155ca2013-08-16 15:16:14 +080035#define CONFIG_SPL_SPI_FLASH_MINIMAL
36#define CONFIG_SPL_FLUSH_IMAGE
37#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
Ying Zhang9b155ca2013-08-16 15:16:14 +080038#define CONFIG_SYS_TEXT_BASE 0x11001000
39#define CONFIG_SPL_TEXT_BASE 0xf8f81000
Ying Zhang25daf572014-01-24 15:50:06 +080040#define CONFIG_SPL_PAD_TO 0x20000
41#define CONFIG_SPL_MAX_SIZE (128 * 1024)
Prabhakar Kushwahaf2036562014-01-14 11:34:26 +053042#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
Ying Zhang9b155ca2013-08-16 15:16:14 +080043#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
44#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
Ying Zhang25daf572014-01-24 15:50:06 +080045#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10)
Ying Zhang9b155ca2013-08-16 15:16:14 +080046#define CONFIG_SYS_MPC85XX_NO_RESETVEC
47#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
48#define CONFIG_SPL_SPI_BOOT
49#ifdef CONFIG_SPL_BUILD
50#define CONFIG_SPL_COMMON_INIT_DDR
51#endif
Matthew McClintockc4253e92012-05-18 06:04:17 +000052#endif
53
Matthew McClintockcd99caa2013-02-18 10:02:19 +000054#define CONFIG_NAND_FSL_ELBC
York Sun4a343052013-12-17 11:21:08 -080055#define CONFIG_SYS_NAND_MAX_ECCPOS 56
56#define CONFIG_SYS_NAND_MAX_OOBFREE 5
Matthew McClintockcd99caa2013-02-18 10:02:19 +000057
58#ifdef CONFIG_NAND
Ying Zhang9c2e84f2013-08-16 15:16:16 +080059#ifdef CONFIG_TPL_BUILD
60#define CONFIG_SPL_NAND_BOOT
61#define CONFIG_SPL_FLUSH_IMAGE
Simon Glass7db65a82016-09-12 23:18:45 -060062#define CONFIG_SPL_NAND_INIT
Ying Zhang9c2e84f2013-08-16 15:16:16 +080063#define CONFIG_SPL_COMMON_INIT_DDR
64#define CONFIG_SPL_MAX_SIZE (128 << 10)
65#define CONFIG_SPL_TEXT_BASE 0xf8f81000
66#define CONFIG_SYS_MPC85XX_NO_RESETVEC
Prabhakar Kushwahaf2036562014-01-14 11:34:26 +053067#define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
Ying Zhang9c2e84f2013-08-16 15:16:16 +080068#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
69#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
70#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
71#elif defined(CONFIG_SPL_BUILD)
Matthew McClintockcd99caa2013-02-18 10:02:19 +000072#define CONFIG_SPL_INIT_MINIMAL
Matthew McClintockcd99caa2013-02-18 10:02:19 +000073#define CONFIG_SPL_FLUSH_IMAGE
Ying Zhang9c2e84f2013-08-16 15:16:16 +080074#define CONFIG_SPL_TEXT_BASE 0xff800000
75#define CONFIG_SPL_MAX_SIZE 4096
76#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
77#define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
78#define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
79#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
80#endif
81#define CONFIG_SPL_PAD_TO 0x20000
82#define CONFIG_TPL_PAD_TO 0x20000
83#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
84#define CONFIG_SYS_TEXT_BASE 0x11001000
85#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
Matthew McClintockcd99caa2013-02-18 10:02:19 +000086#endif
87
Timur Tabi9b45b5a2010-06-14 15:28:24 -050088/* High Level Configuration Options */
Timur Tabi9b45b5a2010-06-14 15:28:24 -050089#define CONFIG_MP /* support multiple processors */
90
Wolfgang Denk291ba1b2010-10-06 09:05:45 +020091#ifndef CONFIG_SYS_TEXT_BASE
Prabhakar Kushwahaf2036562014-01-14 11:34:26 +053092#define CONFIG_SYS_TEXT_BASE 0xeff40000
Wolfgang Denk291ba1b2010-10-06 09:05:45 +020093#endif
94
Kumar Galae727a362011-01-12 02:48:53 -060095#ifndef CONFIG_RESET_VECTOR_ADDRESS
96#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
97#endif
98
Robert P. J. Daya8099812016-05-03 19:52:49 -040099#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
100#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
101#define CONFIG_PCIE3 /* PCIE controller 3 (ULI bridge) */
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500102#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
103#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
104#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
105
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500106#define CONFIG_ENABLE_36BIT_PHYS
Timur Tabi6a873c92011-09-06 09:36:06 -0500107
108#ifdef CONFIG_PHYS_64BIT
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500109#define CONFIG_ADDR_MAP
110#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
Jiang Yutangb7738b52011-01-24 18:21:15 +0800111#endif
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500112
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500113#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
114#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
115#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
116
117/*
118 * These can be toggled for performance analysis, otherwise use default.
119 */
120#define CONFIG_L2_CACHE
121#define CONFIG_BTB
122
123#define CONFIG_SYS_MEMTEST_START 0x00000000
124#define CONFIG_SYS_MEMTEST_END 0x7fffffff
125
Timur Tabid8f341c2011-08-04 18:03:41 -0500126#define CONFIG_SYS_CCSRBAR 0xffe00000
127#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500128
Matthew McClintockcd99caa2013-02-18 10:02:19 +0000129/* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
130 SPL code*/
131#ifdef CONFIG_SPL_BUILD
132#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
133#endif
134
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500135/* DDR Setup */
136#define CONFIG_DDR_SPD
137#define CONFIG_VERY_BIG_RAM
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500138
139#ifdef CONFIG_DDR_ECC
140#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
141#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
142#endif
143
144#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
145#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
146
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500147#define CONFIG_DIMM_SLOTS_PER_CTLR 1
148#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
149
150/* I2C addresses of SPD EEPROMs */
151#define CONFIG_SYS_SPD_BUS_NUM 1
Kumar Galac68e86c2011-01-31 22:18:47 -0600152#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500153
Matthew McClintockcd99caa2013-02-18 10:02:19 +0000154/* These are used when DDR doesn't use SPD. */
155#define CONFIG_SYS_SDRAM_SIZE 2048
156#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G
157#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
158#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
159#define CONFIG_SYS_DDR_CS1_BNDS 0x0040007F
160#define CONFIG_SYS_DDR_CS1_CONFIG 0x80014202
161#define CONFIG_SYS_DDR_TIMING_3 0x00010000
162#define CONFIG_SYS_DDR_TIMING_0 0x40110104
163#define CONFIG_SYS_DDR_TIMING_1 0x5c5bd746
164#define CONFIG_SYS_DDR_TIMING_2 0x0fa8d4ca
165#define CONFIG_SYS_DDR_MODE_1 0x00441221
166#define CONFIG_SYS_DDR_MODE_2 0x00000000
167#define CONFIG_SYS_DDR_INTERVAL 0x0a280100
168#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
169#define CONFIG_SYS_DDR_CLK_CTRL 0x02800000
170#define CONFIG_SYS_DDR_CONTROL 0xc7000008
171#define CONFIG_SYS_DDR_CONTROL_2 0x24401041
172#define CONFIG_SYS_DDR_TIMING_4 0x00220001
173#define CONFIG_SYS_DDR_TIMING_5 0x02401400
174#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
175#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8675f608
176
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500177/*
178 * Memory map
179 *
180 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
181 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable
182 * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable
183 *
184 * Localbus cacheable (TBD)
185 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
186 *
187 * Localbus non-cacheable
188 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable
189 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
Matthew McClintockcd99caa2013-02-18 10:02:19 +0000190 * 0xff80_0000 0xff80_7fff NAND 32K non-cacheable
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500191 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
192 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
193 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
194 */
195
196/*
197 * Local Bus Definitions
198 */
Matthew McClintockcd99caa2013-02-18 10:02:19 +0000199#define CONFIG_SYS_FLASH_BASE 0xe8000000 /* start of FLASH 128M */
Jiang Yutangb7738b52011-01-24 18:21:15 +0800200#ifdef CONFIG_PHYS_64BIT
Matthew McClintockcd99caa2013-02-18 10:02:19 +0000201#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe8000000ull
Jiang Yutangb7738b52011-01-24 18:21:15 +0800202#else
203#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
204#endif
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500205
206#define CONFIG_FLASH_BR_PRELIM \
Matthew McClintockcd99caa2013-02-18 10:02:19 +0000207 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500208#define CONFIG_FLASH_OR_PRELIM (OR_AM_128MB | 0xff7)
209
Matthew McClintockcd99caa2013-02-18 10:02:19 +0000210#ifdef CONFIG_NAND
211#define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
212#define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
213#else
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500214#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
215#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
Matthew McClintockcd99caa2013-02-18 10:02:19 +0000216#endif
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500217
Matthew McClintockcd99caa2013-02-18 10:02:19 +0000218#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500219#define CONFIG_SYS_FLASH_QUIET_TEST
220#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
221
Matthew McClintockcd99caa2013-02-18 10:02:19 +0000222#define CONFIG_SYS_MAX_FLASH_BANKS 1
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500223#define CONFIG_SYS_MAX_FLASH_SECT 1024
224
Matthew McClintockcd99caa2013-02-18 10:02:19 +0000225#ifndef CONFIG_SYS_MONITOR_BASE
226#ifdef CONFIG_SPL_BUILD
227#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
228#else
Wolfgang Denk0708bc62010-10-07 21:51:12 +0200229#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Matthew McClintockcd99caa2013-02-18 10:02:19 +0000230#endif
231#endif
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500232
233#define CONFIG_FLASH_CFI_DRIVER
234#define CONFIG_SYS_FLASH_CFI
235#define CONFIG_SYS_FLASH_EMPTY_INFO
236
Matthew McClintockcd99caa2013-02-18 10:02:19 +0000237/* Nand Flash */
238#if defined(CONFIG_NAND_FSL_ELBC)
239#define CONFIG_SYS_NAND_BASE 0xff800000
240#ifdef CONFIG_PHYS_64BIT
241#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
242#else
243#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
244#endif
245
Ying Zhang9c2e84f2013-08-16 15:16:16 +0800246#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
Matthew McClintockcd99caa2013-02-18 10:02:19 +0000247#define CONFIG_SYS_MAX_NAND_DEVICE 1
Matthew McClintockcd99caa2013-02-18 10:02:19 +0000248#define CONFIG_CMD_NAND 1
Ying Zhang9c2e84f2013-08-16 15:16:16 +0800249#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024)
Matthew McClintockcd99caa2013-02-18 10:02:19 +0000250#define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE
251
252/* NAND flash config */
253#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
254 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
255 | BR_PS_8 /* Port Size = 8 bit */ \
256 | BR_MS_FCM /* MSEL = FCM */ \
257 | BR_V) /* valid */
258#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* length 256K */ \
259 | OR_FCM_PGS /* Large Page*/ \
260 | OR_FCM_CSCT \
261 | OR_FCM_CST \
262 | OR_FCM_CHT \
263 | OR_FCM_SCY_1 \
264 | OR_FCM_TRLX \
265 | OR_FCM_EHTR)
266#ifdef CONFIG_NAND
267#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
268#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
269#else
270#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
271#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
272#endif
273
274#endif /* CONFIG_NAND_FSL_ELBC */
275
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500276#define CONFIG_BOARD_EARLY_INIT_R
277#define CONFIG_MISC_INIT_R
Timur Tabi8848d472010-07-21 16:56:19 -0500278#define CONFIG_HWCONFIG
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500279
280#define CONFIG_FSL_NGPIXIS
281#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
Jiang Yutangb7738b52011-01-24 18:21:15 +0800282#ifdef CONFIG_PHYS_64BIT
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500283#define PIXIS_BASE_PHYS 0xfffdf0000ull
Jiang Yutangb7738b52011-01-24 18:21:15 +0800284#else
285#define PIXIS_BASE_PHYS PIXIS_BASE
286#endif
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500287
288#define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
289#define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | 0x6ff7)
290
291#define PIXIS_LBMAP_SWITCH 7
York Sun362c9932011-01-26 10:30:00 -0800292#define PIXIS_LBMAP_MASK 0xF0
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500293#define PIXIS_LBMAP_ALTBANK 0x20
Matthew McClintockcd99caa2013-02-18 10:02:19 +0000294#define PIXIS_SPD 0x07
295#define PIXIS_SPD_SYSCLK_MASK 0x07
Jiang Yutang382e3572011-02-24 16:11:56 +0800296#define PIXIS_ELBC_SPI_MASK 0xc0
297#define PIXIS_SPI 0x80
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500298
299#define CONFIG_SYS_INIT_RAM_LOCK
300#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200301#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500302
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500303#define CONFIG_SYS_GBL_DATA_OFFSET \
Wolfgang Denk0191e472010-10-26 14:34:52 +0200304 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500305#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
306
Prabhakar Kushwahaf4027312014-03-31 15:31:48 +0530307#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
Jerry Huang5b5bd372011-11-02 09:16:44 +0800308#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500309
310/*
Ying Zhangdfb2b152013-08-16 15:16:12 +0800311 * Config the L2 Cache as L2 SRAM
312*/
313#if defined(CONFIG_SPL_BUILD)
Ying Zhang9b155ca2013-08-16 15:16:14 +0800314#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
Ying Zhangdfb2b152013-08-16 15:16:12 +0800315#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
316#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
317#define CONFIG_SYS_L2_SIZE (256 << 10)
318#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
319#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
Ying Zhang3587a832014-01-24 15:50:08 +0800320#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
Ying Zhangdfb2b152013-08-16 15:16:12 +0800321#define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10)
Ying Zhang3587a832014-01-24 15:50:08 +0800322#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
323#define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10)
Ying Zhangdfb2b152013-08-16 15:16:12 +0800324#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
Ying Zhang9c2e84f2013-08-16 15:16:16 +0800325#elif defined(CONFIG_NAND)
326#ifdef CONFIG_TPL_BUILD
327#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
328#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
329#define CONFIG_SYS_L2_SIZE (256 << 10)
330#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
331#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
332#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
333#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
334#define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
335#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
336#else
337#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
338#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
339#define CONFIG_SYS_L2_SIZE (256 << 10)
340#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
341#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000)
342#define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
343#endif
Ying Zhangdfb2b152013-08-16 15:16:12 +0800344#endif
345#endif
346
347/*
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500348 * Serial Port
349 */
350#define CONFIG_CONS_INDEX 1
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500351#define CONFIG_SYS_NS16550_SERIAL
352#define CONFIG_SYS_NS16550_REG_SIZE 1
353#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Ying Zhangdfb2b152013-08-16 15:16:12 +0800354#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
Matthew McClintockcd99caa2013-02-18 10:02:19 +0000355#define CONFIG_NS16550_MIN_FUNCTIONS
356#endif
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500357
358#define CONFIG_SYS_BAUDRATE_TABLE \
359 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
360
361#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
362#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
363
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500364/* Video */
Timur Tabi32f709e2011-04-11 14:18:22 -0500365
Timur Tabi209c0722010-09-24 01:25:53 +0200366#ifdef CONFIG_FSL_DIU_FB
367#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000)
Timur Tabi209c0722010-09-24 01:25:53 +0200368#define CONFIG_VIDEO_LOGO
369#define CONFIG_VIDEO_BMP_LOGO
Timur Tabi970c01f2010-09-16 16:35:44 -0500370#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
371/*
372 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
373 * disable empty flash sector detection, which is I/O-intensive.
374 */
375#undef CONFIG_SYS_FLASH_EMPTY_INFO
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500376#endif
377
Timur Tabi32f709e2011-04-11 14:18:22 -0500378#ifndef CONFIG_FSL_DIU_FB
Jiang Yutang6c698c02011-01-24 18:21:19 +0800379#endif
380
381#ifdef CONFIG_ATI
382#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT
Jiang Yutang6c698c02011-01-24 18:21:19 +0800383#define CONFIG_BIOSEMU
Jiang Yutang6c698c02011-01-24 18:21:19 +0800384#define CONFIG_ATI_RADEON_FB
385#define CONFIG_VIDEO_LOGO
386#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
Jiang Yutang6c698c02011-01-24 18:21:19 +0800387#endif
388
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500389/* I2C */
Heiko Schocherf2850742012-10-24 13:48:22 +0200390#define CONFIG_SYS_I2C
391#define CONFIG_SYS_I2C_FSL
392#define CONFIG_SYS_FSL_I2C_SPEED 400000
393#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
394#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
395#define CONFIG_SYS_FSL_I2C2_SPEED 400000
396#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
397#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500398#define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}}
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500399
400/*
401 * I2C2 EEPROM
402 */
403#define CONFIG_ID_EEPROM
404#define CONFIG_SYS_I2C_EEPROM_NXID
405#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
406#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
407#define CONFIG_SYS_EEPROM_BUS_NUM 1
408
409/*
Jiang Yutang382e3572011-02-24 16:11:56 +0800410 * eSPI - Enhanced SPI
411 */
Jiang Yutang382e3572011-02-24 16:11:56 +0800412
413#define CONFIG_HARD_SPI
Jiang Yutang382e3572011-02-24 16:11:56 +0800414
Jiang Yutang382e3572011-02-24 16:11:56 +0800415#define CONFIG_SF_DEFAULT_SPEED 10000000
416#define CONFIG_SF_DEFAULT_MODE 0
417
418/*
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500419 * General PCI
420 * Memory space is mapped 1-1, but I/O space must start from 0.
421 */
422
423/* controller 1, Slot 2, tgtid 1, Base address a000 */
424#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
Jiang Yutangb7738b52011-01-24 18:21:15 +0800425#ifdef CONFIG_PHYS_64BIT
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500426#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
427#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
Jiang Yutangb7738b52011-01-24 18:21:15 +0800428#else
429#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
430#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
431#endif
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500432#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
433#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
434#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
Jiang Yutangb7738b52011-01-24 18:21:15 +0800435#ifdef CONFIG_PHYS_64BIT
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500436#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
Jiang Yutangb7738b52011-01-24 18:21:15 +0800437#else
438#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
439#endif
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500440#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
441
442/* controller 2, direct to uli, tgtid 2, Base address 9000 */
443#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
Jiang Yutangb7738b52011-01-24 18:21:15 +0800444#ifdef CONFIG_PHYS_64BIT
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500445#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
446#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
Jiang Yutangb7738b52011-01-24 18:21:15 +0800447#else
448#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
449#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
450#endif
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500451#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
452#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
453#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
Jiang Yutangb7738b52011-01-24 18:21:15 +0800454#ifdef CONFIG_PHYS_64BIT
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500455#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
Jiang Yutangb7738b52011-01-24 18:21:15 +0800456#else
457#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
458#endif
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500459#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
460
461/* controller 3, Slot 1, tgtid 3, Base address b000 */
462#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
Jiang Yutangb7738b52011-01-24 18:21:15 +0800463#ifdef CONFIG_PHYS_64BIT
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500464#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
465#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
Jiang Yutangb7738b52011-01-24 18:21:15 +0800466#else
467#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
468#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
469#endif
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500470#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
471#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
472#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
Jiang Yutangb7738b52011-01-24 18:21:15 +0800473#ifdef CONFIG_PHYS_64BIT
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500474#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
Jiang Yutangb7738b52011-01-24 18:21:15 +0800475#else
476#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
477#endif
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500478#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
479
480#ifdef CONFIG_PCI
Gabor Juhosb4458732013-05-30 07:06:12 +0000481#define CONFIG_PCI_INDIRECT_BRIDGE
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500482#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
483#endif
484
485/* SATA */
486#define CONFIG_LIBATA
487#define CONFIG_FSL_SATA
Zang Roy-R619112ce421a2012-11-26 00:05:38 +0000488#define CONFIG_FSL_SATA_V2
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500489
490#define CONFIG_SYS_SATA_MAX_DEVICE 2
491#define CONFIG_SATA1
492#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
493#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
494#define CONFIG_SATA2
495#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
496#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
497
498#ifdef CONFIG_FSL_SATA
499#define CONFIG_LBA48
500#define CONFIG_CMD_SATA
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500501#endif
502
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500503#ifdef CONFIG_MMC
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500504#define CONFIG_FSL_ESDHC
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500505#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
506#endif
507
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500508#define CONFIG_TSEC_ENET
509#ifdef CONFIG_TSEC_ENET
510
511#define CONFIG_TSECV2
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500512
513#define CONFIG_MII /* MII PHY management */
514#define CONFIG_TSEC1 1
515#define CONFIG_TSEC1_NAME "eTSEC1"
516#define CONFIG_TSEC2 1
517#define CONFIG_TSEC2_NAME "eTSEC2"
518
519#define TSEC1_PHY_ADDR 1
520#define TSEC2_PHY_ADDR 2
521
522#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
523#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
524
525#define TSEC1_PHYIDX 0
526#define TSEC2_PHYIDX 0
527
528#define CONFIG_ETHPRIME "eTSEC1"
529
530#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
531#endif
532
533/*
Yangbo Lu140b2bb2014-10-16 10:58:55 +0800534 * Dynamic MTD Partition support with mtdparts
535 */
536#define CONFIG_MTD_DEVICE
537#define CONFIG_MTD_PARTITIONS
538#define CONFIG_CMD_MTDPARTS
539#define CONFIG_FLASH_CFI_MTD
540#ifdef CONFIG_PHYS_64BIT
541#define MTDIDS_DEFAULT "nor0=fe8000000.nor"
542#define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:48m(ramdisk)," \
543 "14m(diagnostic),2m(dink),6m(kernel),58112k(fs)," \
544 "512k(dtb),768k(u-boot)"
545#else
546#define MTDIDS_DEFAULT "nor0=e8000000.nor"
547#define MTDPARTS_DEFAULT "mtdparts=e8000000.nor:48m(ramdisk)," \
548 "14m(diagnostic),2m(dink),6m(kernel),58112k(fs)," \
549 "512k(dtb),768k(u-boot)"
550#endif
551
552/*
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500553 * Environment
554 */
Ying Zhang9b155ca2013-08-16 15:16:14 +0800555#ifdef CONFIG_SPIFLASH
Matthew McClintockc4253e92012-05-18 06:04:17 +0000556#define CONFIG_ENV_IS_IN_SPI_FLASH
557#define CONFIG_ENV_SPI_BUS 0
558#define CONFIG_ENV_SPI_CS 0
559#define CONFIG_ENV_SPI_MAX_HZ 10000000
560#define CONFIG_ENV_SPI_MODE 0
561#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
562#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
563#define CONFIG_ENV_SECT_SIZE 0x10000
Ying Zhangdfb2b152013-08-16 15:16:12 +0800564#elif defined(CONFIG_SDCARD)
Matthew McClintockc4253e92012-05-18 06:04:17 +0000565#define CONFIG_ENV_IS_IN_MMC
Ying Zhangdfb2b152013-08-16 15:16:12 +0800566#define CONFIG_FSL_FIXED_MMC_LOCATION
Matthew McClintockc4253e92012-05-18 06:04:17 +0000567#define CONFIG_ENV_SIZE 0x2000
568#define CONFIG_SYS_MMC_ENV_DEV 0
Matthew McClintockcd99caa2013-02-18 10:02:19 +0000569#elif defined(CONFIG_NAND)
Ying Zhang9c2e84f2013-08-16 15:16:16 +0800570#ifdef CONFIG_TPL_BUILD
571#define CONFIG_ENV_SIZE 0x2000
572#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
573#else
Matthew McClintockc4253e92012-05-18 06:04:17 +0000574#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
Ying Zhang9c2e84f2013-08-16 15:16:16 +0800575#endif
576#define CONFIG_ENV_IS_IN_NAND
577#define CONFIG_ENV_OFFSET (1024 * 1024)
Matthew McClintockc4253e92012-05-18 06:04:17 +0000578#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
Matthew McClintockcd99caa2013-02-18 10:02:19 +0000579#elif defined(CONFIG_SYS_RAMBOOT)
Matthew McClintockc4253e92012-05-18 06:04:17 +0000580#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
581#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
582#define CONFIG_ENV_SIZE 0x2000
Matthew McClintockc4253e92012-05-18 06:04:17 +0000583#else
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500584#define CONFIG_ENV_IS_IN_FLASH
Matthew McClintockc4253e92012-05-18 06:04:17 +0000585#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500586#define CONFIG_ENV_SIZE 0x2000
Matthew McClintockc4253e92012-05-18 06:04:17 +0000587#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
588#endif
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500589
590#define CONFIG_LOADS_ECHO
591#define CONFIG_SYS_LOADS_BAUD_CHANGE
592
593/*
594 * Command line configuration.
595 */
Matthew McClintock49b9da12010-12-17 17:26:41 -0600596#define CONFIG_CMD_REGINFO
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500597
598#ifdef CONFIG_PCI
599#define CONFIG_CMD_PCI
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500600#endif
601
602/*
603 * USB
604 */
ramneek mehresh3d339632012-04-18 19:39:53 +0000605#define CONFIG_HAS_FSL_DR_USB
606#ifdef CONFIG_HAS_FSL_DR_USB
Tom Riniceed5d22017-05-12 22:33:27 -0400607#ifdef CONFIG_USB_EHCI_HCD
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500608#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
609#define CONFIG_USB_EHCI_FSL
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500610#endif
ramneek mehresh3d339632012-04-18 19:39:53 +0000611#endif
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500612
613/*
614 * Miscellaneous configurable options
615 */
616#define CONFIG_SYS_LONGHELP /* undef to save memory */
617#define CONFIG_CMDLINE_EDITING /* Command-line editing */
Kim Phillipsf7758c12010-07-14 19:47:18 -0500618#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500619#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500620#ifdef CONFIG_CMD_KGDB
621#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
622#else
623#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
624#endif
625/* Print Buffer Size */
626#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
627#define CONFIG_SYS_MAXARGS 16
628#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500629
630/*
631 * For booting Linux, the board info and command line data
Kumar Gala39ffcc12011-04-28 10:13:41 -0500632 * have to be in the first 64 MB of memory, since this is
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500633 * the maximum mapped by the Linux kernel during initialization.
634 */
Kumar Gala39ffcc12011-04-28 10:13:41 -0500635#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
636#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500637
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500638#ifdef CONFIG_CMD_KGDB
639#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500640#endif
641
642/*
643 * Environment Configuration
644 */
645
646#define CONFIG_HOSTNAME p1022ds
Joe Hershberger257ff782011-10-13 13:03:47 +0000647#define CONFIG_ROOTPATH "/opt/nfsroot"
Joe Hershbergere4da2482011-10-13 13:03:48 +0000648#define CONFIG_BOOTFILE "uImage"
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500649#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
650
651#define CONFIG_LOADADDR 1000000
652
Timur Tabi1a70b232012-05-04 12:21:29 +0000653#define CONFIG_EXTRA_ENV_SETTINGS \
654 "netdev=eth0\0" \
Marek Vasut0b3176c2012-09-23 17:41:24 +0200655 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
656 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
Timur Tabi1a70b232012-05-04 12:21:29 +0000657 "tftpflash=tftpboot $loadaddr $uboot && " \
658 "protect off $ubootaddr +$filesize && " \
659 "erase $ubootaddr +$filesize && " \
660 "cp.b $loadaddr $ubootaddr $filesize && " \
661 "protect on $ubootaddr +$filesize && " \
662 "cmp.b $loadaddr $ubootaddr $filesize\0" \
663 "consoledev=ttyS0\0" \
664 "ramdiskaddr=2000000\0" \
665 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
Scott Woodb7f4b852016-07-19 17:52:06 -0500666 "fdtaddr=1e00000\0" \
Timur Tabi1a70b232012-05-04 12:21:29 +0000667 "fdtfile=p1022ds.dtb\0" \
668 "bdev=sda3\0" \
Timur Tabi32f709e2011-04-11 14:18:22 -0500669 "hwconfig=esdhc;audclk:12\0"
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500670
671#define CONFIG_HDBOOT \
672 "setenv bootargs root=/dev/$bdev rw " \
Timur Tabi1a70b232012-05-04 12:21:29 +0000673 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500674 "tftp $loadaddr $bootfile;" \
675 "tftp $fdtaddr $fdtfile;" \
676 "bootm $loadaddr - $fdtaddr"
677
678#define CONFIG_NFSBOOTCOMMAND \
679 "setenv bootargs root=/dev/nfs rw " \
680 "nfsroot=$serverip:$rootpath " \
681 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
Timur Tabi1a70b232012-05-04 12:21:29 +0000682 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500683 "tftp $loadaddr $bootfile;" \
684 "tftp $fdtaddr $fdtfile;" \
685 "bootm $loadaddr - $fdtaddr"
686
687#define CONFIG_RAMBOOTCOMMAND \
688 "setenv bootargs root=/dev/ram rw " \
Timur Tabi1a70b232012-05-04 12:21:29 +0000689 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500690 "tftp $ramdiskaddr $ramdiskfile;" \
691 "tftp $loadaddr $bootfile;" \
692 "tftp $fdtaddr $fdtfile;" \
693 "bootm $loadaddr $ramdiskaddr $fdtaddr"
694
695#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
696
697#endif