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git01.mediatek.com / filogic / uboot / 1e081eb9702a47e48ae255c4052a609470fe8565 / . / arch / arm / dts / k3-j7200-r5-common-proc-board.dts
blob: 69bf999307761e25ef6fa797d32a61170d7dca9e [file] [log] [blame]
Dave Gerlachfe506932020-08-05 22:44:29 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
Reid Tonking7a2826a2023-10-05 13:12:58 -0500[diff] [blame]3 * Copyright (C) 2020-2023 Texas Instruments Incorporated - https://www.ti.com/
Dave Gerlachfe506932020-08-05 22:44:29 +0530[diff] [blame]4 */
5
6/dts-v1/;
7
Reid Tonking7a2826a2023-10-05 13:12:58 -0500[diff] [blame]8#include "k3-j7200-common-proc-board.dts"
Kevin Scholz7a16fb52021-06-03 08:14:53 -0500[diff] [blame]9#include "k3-j7200-ddr-evm-lp4-2666.dtsi"
Dave Gerlachfe506932020-08-05 22:44:29 +0530[diff] [blame]10#include "k3-j721e-ddr.dtsi"
Reid Tonking7a2826a2023-10-05 13:12:58 -0500[diff] [blame]11#include "k3-j7200-common-proc-board-u-boot.dtsi"
Dave Gerlachfe506932020-08-05 22:44:29 +0530[diff] [blame]12
13/ {
14 aliases {
15 remoteproc0 = &sysctrler;
16 remoteproc1 = &a72_0;
17 };
18
Dave Gerlachfe506932020-08-05 22:44:29 +0530[diff] [blame]19 a72_0: a72@0 {
20 compatible = "ti,am654-rproc";
21 reg = <0x0 0x00a90000 0x0 0x10>;
22 power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
Manorit Chawdhry2806e832023-04-14 09:47:55 +0530[diff] [blame]23 <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>,
24 <&k3_pds 4 TI_SCI_PD_EXCLUSIVE>;
Dave Gerlachfe506932020-08-05 22:44:29 +0530[diff] [blame]25 resets = <&k3_reset 202 0>;
Manorit Chawdhryf23728b2024-10-15 16:22:19 +0530[diff] [blame]26 clocks = <&k3_clks 61 1>, <&k3_clks 202 2>;
27 clock-names = "gtc", "core";
Reid Tonking704ef102023-12-07 10:52:11 -0600[diff] [blame]28 assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>, <&k3_clks 323 0>;
29 assigned-clock-parents= <0>, <0>, <&k3_clks 323 2>;
Dave Gerlachfe506932020-08-05 22:44:29 +0530[diff] [blame]30 assigned-clock-rates = <2000000000>, <200000000>;
31 ti,sci = <&dmsc>;
32 ti,sci-proc-id = <32>;
33 ti,sci-host-id = <10>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]34 bootph-pre-ram;
Dave Gerlachfe506932020-08-05 22:44:29 +0530[diff] [blame]35 };
36
Reid Tonking7a2826a2023-10-05 13:12:58 -0500[diff] [blame]37 dm_tifs: dm-tifs {
38 compatible = "ti,j721e-dm-sci";
39 ti,host-id = <3>;
40 ti,secure-host;
41 mbox-names = "rx", "tx";
42 mboxes = <&secure_proxy_mcu 21>,
43 <&secure_proxy_mcu 23>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]44 bootph-pre-ram;
Dave Gerlachfe506932020-08-05 22:44:29 +0530[diff] [blame]45 };
46};
47
48&memorycontroller {
49 power-domains = <&k3_pds 8 TI_SCI_PD_SHARED>,
50 <&k3_pds 90 TI_SCI_PD_SHARED>;
51 clocks = <&k3_clks 8 5>, <&k3_clks 30 9>;
Reid Tonking7a2826a2023-10-05 13:12:58 -0500[diff] [blame]52 bootph-pre-ram;
Dave Gerlachfe506932020-08-05 22:44:29 +0530[diff] [blame]53};
54
Reid Tonking7a2826a2023-10-05 13:12:58 -0500[diff] [blame]55&mcu_timer0 {
Manorit Chawdhry1e081eb2024-11-21 17:32:51 +0530[diff] [blame^]56 /delete-property/ clocks;
57 /delete-property/ clocks-names;
58 /delete-property/ assigned-clocks;
59 /delete-property/ assigned-clock-parents;
Aniket Limaye264f2282024-03-06 12:07:48 +0530[diff] [blame]60 clock-frequency = <250000000>;
Reid Tonking7a2826a2023-10-05 13:12:58 -0500[diff] [blame]61 bootph-pre-ram;
62};
Dave Gerlachfe506932020-08-05 22:44:29 +0530[diff] [blame]63
Reid Tonking7a2826a2023-10-05 13:12:58 -0500[diff] [blame]64&secure_proxy_mcu {
65 bootph-pre-ram;
66 status = "okay";
67};
68
69&cbass_mcu_wakeup {
Dave Gerlachfe506932020-08-05 22:44:29 +0530[diff] [blame]70 sysctrler: sysctrler {
Dave Gerlachfe506932020-08-05 22:44:29 +0530[diff] [blame]71 compatible = "ti,am654-system-controller";
Reid Tonking7a2826a2023-10-05 13:12:58 -0500[diff] [blame]72 mboxes= <&secure_proxy_mcu 4>,
73 <&secure_proxy_mcu 5>;
Dave Gerlachfe506932020-08-05 22:44:29 +0530[diff] [blame]74 mbox-names = "tx", "rx";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]75 bootph-pre-ram;
Vignesh Raghavendra98181972021-06-07 19:47:50 +0530[diff] [blame]76 };
Dave Gerlachfe506932020-08-05 22:44:29 +0530[diff] [blame]77};
78
79&dmsc {
Reid Tonking7a2826a2023-10-05 13:12:58 -0500[diff] [blame]80 mboxes = <&secure_proxy_mcu 8>,
81 <&secure_proxy_mcu 6>, <&secure_proxy_mcu 5>;
Dave Gerlachfe506932020-08-05 22:44:29 +0530[diff] [blame]82 mbox-names = "tx", "rx", "notify";
83 ti,host-id = <4>;
84 ti,secure-host;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]85 bootph-pre-ram;
Dave Gerlachfe506932020-08-05 22:44:29 +0530[diff] [blame]86};
87
Gowtham Tammana5075bad2021-07-14 15:52:59 -0500[diff] [blame]88&wkup_vtm0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]89 bootph-pre-ram;
Gowtham Tammana5075bad2021-07-14 15:52:59 -0500[diff] [blame]90};
Aniket Limayee49d5da2024-03-06 12:07:47 +0530[diff] [blame]91
92&ospi0 {
93 reg = <0x0 0x47040000 0x0 0x100>,
94 <0x0 0x50000000 0x0 0x8000000>;
95};
Aniket Limaye06ae6c42024-03-06 12:07:49 +0530[diff] [blame]96
Jonathan Humphreysbeb31062024-08-09 18:01:55 -0500[diff] [blame]97&fss {
98 /* enable ranges missing from the FSS node */
99 ranges = <0x0 0x47000000 0x0 0x47000000 0x0 0x00068400>,
100 <0x0 0x50000000 0x0 0x50000000 0x0 0x08000000>;
101};
102
Aniket Limaye06ae6c42024-03-06 12:07:49 +0530[diff] [blame]103&mcu_ringacc {
104 ti,sci = <&dm_tifs>;
105};
106
107&mcu_udmap {
108 ti,sci = <&dm_tifs>;
109};
Udit Kumar8507ed02024-09-11 14:07:22 +0530[diff] [blame]110
111&wkup_vtm0 {
112 vdd-supply-2 = <&buckb1>;
113 bootph-pre-ram;
114};