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git01.mediatek.com / filogic / uboot / 7a2826a1e9519ec276922206fad393e8b310e3b8 / . / arch / arm / dts / k3-j7200-r5-common-proc-board.dts
blob: f0a73605020f1be5ccb0dd59492aaf96ecdc0c08 [file] [log] [blame]
Dave Gerlachfe506932020-08-05 22:44:29 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
Reid Tonking7a2826a2023-10-05 13:12:58 -0500[diff] [blame^]3 * Copyright (C) 2020-2023 Texas Instruments Incorporated - https://www.ti.com/
Dave Gerlachfe506932020-08-05 22:44:29 +0530[diff] [blame]4 */
5
6/dts-v1/;
7
Reid Tonking7a2826a2023-10-05 13:12:58 -0500[diff] [blame^]8#include "k3-j7200-common-proc-board.dts"
Kevin Scholz7a16fb52021-06-03 08:14:53 -0500[diff] [blame]9#include "k3-j7200-ddr-evm-lp4-2666.dtsi"
Dave Gerlachfe506932020-08-05 22:44:29 +0530[diff] [blame]10#include "k3-j721e-ddr.dtsi"
Reid Tonking7a2826a2023-10-05 13:12:58 -0500[diff] [blame^]11#include "k3-j7200-common-proc-board-u-boot.dtsi"
Dave Gerlachfe506932020-08-05 22:44:29 +0530[diff] [blame]12
13/ {
14 aliases {
15 remoteproc0 = &sysctrler;
16 remoteproc1 = &a72_0;
17 };
18
Dave Gerlachfe506932020-08-05 22:44:29 +0530[diff] [blame]19 a72_0: a72@0 {
20 compatible = "ti,am654-rproc";
21 reg = <0x0 0x00a90000 0x0 0x10>;
22 power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
Manorit Chawdhry2806e832023-04-14 09:47:55 +0530[diff] [blame]23 <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>,
24 <&k3_pds 4 TI_SCI_PD_EXCLUSIVE>;
Dave Gerlachfe506932020-08-05 22:44:29 +0530[diff] [blame]25 resets = <&k3_reset 202 0>;
Nishanth Menon975b78c2021-01-06 13:20:31 -0600[diff] [blame]26 clocks = <&k3_clks 61 1>;
Dave Gerlachfe506932020-08-05 22:44:29 +0530[diff] [blame]27 assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>;
28 assigned-clock-rates = <2000000000>, <200000000>;
29 ti,sci = <&dmsc>;
30 ti,sci-proc-id = <32>;
31 ti,sci-host-id = <10>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]32 bootph-pre-ram;
Dave Gerlachfe506932020-08-05 22:44:29 +0530[diff] [blame]33 };
34
Reid Tonking7a2826a2023-10-05 13:12:58 -0500[diff] [blame^]35 dm_tifs: dm-tifs {
36 compatible = "ti,j721e-dm-sci";
37 ti,host-id = <3>;
38 ti,secure-host;
39 mbox-names = "rx", "tx";
40 mboxes = <&secure_proxy_mcu 21>,
41 <&secure_proxy_mcu 23>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]42 bootph-pre-ram;
Dave Gerlachfe506932020-08-05 22:44:29 +0530[diff] [blame]43 };
44};
45
46&memorycontroller {
47 power-domains = <&k3_pds 8 TI_SCI_PD_SHARED>,
48 <&k3_pds 90 TI_SCI_PD_SHARED>;
49 clocks = <&k3_clks 8 5>, <&k3_clks 30 9>;
Reid Tonking7a2826a2023-10-05 13:12:58 -0500[diff] [blame^]50 bootph-pre-ram;
Dave Gerlachfe506932020-08-05 22:44:29 +0530[diff] [blame]51};
52
Reid Tonking7a2826a2023-10-05 13:12:58 -0500[diff] [blame^]53&mcu_timer0 {
54 clock-frequency = <25000000>;
55 bootph-pre-ram;
56};
Dave Gerlachfe506932020-08-05 22:44:29 +0530[diff] [blame]57
Reid Tonking7a2826a2023-10-05 13:12:58 -0500[diff] [blame^]58&secure_proxy_mcu {
59 bootph-pre-ram;
60 status = "okay";
61};
62
63&cbass_mcu_wakeup {
Dave Gerlachfe506932020-08-05 22:44:29 +0530[diff] [blame]64 sysctrler: sysctrler {
Dave Gerlachfe506932020-08-05 22:44:29 +0530[diff] [blame]65 compatible = "ti,am654-system-controller";
Reid Tonking7a2826a2023-10-05 13:12:58 -0500[diff] [blame^]66 mboxes= <&secure_proxy_mcu 4>,
67 <&secure_proxy_mcu 5>;
Dave Gerlachfe506932020-08-05 22:44:29 +0530[diff] [blame]68 mbox-names = "tx", "rx";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]69 bootph-pre-ram;
Vignesh Raghavendra98181972021-06-07 19:47:50 +0530[diff] [blame]70 };
Dave Gerlachfe506932020-08-05 22:44:29 +0530[diff] [blame]71};
72
73&dmsc {
Reid Tonking7a2826a2023-10-05 13:12:58 -0500[diff] [blame^]74 mboxes = <&secure_proxy_mcu 8>,
75 <&secure_proxy_mcu 6>, <&secure_proxy_mcu 5>;
Dave Gerlachfe506932020-08-05 22:44:29 +0530[diff] [blame]76 mbox-names = "tx", "rx", "notify";
77 ti,host-id = <4>;
78 ti,secure-host;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]79 bootph-pre-ram;
Dave Gerlachfe506932020-08-05 22:44:29 +0530[diff] [blame]80};
81
Gowtham Tammana5075bad2021-07-14 15:52:59 -0500[diff] [blame]82&wkup_vtm0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]83 bootph-pre-ram;
Gowtham Tammana5075bad2021-07-14 15:52:59 -0500[diff] [blame]84};