Rui Miguel Silva | 08ee377 | 2022-06-29 11:06:15 +0100 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * Driver for the NXP ISP1760 chip |
| 4 | * |
| 5 | * Copyright 2021 Linaro, Rui Miguel Silva <rui.silva@linaro.org> |
| 6 | * |
| 7 | */ |
| 8 | |
| 9 | #include <hexdump.h> |
Rui Miguel Silva | 08ee377 | 2022-06-29 11:06:15 +0100 | [diff] [blame] | 10 | #include <asm/cache.h> |
| 11 | #include <cpu_func.h> |
| 12 | #include <dm.h> |
| 13 | #include <dm/device-internal.h> |
| 14 | #include <dm/device_compat.h> |
| 15 | #include <linux/bug.h> |
| 16 | #include <linux/kernel.h> |
| 17 | #include <linux/list.h> |
| 18 | #include <linux/usb/usb_urb_compat.h> |
| 19 | #include <usb.h> |
| 20 | #include <linux/io.h> |
| 21 | #include <linux/iopoll.h> |
| 22 | #include <asm/unaligned.h> |
| 23 | |
| 24 | #include "isp1760-core.h" |
| 25 | #include "isp1760-hcd.h" |
| 26 | #include "isp1760-regs.h" |
| 27 | #include "isp1760-uboot.h" |
| 28 | |
| 29 | #define ISP1760_LANGUAGE_DESC "\4\3\19\4" |
| 30 | #define ISP1760_VENDOR_DESC "\16\3U\0-\0B\0o\0o\0t\0" |
| 31 | #define ISP1760_PRODUCT_NAME_DESC "\52\3I\0S\0P\0-\0 \0H\0o\0s\0t\0 \0C\0o\0n\0t\0r\0o\0l\0l\0e\0r\0" |
| 32 | |
| 33 | static struct kmem_cache *qtd_cachep; |
| 34 | static struct kmem_cache *qh_cachep; |
| 35 | static struct kmem_cache *urb_listitem_cachep; |
| 36 | |
| 37 | typedef void (packet_enqueue)(struct usb_hcd *hcd, struct isp1760_qh *qh, |
| 38 | struct isp1760_qtd *qtd); |
| 39 | |
| 40 | static inline struct isp1760_hcd *hcd_to_priv(struct usb_hcd *hcd) |
| 41 | { |
| 42 | return hcd->hcd_priv; |
| 43 | } |
| 44 | |
| 45 | #define dw_to_le32(x) (cpu_to_le32((__force u32)x)) |
| 46 | #define le32_to_dw(x) ((__force __dw)(le32_to_cpu(x))) |
| 47 | |
| 48 | /* urb state*/ |
| 49 | #define DELETE_URB (0x0008) |
| 50 | #define NO_TRANSFER_ACTIVE (0xffffffff) |
| 51 | |
| 52 | /* Philips Proprietary Transfer Descriptor (PTD) */ |
| 53 | typedef __u32 __bitwise __dw; |
| 54 | struct ptd { |
| 55 | __dw dw0; |
| 56 | __dw dw1; |
| 57 | __dw dw2; |
| 58 | __dw dw3; |
| 59 | __dw dw4; |
| 60 | __dw dw5; |
| 61 | __dw dw6; |
| 62 | __dw dw7; |
| 63 | }; |
| 64 | |
| 65 | struct ptd_le32 { |
| 66 | __le32 dw0; |
| 67 | __le32 dw1; |
| 68 | __le32 dw2; |
| 69 | __le32 dw3; |
| 70 | __le32 dw4; |
| 71 | __le32 dw5; |
| 72 | __le32 dw6; |
| 73 | __le32 dw7; |
| 74 | }; |
| 75 | |
| 76 | #define PTD_OFFSET 0x0400 |
| 77 | #define ISO_PTD_OFFSET 0x0400 |
| 78 | #define INT_PTD_OFFSET 0x0800 |
| 79 | #define ATL_PTD_OFFSET 0x0c00 |
| 80 | #define PAYLOAD_OFFSET 0x1000 |
| 81 | |
| 82 | #define ISP_BANK_0 0x00 |
| 83 | #define ISP_BANK_1 0x01 |
| 84 | #define ISP_BANK_2 0x02 |
| 85 | #define ISP_BANK_3 0x03 |
| 86 | |
| 87 | #define TO_DW(x) ((__force __dw)x) |
| 88 | #define TO_U32(x) ((__force u32)x) |
| 89 | |
| 90 | /* ATL */ |
| 91 | /* DW0 */ |
| 92 | #define DW0_VALID_BIT TO_DW(1) |
| 93 | #define FROM_DW0_VALID(x) (TO_U32(x) & 0x01) |
| 94 | #define TO_DW0_LENGTH(x) TO_DW((((u32)x) << 3)) |
| 95 | #define TO_DW0_MAXPACKET(x) TO_DW((((u32)x) << 18)) |
| 96 | #define TO_DW0_MULTI(x) TO_DW((((u32)x) << 29)) |
| 97 | #define TO_DW0_ENDPOINT(x) TO_DW((((u32)x) << 31)) |
| 98 | /* DW1 */ |
| 99 | #define TO_DW1_DEVICE_ADDR(x) TO_DW((((u32)x) << 3)) |
| 100 | #define TO_DW1_PID_TOKEN(x) TO_DW((((u32)x) << 10)) |
| 101 | #define DW1_TRANS_BULK TO_DW(((u32)2 << 12)) |
| 102 | #define DW1_TRANS_INT TO_DW(((u32)3 << 12)) |
| 103 | #define DW1_TRANS_SPLIT TO_DW(((u32)1 << 14)) |
| 104 | #define DW1_SE_USB_LOSPEED TO_DW(((u32)2 << 16)) |
| 105 | #define TO_DW1_PORT_NUM(x) TO_DW((((u32)x) << 18)) |
| 106 | #define TO_DW1_HUB_NUM(x) TO_DW((((u32)x) << 25)) |
| 107 | /* DW2 */ |
| 108 | #define TO_DW2_DATA_START_ADDR(x) TO_DW((((u32)x) << 8)) |
| 109 | #define TO_DW2_RL(x) TO_DW(((x) << 25)) |
| 110 | #define FROM_DW2_RL(x) ((TO_U32(x) >> 25) & 0xf) |
| 111 | /* DW3 */ |
| 112 | #define FROM_DW3_NRBYTESTRANSFERRED(x) TO_U32((x) & 0x3fff) |
| 113 | #define FROM_DW3_SCS_NRBYTESTRANSFERRED(x) TO_U32((x) & 0x07ff) |
| 114 | #define TO_DW3_NAKCOUNT(x) TO_DW(((x) << 19)) |
| 115 | #define FROM_DW3_NAKCOUNT(x) ((TO_U32(x) >> 19) & 0xf) |
| 116 | #define TO_DW3_CERR(x) TO_DW(((x) << 23)) |
| 117 | #define FROM_DW3_CERR(x) ((TO_U32(x) >> 23) & 0x3) |
| 118 | #define TO_DW3_DATA_TOGGLE(x) TO_DW(((x) << 25)) |
| 119 | #define FROM_DW3_DATA_TOGGLE(x) ((TO_U32(x) >> 25) & 0x1) |
| 120 | #define TO_DW3_PING(x) TO_DW(((x) << 26)) |
| 121 | #define FROM_DW3_PING(x) ((TO_U32(x) >> 26) & 0x1) |
| 122 | #define DW3_ERROR_BIT TO_DW((1 << 28)) |
| 123 | #define DW3_BABBLE_BIT TO_DW((1 << 29)) |
| 124 | #define DW3_HALT_BIT TO_DW((1 << 30)) |
| 125 | #define DW3_ACTIVE_BIT TO_DW((1 << 31)) |
| 126 | #define FROM_DW3_ACTIVE(x) ((TO_U32(x) >> 31) & 0x01) |
| 127 | |
| 128 | #define INT_UNDERRUN BIT(2) |
| 129 | #define INT_BABBLE BIT(1) |
| 130 | #define INT_EXACT BIT(0) |
| 131 | |
| 132 | #define SETUP_PID (2) |
| 133 | #define IN_PID (1) |
| 134 | #define OUT_PID (0) |
| 135 | |
| 136 | /* Errata 1 */ |
| 137 | #define RL_COUNTER (0) |
| 138 | #define NAK_COUNTER (0) |
| 139 | #define ERR_COUNTER (3) |
| 140 | |
| 141 | struct isp1760_qtd { |
| 142 | u8 packet_type; |
| 143 | void *data_buffer; |
| 144 | u32 payload_addr; |
| 145 | |
| 146 | /* the rest is HCD-private */ |
| 147 | struct list_head qtd_list; |
| 148 | struct urb *urb; |
| 149 | size_t length; |
| 150 | size_t actual_length; |
| 151 | |
| 152 | /* |
| 153 | * QTD_ENQUEUED: waiting for transfer (inactive) |
| 154 | * QTD_PAYLOAD_ALLOC: chip mem has been allocated for payload |
| 155 | * QTD_XFER_STARTED: valid ptd has been written to isp176x - only |
| 156 | * interrupt handler may touch this qtd! |
| 157 | * QTD_XFER_COMPLETE: payload has been transferred successfully |
| 158 | * QTD_RETIRE: transfer error/abort qtd |
| 159 | */ |
| 160 | #define QTD_ENQUEUED 0 |
| 161 | #define QTD_PAYLOAD_ALLOC 1 |
| 162 | #define QTD_XFER_STARTED 2 |
| 163 | #define QTD_XFER_COMPLETE 3 |
| 164 | #define QTD_RETIRE 4 |
| 165 | u32 status; |
| 166 | }; |
| 167 | |
| 168 | /* Queue head, one for each active endpoint */ |
| 169 | struct isp1760_qh { |
| 170 | struct list_head qh_list; |
| 171 | struct list_head qtd_list; |
| 172 | int epnum; |
| 173 | u32 toggle; |
| 174 | u32 ping; |
| 175 | int slot; |
| 176 | int tt_buffer_dirty; /* See USB2.0 spec section 11.17.5 */ |
| 177 | }; |
| 178 | |
| 179 | struct urb_listitem { |
| 180 | struct list_head urb_list; |
| 181 | struct urb *urb; |
| 182 | }; |
| 183 | |
| 184 | static const u32 isp1763_hc_portsc1_fields[] = { |
| 185 | [PORT_OWNER] = BIT(13), |
| 186 | [PORT_POWER] = BIT(12), |
| 187 | [PORT_LSTATUS] = BIT(10), |
| 188 | [PORT_RESET] = BIT(8), |
| 189 | [PORT_SUSPEND] = BIT(7), |
| 190 | [PORT_RESUME] = BIT(6), |
| 191 | [PORT_PE] = BIT(2), |
| 192 | [PORT_CSC] = BIT(1), |
| 193 | [PORT_CONNECT] = BIT(0), |
| 194 | }; |
| 195 | |
| 196 | static struct descriptor { |
| 197 | struct usb_device_descriptor device; |
| 198 | struct usb_config_descriptor config; |
| 199 | struct usb_interface_descriptor interface; |
| 200 | struct usb_endpoint_descriptor endpoint; |
| 201 | } __packed rh_descriptor = { |
| 202 | { |
| 203 | /* usb 2.0 root hub device descriptor */ |
| 204 | 0x12, /* __u8 bLength; */ |
| 205 | USB_DT_DEVICE, /* __u8 bDescriptorType; Device */ |
| 206 | 0x0002, /* __le16 bcdUSB; v2.0 */ |
| 207 | |
| 208 | 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */ |
| 209 | 0x00, /* __u8 bDeviceSubClass; */ |
| 210 | 0x00, /* __u8 bDeviceProtocol; [ usb 2.0 no TT ] */ |
| 211 | 0x40, /* __u8 bMaxPacketSize0; 64 Bytes */ |
| 212 | |
| 213 | 0x6b1d, /* __le16 idVendor; Linux Foundation 0x1d6b */ |
| 214 | 0x0200, /* __le16 idProduct; device 0x0002 */ |
| 215 | 0x0001, /* __le16 bcdDevice */ |
| 216 | |
| 217 | 0x03, /* __u8 iManufacturer; */ |
| 218 | 0x02, /* __u8 iProduct; */ |
| 219 | 0x01, /* __u8 iSerialNumber; */ |
| 220 | 0x01 /* __u8 bNumConfigurations; */ |
| 221 | }, { |
| 222 | /* one configuration */ |
| 223 | 0x09, /* __u8 bLength; */ |
| 224 | USB_DT_CONFIG, /* __u8 bDescriptorType; Configuration */ |
| 225 | 0x1900, /* __le16 wTotalLength; */ |
| 226 | 0x01, /* __u8 bNumInterfaces; (1) */ |
| 227 | 0x01, /* __u8 bConfigurationValue; */ |
| 228 | 0x00, /* __u8 iConfiguration; */ |
| 229 | 0xc0, /* __u8 bmAttributes; |
| 230 | * Bit 7: must be set, |
| 231 | * 6: Self-powered, |
| 232 | * 5: Remote wakeup, |
| 233 | * 4..0: resvd |
| 234 | */ |
| 235 | 0x00, /* __u8 MaxPower; */ |
| 236 | }, { |
| 237 | /* one interface */ |
| 238 | 0x09, /* __u8 if_bLength; */ |
| 239 | USB_DT_INTERFACE, /* __u8 if_bDescriptorType; Interface */ |
| 240 | 0x00, /* __u8 if_bInterfaceNumber; */ |
| 241 | 0x00, /* __u8 if_bAlternateSetting; */ |
| 242 | 0x01, /* __u8 if_bNumEndpoints; */ |
| 243 | 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */ |
| 244 | 0x00, /* __u8 if_bInterfaceSubClass; */ |
| 245 | 0x00, /* __u8 if_bInterfaceProtocol; [usb1.1 or single tt] */ |
| 246 | 0x00, /* __u8 if_iInterface; */ |
| 247 | }, { |
| 248 | /* one endpoint (status change endpoint) */ |
| 249 | 0x07, /* __u8 ep_bLength; */ |
| 250 | USB_DT_ENDPOINT, /* __u8 ep_bDescriptorType; Endpoint */ |
| 251 | 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */ |
| 252 | 0x03, /* __u8 ep_bmAttributes; Interrupt */ |
| 253 | /* __le16 ep_wMaxPacketSize; 1 + (MAX_ROOT_PORTS / 8) */ |
| 254 | /* see hub.c:hub_configure() for details. */ |
| 255 | (USB_MAXCHILDREN + 1 + 7) / 8, 0x00, |
| 256 | 0x0c /* __u8 ep_bInterval; (256ms -- usb 2.0 spec) */ |
| 257 | }, |
| 258 | }; |
| 259 | |
| 260 | /* |
| 261 | * Access functions for isp176x registers regmap fields |
| 262 | */ |
| 263 | static u32 isp1760_hcd_read(struct usb_hcd *hcd, u32 field) |
| 264 | { |
| 265 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
| 266 | |
| 267 | return isp1760_field_read(priv->fields, field); |
| 268 | } |
| 269 | |
| 270 | /* |
| 271 | * We need, in isp1763, to write directly the values to the portsc1 |
| 272 | * register so it will make the other values to trigger. |
| 273 | */ |
| 274 | static void isp1760_hcd_portsc1_set_clear(struct isp1760_hcd *priv, u32 field, |
| 275 | u32 val) |
| 276 | { |
| 277 | u32 bit = isp1763_hc_portsc1_fields[field]; |
| 278 | u32 port_status = readl(priv->base + ISP1763_HC_PORTSC1); |
| 279 | |
| 280 | if (val) |
| 281 | writel(port_status | bit, priv->base + ISP1763_HC_PORTSC1); |
| 282 | else |
| 283 | writel(port_status & ~bit, priv->base + ISP1763_HC_PORTSC1); |
| 284 | } |
| 285 | |
| 286 | static void isp1760_hcd_write(struct usb_hcd *hcd, u32 field, u32 val) |
| 287 | { |
| 288 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
| 289 | |
| 290 | if (unlikely(priv->is_isp1763 && |
| 291 | (field >= PORT_OWNER && field <= PORT_CONNECT))) |
| 292 | return isp1760_hcd_portsc1_set_clear(priv, field, val); |
| 293 | |
| 294 | isp1760_field_write(priv->fields, field, val); |
| 295 | } |
| 296 | |
| 297 | static void isp1760_hcd_set(struct usb_hcd *hcd, u32 field) |
| 298 | { |
| 299 | isp1760_hcd_write(hcd, field, 0xFFFFFFFF); |
| 300 | } |
| 301 | |
| 302 | static void isp1760_hcd_clear(struct usb_hcd *hcd, u32 field) |
| 303 | { |
| 304 | isp1760_hcd_write(hcd, field, 0); |
| 305 | } |
| 306 | |
| 307 | static int isp1760_hcd_set_and_wait(struct usb_hcd *hcd, u32 field, |
| 308 | u32 timeout_us) |
| 309 | { |
| 310 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
| 311 | u32 val; |
| 312 | |
| 313 | isp1760_hcd_set(hcd, field); |
| 314 | |
| 315 | return regmap_field_read_poll_timeout(priv->fields[field], val, |
| 316 | val, 0, timeout_us); |
| 317 | } |
| 318 | |
| 319 | static int isp1760_hcd_set_and_wait_swap(struct usb_hcd *hcd, u32 field, |
| 320 | u32 timeout_us) |
| 321 | { |
| 322 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
| 323 | u32 val; |
| 324 | |
| 325 | isp1760_hcd_set(hcd, field); |
| 326 | |
| 327 | return regmap_field_read_poll_timeout(priv->fields[field], val, |
| 328 | !val, 0, timeout_us); |
| 329 | } |
| 330 | |
| 331 | static int isp1760_hcd_clear_and_wait(struct usb_hcd *hcd, u32 field, |
| 332 | u32 timeout_us) |
| 333 | { |
| 334 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
| 335 | u32 val; |
| 336 | |
| 337 | isp1760_hcd_clear(hcd, field); |
| 338 | |
| 339 | return regmap_field_read_poll_timeout(priv->fields[field], val, |
| 340 | !val, 0, timeout_us); |
| 341 | } |
| 342 | |
| 343 | static bool isp1760_hcd_is_set(struct usb_hcd *hcd, u32 field) |
| 344 | { |
| 345 | return !!isp1760_hcd_read(hcd, field); |
| 346 | } |
| 347 | |
| 348 | static bool isp1760_hcd_ppc_is_set(struct usb_hcd *hcd) |
| 349 | { |
| 350 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
| 351 | |
| 352 | if (priv->is_isp1763) |
| 353 | return true; |
| 354 | |
| 355 | return isp1760_hcd_is_set(hcd, HCS_PPC); |
| 356 | } |
| 357 | |
| 358 | static u32 isp1760_hcd_n_ports(struct usb_hcd *hcd) |
| 359 | { |
| 360 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
| 361 | |
| 362 | if (priv->is_isp1763) |
| 363 | return 1; |
| 364 | |
| 365 | return isp1760_hcd_read(hcd, HCS_N_PORTS); |
| 366 | } |
| 367 | |
| 368 | /* |
| 369 | * Access functions for isp176x memory (offset >= 0x0400). |
| 370 | * |
| 371 | * bank_reads8() reads memory locations prefetched by an earlier write to |
| 372 | * HC_MEMORY_REG (see isp176x datasheet). Unless you want to do fancy multi- |
| 373 | * bank optimizations, you should use the more generic mem_read() below. |
| 374 | * |
| 375 | * For access to ptd memory, use the specialized ptd_read() and ptd_write() |
| 376 | * below. |
| 377 | * |
| 378 | * These functions copy via MMIO data to/from the device. memcpy_{to|from}io() |
| 379 | * doesn't quite work because some people have to enforce 32-bit access |
| 380 | */ |
| 381 | static void bank_reads8(void __iomem *src_base, u32 src_offset, u32 bank_addr, |
| 382 | __u32 *dst, u32 bytes) |
| 383 | { |
| 384 | __u32 __iomem *src; |
| 385 | u32 val; |
| 386 | __u8 *src_byteptr; |
| 387 | __u8 *dst_byteptr; |
| 388 | |
| 389 | src = src_base + (bank_addr | src_offset); |
| 390 | |
| 391 | if (src_offset < PAYLOAD_OFFSET) { |
| 392 | while (bytes >= 4) { |
| 393 | *dst = readl_relaxed(src); |
| 394 | bytes -= 4; |
| 395 | src++; |
| 396 | dst++; |
| 397 | } |
| 398 | } else { |
| 399 | while (bytes >= 4) { |
| 400 | *dst = __raw_readl(src); |
| 401 | bytes -= 4; |
| 402 | src++; |
| 403 | dst++; |
| 404 | } |
| 405 | } |
| 406 | |
| 407 | if (!bytes) |
| 408 | return; |
| 409 | |
| 410 | /* in case we have 3, 2 or 1 by left. The dst buffer may not be fully |
| 411 | * allocated. |
| 412 | */ |
| 413 | if (src_offset < PAYLOAD_OFFSET) |
| 414 | val = readl_relaxed(src); |
| 415 | else |
| 416 | val = __raw_readl(src); |
| 417 | |
| 418 | dst_byteptr = (void *)dst; |
| 419 | src_byteptr = (void *)&val; |
| 420 | while (bytes > 0) { |
| 421 | *dst_byteptr = *src_byteptr; |
| 422 | dst_byteptr++; |
| 423 | src_byteptr++; |
| 424 | bytes--; |
| 425 | } |
| 426 | } |
| 427 | |
| 428 | static void isp1760_mem_read(struct usb_hcd *hcd, u32 src_offset, void *dst, |
| 429 | u32 bytes) |
| 430 | { |
| 431 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
| 432 | |
| 433 | isp1760_hcd_write(hcd, MEM_BANK_SEL, ISP_BANK_0); |
| 434 | isp1760_hcd_write(hcd, MEM_START_ADDR, src_offset); |
| 435 | ndelay(100); |
| 436 | |
| 437 | bank_reads8(priv->base, src_offset, ISP_BANK_0, dst, bytes); |
| 438 | } |
| 439 | |
| 440 | /* |
| 441 | * ISP1763 does not have the banks direct host controller memory access, |
| 442 | * needs to use the HC_DATA register. Add data read/write according to this, |
| 443 | * and also adjust 16bit access. |
| 444 | */ |
| 445 | static void isp1763_mem_read(struct usb_hcd *hcd, u16 srcaddr, |
| 446 | u16 *dstptr, u32 bytes) |
| 447 | { |
| 448 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
| 449 | |
| 450 | /* Write the starting device address to the hcd memory register */ |
| 451 | isp1760_reg_write(priv->regs, ISP1763_HC_MEMORY, srcaddr); |
| 452 | ndelay(100); /* Delay between consecutive access */ |
| 453 | |
| 454 | /* As long there are at least 16-bit to read ... */ |
| 455 | while (bytes >= 2) { |
| 456 | *dstptr = __raw_readw(priv->base + ISP1763_HC_DATA); |
| 457 | bytes -= 2; |
| 458 | dstptr++; |
| 459 | } |
| 460 | |
| 461 | /* If there are no more bytes to read, return */ |
| 462 | if (bytes <= 0) |
| 463 | return; |
| 464 | |
| 465 | *((u8 *)dstptr) = (u8)(readw(priv->base + ISP1763_HC_DATA) & 0xFF); |
| 466 | } |
| 467 | |
| 468 | static void mem_read(struct usb_hcd *hcd, u32 src_offset, __u32 *dst, |
| 469 | u32 bytes) |
| 470 | { |
| 471 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
| 472 | |
| 473 | if (!priv->is_isp1763) |
| 474 | return isp1760_mem_read(hcd, src_offset, (u16 *)dst, bytes); |
| 475 | |
| 476 | isp1763_mem_read(hcd, (u16)src_offset, (u16 *)dst, bytes); |
| 477 | } |
| 478 | |
| 479 | static void isp1760_mem_write(void __iomem *dst_base, u32 dst_offset, |
| 480 | __u32 const *src, u32 bytes) |
| 481 | { |
| 482 | __u32 __iomem *dst; |
| 483 | |
| 484 | dst = dst_base + dst_offset; |
| 485 | |
| 486 | if (dst_offset < PAYLOAD_OFFSET) { |
| 487 | while (bytes >= 4) { |
| 488 | writel_relaxed(*src, dst); |
| 489 | bytes -= 4; |
| 490 | src++; |
| 491 | dst++; |
| 492 | } |
| 493 | } else { |
| 494 | while (bytes >= 4) { |
| 495 | __raw_writel(*src, dst); |
| 496 | bytes -= 4; |
| 497 | src++; |
| 498 | dst++; |
| 499 | } |
| 500 | } |
| 501 | |
| 502 | if (!bytes) |
| 503 | return; |
| 504 | /* in case we have 3, 2 or 1 bytes left. The buffer is allocated and the |
| 505 | * extra bytes should not be read by the HW. |
| 506 | */ |
| 507 | |
| 508 | if (dst_offset < PAYLOAD_OFFSET) |
| 509 | writel_relaxed(*src, dst); |
| 510 | else |
| 511 | __raw_writel(*src, dst); |
| 512 | } |
| 513 | |
| 514 | static void isp1763_mem_write(struct usb_hcd *hcd, u16 dstaddr, u16 *src, |
| 515 | u32 bytes) |
| 516 | { |
| 517 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
| 518 | |
| 519 | /* Write the starting device address to the hcd memory register */ |
| 520 | isp1760_reg_write(priv->regs, ISP1763_HC_MEMORY, dstaddr); |
| 521 | ndelay(100); /* Delay between consecutive access */ |
| 522 | |
| 523 | while (bytes >= 2) { |
| 524 | /* Get and write the data; then adjust the data ptr and len */ |
| 525 | __raw_writew(*src, priv->base + ISP1763_HC_DATA); |
| 526 | bytes -= 2; |
| 527 | src++; |
| 528 | } |
| 529 | |
| 530 | /* If there are no more bytes to process, return */ |
| 531 | if (bytes <= 0) |
| 532 | return; |
| 533 | |
| 534 | /* |
| 535 | * The only way to get here is if there is a single byte left, |
| 536 | * get it and write it to the data reg; |
| 537 | */ |
| 538 | writew(*((u8 *)src), priv->base + ISP1763_HC_DATA); |
| 539 | } |
| 540 | |
| 541 | static void mem_write(struct usb_hcd *hcd, u32 dst_offset, __u32 *src, |
| 542 | u32 bytes) |
| 543 | { |
| 544 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
| 545 | |
| 546 | if (!priv->is_isp1763) |
| 547 | return isp1760_mem_write(priv->base, dst_offset, src, bytes); |
| 548 | |
| 549 | isp1763_mem_write(hcd, dst_offset, (u16 *)src, bytes); |
| 550 | } |
| 551 | |
| 552 | /* |
| 553 | * Read and write ptds. 'ptd_offset' should be one of ISO_PTD_OFFSET, |
| 554 | * INT_PTD_OFFSET, and ATL_PTD_OFFSET. 'slot' should be less than 32. |
| 555 | */ |
| 556 | static void isp1760_ptd_read(struct usb_hcd *hcd, u32 ptd_offset, u32 slot, |
| 557 | struct ptd *ptd) |
| 558 | { |
| 559 | u16 src_offset = ptd_offset + slot * sizeof(*ptd); |
| 560 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
| 561 | |
| 562 | isp1760_hcd_write(hcd, MEM_BANK_SEL, ISP_BANK_0); |
| 563 | isp1760_hcd_write(hcd, MEM_START_ADDR, src_offset); |
| 564 | ndelay(90); |
| 565 | |
| 566 | bank_reads8(priv->base, src_offset, ISP_BANK_0, (void *)ptd, |
| 567 | sizeof(*ptd)); |
| 568 | } |
| 569 | |
| 570 | static void isp1763_ptd_read(struct usb_hcd *hcd, u32 ptd_offset, u32 slot, |
| 571 | struct ptd *ptd) |
| 572 | { |
| 573 | u16 src_offset = ptd_offset + slot * sizeof(*ptd); |
| 574 | struct ptd_le32 le32_ptd; |
| 575 | |
| 576 | isp1763_mem_read(hcd, src_offset, (u16 *)&le32_ptd, sizeof(le32_ptd)); |
| 577 | /* Normalize the data obtained */ |
| 578 | ptd->dw0 = le32_to_dw(le32_ptd.dw0); |
| 579 | ptd->dw1 = le32_to_dw(le32_ptd.dw1); |
| 580 | ptd->dw2 = le32_to_dw(le32_ptd.dw2); |
| 581 | ptd->dw3 = le32_to_dw(le32_ptd.dw3); |
| 582 | ptd->dw4 = le32_to_dw(le32_ptd.dw4); |
| 583 | ptd->dw5 = le32_to_dw(le32_ptd.dw5); |
| 584 | ptd->dw6 = le32_to_dw(le32_ptd.dw6); |
| 585 | ptd->dw7 = le32_to_dw(le32_ptd.dw7); |
| 586 | } |
| 587 | |
| 588 | static void ptd_read(struct usb_hcd *hcd, u32 ptd_offset, u32 slot, |
| 589 | struct ptd *ptd) |
| 590 | { |
| 591 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
| 592 | |
| 593 | if (!priv->is_isp1763) |
| 594 | return isp1760_ptd_read(hcd, ptd_offset, slot, ptd); |
| 595 | |
| 596 | isp1763_ptd_read(hcd, ptd_offset, slot, ptd); |
| 597 | } |
| 598 | |
| 599 | static void isp1763_ptd_write(struct usb_hcd *hcd, u32 ptd_offset, u32 slot, |
| 600 | struct ptd *cpu_ptd) |
| 601 | { |
| 602 | u16 dst_offset = ptd_offset + slot * sizeof(*cpu_ptd); |
| 603 | struct ptd_le32 ptd; |
| 604 | |
| 605 | ptd.dw0 = dw_to_le32(cpu_ptd->dw0); |
| 606 | ptd.dw1 = dw_to_le32(cpu_ptd->dw1); |
| 607 | ptd.dw2 = dw_to_le32(cpu_ptd->dw2); |
| 608 | ptd.dw3 = dw_to_le32(cpu_ptd->dw3); |
| 609 | ptd.dw4 = dw_to_le32(cpu_ptd->dw4); |
| 610 | ptd.dw5 = dw_to_le32(cpu_ptd->dw5); |
| 611 | ptd.dw6 = dw_to_le32(cpu_ptd->dw6); |
| 612 | ptd.dw7 = dw_to_le32(cpu_ptd->dw7); |
| 613 | |
| 614 | isp1763_mem_write(hcd, dst_offset, (u16 *)&ptd.dw0, |
| 615 | 8 * sizeof(ptd.dw0)); |
| 616 | } |
| 617 | |
| 618 | static void isp1760_ptd_write(void __iomem *base, u32 ptd_offset, u32 slot, |
| 619 | struct ptd *ptd) |
| 620 | { |
| 621 | u32 dst_offset = ptd_offset + slot * sizeof(*ptd); |
| 622 | |
| 623 | isp1760_mem_write(base, dst_offset + sizeof(ptd->dw0), |
| 624 | (__force u32 *)&ptd->dw1, 7 * sizeof(ptd->dw1)); |
| 625 | /* |
| 626 | * Make sure dw0 gets written last (after other dw's and after payload) |
| 627 | * since it contains the enable bit |
| 628 | */ |
| 629 | wmb(); |
| 630 | isp1760_mem_write(base, dst_offset, (__force u32 *)&ptd->dw0, |
| 631 | sizeof(ptd->dw0)); |
| 632 | } |
| 633 | |
| 634 | static void ptd_write(struct usb_hcd *hcd, u32 ptd_offset, u32 slot, |
| 635 | struct ptd *ptd) |
| 636 | { |
| 637 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
| 638 | |
| 639 | if (!priv->is_isp1763) |
| 640 | return isp1760_ptd_write(priv->base, ptd_offset, slot, ptd); |
| 641 | |
| 642 | isp1763_ptd_write(hcd, ptd_offset, slot, ptd); |
| 643 | } |
| 644 | |
| 645 | /* memory management of the 60kb on the chip from 0x1000 to 0xffff */ |
| 646 | static void init_memory(struct isp1760_hcd *priv) |
| 647 | { |
| 648 | const struct isp1760_memory_layout *mem = priv->memory_layout; |
| 649 | int i, j, curr; |
| 650 | u32 payload_addr; |
| 651 | |
| 652 | payload_addr = PAYLOAD_OFFSET; |
| 653 | |
| 654 | for (i = 0, curr = 0; i < ARRAY_SIZE(mem->blocks); i++, curr += j) { |
| 655 | for (j = 0; j < mem->blocks[i]; j++) { |
| 656 | priv->memory_pool[curr + j].start = payload_addr; |
| 657 | priv->memory_pool[curr + j].size = mem->blocks_size[i]; |
| 658 | priv->memory_pool[curr + j].free = 1; |
| 659 | payload_addr += priv->memory_pool[curr + j].size; |
| 660 | } |
| 661 | } |
| 662 | |
| 663 | WARN_ON(payload_addr - priv->memory_pool[0].start > |
| 664 | mem->payload_area_size); |
| 665 | } |
| 666 | |
| 667 | static void alloc_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd) |
| 668 | { |
| 669 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
| 670 | const struct isp1760_memory_layout *mem = priv->memory_layout; |
| 671 | int i; |
| 672 | |
| 673 | WARN_ON(qtd->payload_addr); |
| 674 | |
| 675 | if (!qtd->length) |
| 676 | return; |
| 677 | |
| 678 | for (i = 0; i < mem->payload_blocks; i++) { |
| 679 | if (priv->memory_pool[i].size >= qtd->length && |
| 680 | priv->memory_pool[i].free) { |
| 681 | priv->memory_pool[i].free = 0; |
| 682 | qtd->payload_addr = priv->memory_pool[i].start; |
| 683 | return; |
| 684 | } |
| 685 | } |
| 686 | } |
| 687 | |
| 688 | static void free_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd) |
| 689 | { |
| 690 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
| 691 | const struct isp1760_memory_layout *mem = priv->memory_layout; |
| 692 | int i; |
| 693 | |
| 694 | if (!qtd->payload_addr) |
| 695 | return; |
| 696 | |
| 697 | for (i = 0; i < mem->payload_blocks; i++) { |
| 698 | if (priv->memory_pool[i].start == qtd->payload_addr) { |
| 699 | WARN_ON(priv->memory_pool[i].free); |
| 700 | priv->memory_pool[i].free = 1; |
| 701 | qtd->payload_addr = 0; |
| 702 | return; |
| 703 | } |
| 704 | } |
| 705 | |
| 706 | WARN_ON(1); |
| 707 | qtd->payload_addr = 0; |
| 708 | } |
| 709 | |
| 710 | /* reset a non-running (STS_HALT == 1) controller */ |
| 711 | static int ehci_reset(struct usb_hcd *hcd) |
| 712 | { |
| 713 | return isp1760_hcd_set_and_wait_swap(hcd, CMD_RESET, 250 * 1000); |
| 714 | } |
| 715 | |
| 716 | static struct isp1760_qh *qh_alloc(gfp_t flags) |
| 717 | { |
| 718 | struct isp1760_qh *qh; |
| 719 | |
| 720 | qh = kmem_cache_alloc(qh_cachep, flags); |
| 721 | if (!qh) |
| 722 | return NULL; |
| 723 | |
| 724 | memset(qh, '\0', qh_cachep->sz); |
| 725 | INIT_LIST_HEAD(&qh->qh_list); |
| 726 | INIT_LIST_HEAD(&qh->qtd_list); |
| 727 | qh->slot = -1; |
| 728 | |
| 729 | return qh; |
| 730 | } |
| 731 | |
| 732 | static void qh_free(struct isp1760_qh *qh) |
| 733 | { |
| 734 | WARN_ON(!list_empty(&qh->qtd_list)); |
| 735 | WARN_ON(qh->slot > -1); |
| 736 | kmem_cache_free(qh_cachep, qh); |
| 737 | } |
| 738 | |
| 739 | /* one-time init, only for memory state */ |
| 740 | static int priv_init(struct usb_hcd *hcd) |
| 741 | { |
| 742 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
| 743 | u32 isoc_cache; |
| 744 | u32 isoc_thres; |
| 745 | int i; |
| 746 | |
| 747 | for (i = 0; i < QH_END; i++) |
| 748 | INIT_LIST_HEAD(&priv->qh_list[i]); |
| 749 | |
| 750 | /* |
| 751 | * hw default: 1K periodic list heads, one per frame. |
| 752 | * periodic_size can shrink by USBCMD update if hcc_params allows. |
| 753 | */ |
| 754 | priv->periodic_size = DEFAULT_I_TDPS; |
| 755 | |
| 756 | if (priv->is_isp1763) { |
| 757 | priv->i_thresh = 2; |
| 758 | return 0; |
| 759 | } |
| 760 | |
| 761 | /* controllers may cache some of the periodic schedule ... */ |
| 762 | isoc_cache = isp1760_hcd_read(hcd, HCC_ISOC_CACHE); |
| 763 | isoc_thres = isp1760_hcd_read(hcd, HCC_ISOC_THRES); |
| 764 | |
| 765 | /* full frame cache */ |
| 766 | if (isoc_cache) |
| 767 | priv->i_thresh = 8; |
| 768 | else /* N microframes cached */ |
| 769 | priv->i_thresh = 2 + isoc_thres; |
| 770 | |
| 771 | return 0; |
| 772 | } |
| 773 | |
| 774 | static int isp1760_hc_setup(struct usb_hcd *hcd) |
| 775 | { |
| 776 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
| 777 | u32 atx_reset; |
| 778 | int result; |
| 779 | u32 scratch; |
| 780 | u32 pattern; |
| 781 | |
| 782 | if (priv->is_isp1763) |
| 783 | pattern = 0xcafe; |
| 784 | else |
| 785 | pattern = 0xdeadcafe; |
| 786 | |
| 787 | isp1760_hcd_write(hcd, HC_SCRATCH, pattern); |
| 788 | |
| 789 | /* Change bus pattern */ |
| 790 | isp1760_hcd_read(hcd, HC_CHIP_ID_HIGH); |
| 791 | scratch = isp1760_hcd_read(hcd, HC_SCRATCH); |
| 792 | if (scratch != pattern) { |
| 793 | printf("Scratch test failed. 0x%08x\n", scratch); |
| 794 | return -ENODEV; |
| 795 | } |
| 796 | |
| 797 | /* |
| 798 | * The RESET_HC bit in the SW_RESET register is supposed to reset the |
| 799 | * host controller without touching the CPU interface registers, but at |
| 800 | * least on the ISP1761 it seems to behave as the RESET_ALL bit and |
| 801 | * reset the whole device. We thus can't use it here, so let's reset |
| 802 | * the host controller through the EHCI USB Command register. The device |
| 803 | * has been reset in core code anyway, so this shouldn't matter. |
| 804 | */ |
| 805 | isp1760_hcd_clear(hcd, ISO_BUF_FILL); |
| 806 | isp1760_hcd_clear(hcd, INT_BUF_FILL); |
| 807 | isp1760_hcd_clear(hcd, ATL_BUF_FILL); |
| 808 | |
| 809 | isp1760_hcd_set(hcd, HC_ATL_PTD_SKIPMAP); |
| 810 | isp1760_hcd_set(hcd, HC_INT_PTD_SKIPMAP); |
| 811 | isp1760_hcd_set(hcd, HC_ISO_PTD_SKIPMAP); |
| 812 | |
| 813 | result = ehci_reset(hcd); |
| 814 | if (result) |
| 815 | return result; |
| 816 | |
| 817 | /* Step 11 passed */ |
| 818 | |
| 819 | /* ATL reset */ |
| 820 | if (priv->is_isp1763) |
| 821 | atx_reset = SW_RESET_RESET_ATX; |
| 822 | else |
| 823 | atx_reset = ALL_ATX_RESET; |
| 824 | |
| 825 | isp1760_hcd_set(hcd, atx_reset); |
| 826 | mdelay(10); |
| 827 | isp1760_hcd_clear(hcd, atx_reset); |
| 828 | |
| 829 | if (priv->is_isp1763) { |
| 830 | isp1760_hcd_set(hcd, HW_OTG_DISABLE); |
| 831 | isp1760_hcd_set(hcd, HW_SW_SEL_HC_DC_CLEAR); |
| 832 | isp1760_hcd_set(hcd, HW_HC_2_DIS_CLEAR); |
| 833 | isp1760_hcd_set(hcd, HW_DM_PULLDOWN); |
| 834 | isp1760_hcd_set(hcd, HW_DP_PULLDOWN); |
| 835 | mdelay(10); |
| 836 | |
| 837 | isp1760_hcd_set(hcd, HW_INTF_LOCK); |
| 838 | } |
| 839 | |
| 840 | isp1760_hcd_set(hcd, HC_INT_IRQ_ENABLE); |
| 841 | isp1760_hcd_set(hcd, HC_ATL_IRQ_ENABLE); |
| 842 | |
| 843 | return priv_init(hcd); |
| 844 | } |
| 845 | |
| 846 | static u32 base_to_chip(u32 base) |
| 847 | { |
| 848 | return ((base - 0x400) >> 3); |
| 849 | } |
| 850 | |
| 851 | static int last_qtd_of_urb(struct isp1760_qtd *qtd, struct isp1760_qh *qh) |
| 852 | { |
| 853 | struct urb *urb; |
| 854 | |
| 855 | if (list_is_last(&qtd->qtd_list, &qh->qtd_list)) |
| 856 | return 1; |
| 857 | |
| 858 | urb = qtd->urb; |
| 859 | qtd = list_entry(qtd->qtd_list.next, typeof(*qtd), qtd_list); |
| 860 | |
| 861 | return (qtd->urb != urb); |
| 862 | } |
| 863 | |
| 864 | /* magic numbers that can affect system performance */ |
| 865 | #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */ |
| 866 | #define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */ |
| 867 | #define EHCI_TUNE_RL_TT 0 |
| 868 | #define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */ |
| 869 | #define EHCI_TUNE_MULT_TT 1 |
| 870 | #define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */ |
| 871 | |
| 872 | static void create_ptd_atl(struct isp1760_qh *qh, struct isp1760_qtd *qtd, |
| 873 | struct ptd *ptd) |
| 874 | { |
| 875 | u32 maxpacket; |
| 876 | u32 multi; |
| 877 | u32 rl = RL_COUNTER; |
| 878 | u32 nak = NAK_COUNTER; |
| 879 | u8 portnr; |
| 880 | u8 hubaddr; |
| 881 | |
| 882 | memset(ptd, 0, sizeof(*ptd)); |
| 883 | |
| 884 | /* according to 3.6.2, max packet len can not be > 0x400 */ |
| 885 | maxpacket = usb_maxpacket(qtd->urb->dev, qtd->urb->pipe); |
| 886 | multi = 1 + ((maxpacket >> 11) & 0x3); |
| 887 | maxpacket &= 0x7ff; |
| 888 | |
| 889 | /* DW0 */ |
| 890 | ptd->dw0 = DW0_VALID_BIT; |
| 891 | ptd->dw0 |= TO_DW0_LENGTH(qtd->length); |
| 892 | ptd->dw0 |= TO_DW0_MAXPACKET(maxpacket); |
| 893 | ptd->dw0 |= TO_DW0_ENDPOINT(usb_pipeendpoint(qtd->urb->pipe)); |
| 894 | |
| 895 | /* DW1 */ |
| 896 | ptd->dw1 = TO_DW((usb_pipeendpoint(qtd->urb->pipe) >> 1)); |
| 897 | ptd->dw1 |= TO_DW1_DEVICE_ADDR(usb_pipedevice(qtd->urb->pipe)); |
| 898 | ptd->dw1 |= TO_DW1_PID_TOKEN(qtd->packet_type); |
| 899 | |
| 900 | if (usb_pipebulk(qtd->urb->pipe)) |
| 901 | ptd->dw1 |= DW1_TRANS_BULK; |
| 902 | else if (usb_pipeint(qtd->urb->pipe)) |
| 903 | ptd->dw1 |= DW1_TRANS_INT; |
| 904 | |
| 905 | if (qtd->urb->dev->speed != USB_SPEED_HIGH) { |
| 906 | /* split transaction */ |
| 907 | |
| 908 | ptd->dw1 |= DW1_TRANS_SPLIT; |
| 909 | if (qtd->urb->dev->speed == USB_SPEED_LOW) |
| 910 | ptd->dw1 |= DW1_SE_USB_LOSPEED; |
| 911 | |
| 912 | if (!qtd->urb->dev->dev->parent_priv_) { |
| 913 | portnr = qtd->urb->dev->portnr; |
| 914 | hubaddr = qtd->urb->dev->devnum; |
| 915 | } else { |
| 916 | usb_find_usb2_hub_address_port(qtd->urb->dev, &hubaddr, |
| 917 | &portnr); |
| 918 | } |
| 919 | |
| 920 | ptd->dw1 |= TO_DW1_PORT_NUM(portnr); |
| 921 | ptd->dw1 |= TO_DW1_HUB_NUM(hubaddr); |
| 922 | |
| 923 | /* SE bit for Split INT transfers */ |
| 924 | if (usb_pipeint(qtd->urb->pipe) && |
| 925 | qtd->urb->dev->speed == USB_SPEED_LOW) |
| 926 | ptd->dw1 |= DW1_SE_USB_LOSPEED; |
| 927 | |
| 928 | rl = 0; |
| 929 | nak = 0; |
| 930 | } else { |
| 931 | ptd->dw0 |= TO_DW0_MULTI(multi); |
| 932 | if (usb_pipecontrol(qtd->urb->pipe) || |
| 933 | usb_pipebulk(qtd->urb->pipe)) |
| 934 | ptd->dw3 |= TO_DW3_PING(qh->ping); |
| 935 | } |
| 936 | /* DW2 */ |
| 937 | ptd->dw2 = 0; |
| 938 | ptd->dw2 |= TO_DW2_DATA_START_ADDR(base_to_chip(qtd->payload_addr)); |
| 939 | ptd->dw2 |= TO_DW2_RL(rl); |
| 940 | |
| 941 | /* DW3 */ |
| 942 | ptd->dw3 |= TO_DW3_NAKCOUNT(nak); |
| 943 | ptd->dw3 |= TO_DW3_DATA_TOGGLE(qh->toggle); |
| 944 | |
| 945 | if (usb_pipecontrol(qtd->urb->pipe)) { |
| 946 | if (qtd->data_buffer == qtd->urb->setup_packet) |
| 947 | ptd->dw3 &= ~TO_DW3_DATA_TOGGLE(1); |
| 948 | else if (last_qtd_of_urb(qtd, qh)) |
| 949 | ptd->dw3 |= TO_DW3_DATA_TOGGLE(1); |
| 950 | } |
| 951 | |
| 952 | ptd->dw3 |= DW3_ACTIVE_BIT; |
| 953 | /* Cerr */ |
| 954 | ptd->dw3 |= TO_DW3_CERR(ERR_COUNTER); |
| 955 | } |
| 956 | |
| 957 | static void transform_add_int(struct isp1760_qh *qh, struct isp1760_qtd *qtd, |
| 958 | struct ptd *ptd) |
| 959 | { |
| 960 | struct usb_host_endpoint *hep = qtd->urb->ep; |
| 961 | struct usb_endpoint_descriptor *epd = &hep->desc; |
| 962 | u32 usof; |
| 963 | u32 period; |
| 964 | |
| 965 | /* |
| 966 | * Most of this is guessing. ISP1761 datasheet is quite unclear, and |
| 967 | * the algorithm from the original Philips driver code, which was |
| 968 | * pretty much used in this driver before as well, is quite horrendous |
| 969 | * and, i believe, incorrect. The code below follows the datasheet and |
| 970 | * USB2.0 spec as far as I can tell, and plug/unplug seems to be much |
| 971 | * more reliable this way (fingers crossed...). |
| 972 | */ |
| 973 | |
| 974 | if (qtd->urb->dev->speed == USB_SPEED_HIGH) { |
| 975 | /* urb->interval is in units of microframes (1/8 ms) */ |
| 976 | period = epd->bInterval >> 3; |
| 977 | |
| 978 | if (epd->bInterval > 4) |
| 979 | usof = 0x01; /* One bit set => interval 1 ms * uFrame-match */ |
| 980 | else if (epd->bInterval > 2) |
| 981 | usof = 0x22; /* Two bits set => interval 1/2 ms */ |
| 982 | else if (epd->bInterval > 1) |
| 983 | usof = 0x55; /* Four bits set => interval 1/4 ms */ |
| 984 | else |
| 985 | usof = 0xff; /* All bits set => interval 1/8 ms */ |
| 986 | } else { |
| 987 | /* urb->interval is in units of frames (1 ms) */ |
| 988 | period = epd->bInterval; |
| 989 | /* Execute Start Split on any of the four first uFrames */ |
| 990 | usof = 0x0f; |
| 991 | |
| 992 | /* |
| 993 | * First 8 bits in dw5 is uSCS and "specifies which uSOF the |
| 994 | * complete split needs to be sent. Valid only for IN." Also, |
| 995 | * "All bits can be set to one for every transfer." (p 82, |
| 996 | * ISP1761 data sheet.) 0x1c is from Philips driver. Where did |
| 997 | * that number come from? 0xff seems to work fine... |
| 998 | */ |
| 999 | /* Execute Complete Split on any uFrame */ |
| 1000 | ptd->dw5 = TO_DW(0xff); |
| 1001 | } |
| 1002 | |
| 1003 | /* Ensure equal or shorter period than requested */ |
| 1004 | period = period >> 1; |
| 1005 | /* Mask off too large values and lowest unused 3 bits */ |
| 1006 | period &= 0xf8; |
| 1007 | |
| 1008 | ptd->dw2 |= TO_DW(period); |
| 1009 | ptd->dw4 = TO_DW(usof); |
| 1010 | } |
| 1011 | |
| 1012 | static void create_ptd_int(struct isp1760_qh *qh, struct isp1760_qtd *qtd, |
| 1013 | struct ptd *ptd) |
| 1014 | { |
| 1015 | create_ptd_atl(qh, qtd, ptd); |
| 1016 | transform_add_int(qh, qtd, ptd); |
| 1017 | } |
| 1018 | |
| 1019 | static void isp1760_urb_done(struct usb_hcd *hcd, struct urb *urb) |
| 1020 | { |
| 1021 | if (usb_pipein(urb->pipe) && usb_pipetype(urb->pipe) != PIPE_CONTROL) { |
| 1022 | void *ptr; |
| 1023 | |
| 1024 | for (ptr = urb->transfer_buffer; |
| 1025 | ptr < urb->transfer_buffer + urb->transfer_buffer_length; |
| 1026 | ptr += PAGE_SIZE) |
| 1027 | flush_dcache_range((unsigned long)ptr, |
| 1028 | (unsigned long)ptr + PAGE_SIZE); |
| 1029 | } |
| 1030 | |
| 1031 | /* complete() can reenter this HCD */ |
| 1032 | usb_hcd_unlink_urb_from_ep(hcd, urb); |
| 1033 | usb_hcd_giveback_urb(hcd, urb, urb->status); |
| 1034 | } |
| 1035 | |
| 1036 | static struct isp1760_qtd *qtd_alloc(gfp_t flags, struct urb *urb, |
| 1037 | u8 packet_type) |
| 1038 | { |
| 1039 | struct isp1760_qtd *qtd; |
| 1040 | |
| 1041 | qtd = kmem_cache_alloc(qtd_cachep, flags); |
| 1042 | if (!qtd) |
| 1043 | return NULL; |
| 1044 | |
| 1045 | memset(qtd, '\0', sizeof(*qtd)); |
| 1046 | INIT_LIST_HEAD(&qtd->qtd_list); |
| 1047 | qtd->urb = urb; |
| 1048 | qtd->packet_type = packet_type; |
| 1049 | qtd->status = QTD_ENQUEUED; |
| 1050 | qtd->actual_length = 0; |
| 1051 | |
| 1052 | return qtd; |
| 1053 | } |
| 1054 | |
| 1055 | static void qtd_free(struct isp1760_qtd *qtd) |
| 1056 | { |
| 1057 | WARN_ON(qtd->payload_addr); |
| 1058 | kmem_cache_free(qtd_cachep, qtd); |
| 1059 | } |
| 1060 | |
| 1061 | static void start_bus_transfer(struct usb_hcd *hcd, u32 ptd_offset, int slot, |
| 1062 | struct isp1760_slotinfo *slots, |
| 1063 | struct isp1760_qtd *qtd, struct isp1760_qh *qh, |
| 1064 | struct ptd *ptd) |
| 1065 | { |
| 1066 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
| 1067 | const struct isp1760_memory_layout *mem = priv->memory_layout; |
| 1068 | int skip_map; |
| 1069 | |
| 1070 | WARN_ON((slot < 0) || (slot > mem->slot_num - 1)); |
| 1071 | WARN_ON(qtd->length && !qtd->payload_addr); |
| 1072 | WARN_ON(slots[slot].qtd); |
| 1073 | WARN_ON(slots[slot].qh); |
| 1074 | WARN_ON(qtd->status != QTD_PAYLOAD_ALLOC); |
| 1075 | |
| 1076 | if (priv->is_isp1763) |
| 1077 | ndelay(100); |
| 1078 | |
| 1079 | /* Make sure done map has not triggered from some unlinked transfer */ |
| 1080 | if (ptd_offset == ATL_PTD_OFFSET) { |
| 1081 | skip_map = isp1760_hcd_read(hcd, HC_ATL_PTD_SKIPMAP); |
| 1082 | isp1760_hcd_write(hcd, HC_ATL_PTD_SKIPMAP, |
| 1083 | skip_map | (1 << slot)); |
| 1084 | priv->atl_done_map |= isp1760_hcd_read(hcd, HC_ATL_PTD_DONEMAP); |
| 1085 | priv->atl_done_map &= ~(1 << slot); |
| 1086 | } else { |
| 1087 | skip_map = isp1760_hcd_read(hcd, HC_INT_PTD_SKIPMAP); |
| 1088 | isp1760_hcd_write(hcd, HC_INT_PTD_SKIPMAP, |
| 1089 | skip_map | (1 << slot)); |
| 1090 | priv->int_done_map |= isp1760_hcd_read(hcd, HC_INT_PTD_DONEMAP); |
| 1091 | priv->int_done_map &= ~(1 << slot); |
| 1092 | } |
| 1093 | |
| 1094 | skip_map &= ~(1 << slot); |
| 1095 | qh->slot = slot; |
| 1096 | qtd->status = QTD_XFER_STARTED; |
| 1097 | slots[slot].qtd = qtd; |
| 1098 | slots[slot].qh = qh; |
| 1099 | |
| 1100 | ptd_write(hcd, ptd_offset, slot, ptd); |
| 1101 | |
| 1102 | if (ptd_offset == ATL_PTD_OFFSET) |
| 1103 | isp1760_hcd_write(hcd, HC_ATL_PTD_SKIPMAP, skip_map); |
| 1104 | else |
| 1105 | isp1760_hcd_write(hcd, HC_INT_PTD_SKIPMAP, skip_map); |
| 1106 | } |
| 1107 | |
| 1108 | static int is_short_bulk(struct isp1760_qtd *qtd) |
| 1109 | { |
| 1110 | return (usb_pipebulk(qtd->urb->pipe) && |
| 1111 | (qtd->actual_length < qtd->length)); |
| 1112 | } |
| 1113 | |
| 1114 | static void collect_qtds(struct usb_hcd *hcd, struct isp1760_qh *qh, |
| 1115 | struct list_head *urb_list) |
| 1116 | { |
| 1117 | struct isp1760_qtd *qtd, *qtd_next; |
| 1118 | struct urb_listitem *urb_listitem; |
| 1119 | int last_qtd; |
| 1120 | |
| 1121 | list_for_each_entry_safe(qtd, qtd_next, &qh->qtd_list, qtd_list) { |
| 1122 | if (qtd->status < QTD_XFER_COMPLETE) |
| 1123 | break; |
| 1124 | |
| 1125 | last_qtd = last_qtd_of_urb(qtd, qh); |
| 1126 | |
| 1127 | if (!last_qtd && qtd->status == QTD_RETIRE) |
| 1128 | qtd_next->status = QTD_RETIRE; |
| 1129 | |
| 1130 | if (qtd->status == QTD_XFER_COMPLETE) { |
| 1131 | if (qtd->actual_length) { |
| 1132 | switch (qtd->packet_type) { |
| 1133 | case IN_PID: |
| 1134 | mem_read(hcd, qtd->payload_addr, |
| 1135 | qtd->data_buffer, |
| 1136 | qtd->actual_length); |
| 1137 | fallthrough; |
| 1138 | case OUT_PID: |
| 1139 | qtd->urb->actual_length += |
| 1140 | qtd->actual_length; |
| 1141 | fallthrough; |
| 1142 | case SETUP_PID: |
| 1143 | break; |
| 1144 | } |
| 1145 | } |
| 1146 | |
| 1147 | if (is_short_bulk(qtd)) { |
| 1148 | if (qtd->urb->transfer_flags & URB_SHORT_NOT_OK) |
| 1149 | qtd->urb->status = -EREMOTEIO; |
| 1150 | if (!last_qtd) |
| 1151 | qtd_next->status = QTD_RETIRE; |
| 1152 | } |
| 1153 | } |
| 1154 | |
| 1155 | if (qtd->payload_addr) |
| 1156 | free_mem(hcd, qtd); |
| 1157 | |
| 1158 | if (last_qtd) { |
| 1159 | if (qtd->status == QTD_RETIRE && |
| 1160 | qtd->urb->status == -EINPROGRESS) |
| 1161 | qtd->urb->status = -EPIPE; |
| 1162 | |
| 1163 | /* Defer calling of urb_done() since it releases lock */ |
| 1164 | urb_listitem = kmem_cache_alloc(urb_listitem_cachep, |
| 1165 | GFP_ATOMIC); |
| 1166 | if (unlikely(!urb_listitem)) |
| 1167 | break; /* Try again on next call */ |
| 1168 | urb_listitem->urb = qtd->urb; |
| 1169 | list_add_tail(&urb_listitem->urb_list, urb_list); |
| 1170 | } |
| 1171 | |
| 1172 | list_del(&qtd->qtd_list); |
| 1173 | qtd_free(qtd); |
| 1174 | } |
| 1175 | } |
| 1176 | |
| 1177 | #define ENQUEUE_DEPTH 2 |
| 1178 | static void enqueue_qtds(struct usb_hcd *hcd, struct isp1760_qh *qh) |
| 1179 | { |
| 1180 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
| 1181 | const struct isp1760_memory_layout *mem = priv->memory_layout; |
| 1182 | int slot_num = mem->slot_num; |
| 1183 | int ptd_offset; |
| 1184 | struct isp1760_slotinfo *slots; |
| 1185 | int curr_slot, free_slot; |
| 1186 | int n; |
| 1187 | struct ptd ptd; |
| 1188 | struct isp1760_qtd *qtd; |
| 1189 | |
| 1190 | if (unlikely(list_empty(&qh->qtd_list))) |
| 1191 | return; |
| 1192 | |
| 1193 | /* Make sure this endpoint's TT buffer is clean before queueing ptds */ |
| 1194 | if (qh->tt_buffer_dirty) |
| 1195 | return; |
| 1196 | |
| 1197 | if (usb_pipeint(list_entry(qh->qtd_list.next, struct isp1760_qtd, |
| 1198 | qtd_list)->urb->pipe)) { |
| 1199 | ptd_offset = INT_PTD_OFFSET; |
| 1200 | slots = priv->int_slots; |
| 1201 | } else { |
| 1202 | ptd_offset = ATL_PTD_OFFSET; |
| 1203 | slots = priv->atl_slots; |
| 1204 | } |
| 1205 | |
| 1206 | free_slot = -1; |
| 1207 | for (curr_slot = 0; curr_slot < slot_num; curr_slot++) { |
| 1208 | if (free_slot == -1 && !slots[curr_slot].qtd) |
| 1209 | free_slot = curr_slot; |
| 1210 | if (slots[curr_slot].qh == qh) |
| 1211 | break; |
| 1212 | } |
| 1213 | |
| 1214 | n = 0; |
| 1215 | list_for_each_entry(qtd, &qh->qtd_list, qtd_list) { |
| 1216 | if (qtd->status == QTD_ENQUEUED) { |
| 1217 | WARN_ON(qtd->payload_addr); |
| 1218 | alloc_mem(hcd, qtd); |
| 1219 | if (qtd->length && !qtd->payload_addr) |
| 1220 | break; |
| 1221 | |
| 1222 | if (qtd->length && (qtd->packet_type == SETUP_PID || |
| 1223 | qtd->packet_type == OUT_PID)) { |
| 1224 | mem_write(hcd, qtd->payload_addr, |
| 1225 | qtd->data_buffer, qtd->length); |
| 1226 | } |
| 1227 | |
| 1228 | qtd->status = QTD_PAYLOAD_ALLOC; |
| 1229 | } |
| 1230 | |
| 1231 | if (qtd->status == QTD_PAYLOAD_ALLOC) { |
| 1232 | /* Start xfer for this endpoint if not already done */ |
| 1233 | if ((curr_slot > slot_num - 1) && (free_slot > -1)) { |
| 1234 | if (usb_pipeint(qtd->urb->pipe)) |
| 1235 | create_ptd_int(qh, qtd, &ptd); |
| 1236 | else |
| 1237 | create_ptd_atl(qh, qtd, &ptd); |
| 1238 | |
| 1239 | start_bus_transfer(hcd, ptd_offset, free_slot, |
| 1240 | slots, qtd, qh, &ptd); |
| 1241 | curr_slot = free_slot; |
| 1242 | } |
| 1243 | |
| 1244 | n++; |
| 1245 | if (n >= ENQUEUE_DEPTH) |
| 1246 | break; |
| 1247 | } |
| 1248 | } |
| 1249 | } |
| 1250 | |
| 1251 | static void schedule_ptds(struct usb_hcd *hcd) |
| 1252 | { |
| 1253 | struct isp1760_hcd *priv; |
| 1254 | struct isp1760_qh *qh, *qh_next; |
| 1255 | struct list_head *ep_queue; |
| 1256 | LIST_HEAD(urb_list); |
| 1257 | struct urb_listitem *urb_listitem, *urb_listitem_next; |
| 1258 | int i; |
| 1259 | |
| 1260 | if (!hcd) { |
| 1261 | WARN_ON(1); |
| 1262 | return; |
| 1263 | } |
| 1264 | |
| 1265 | priv = hcd_to_priv(hcd); |
| 1266 | |
| 1267 | /* |
| 1268 | * check finished/retired xfers, transfer payloads, call urb_done() |
| 1269 | */ |
| 1270 | for (i = 0; i < QH_END; i++) { |
| 1271 | ep_queue = &priv->qh_list[i]; |
| 1272 | list_for_each_entry_safe(qh, qh_next, ep_queue, qh_list) |
| 1273 | collect_qtds(hcd, qh, &urb_list); |
| 1274 | } |
| 1275 | |
| 1276 | list_for_each_entry_safe(urb_listitem, urb_listitem_next, &urb_list, |
| 1277 | urb_list) { |
| 1278 | isp1760_urb_done(hcd, urb_listitem->urb); |
| 1279 | kmem_cache_free(urb_listitem_cachep, urb_listitem); |
| 1280 | } |
| 1281 | |
| 1282 | /* |
| 1283 | * Schedule packets for transfer. |
| 1284 | * |
| 1285 | * According to USB2.0 specification: |
| 1286 | * |
| 1287 | * 1st prio: interrupt xfers, up to 80 % of bandwidth |
| 1288 | * 2nd prio: control xfers |
| 1289 | * 3rd prio: bulk xfers |
| 1290 | * |
| 1291 | * ... but let's use a simpler scheme here (mostly because ISP1761 doc |
| 1292 | * is very unclear on how to prioritize traffic): |
| 1293 | * |
| 1294 | * 1) Enqueue any queued control transfers, as long as payload chip mem |
| 1295 | * and PTD ATL slots are available. |
| 1296 | * 2) Enqueue any queued INT transfers, as long as payload chip mem |
| 1297 | * and PTD INT slots are available. |
| 1298 | * 3) Enqueue any queued bulk transfers, as long as payload chip mem |
| 1299 | * and PTD ATL slots are available. |
| 1300 | * |
| 1301 | * Use double buffering (ENQUEUE_DEPTH==2) as a compromise between |
| 1302 | * conservation of chip mem and performance. |
| 1303 | * |
| 1304 | * I'm sure this scheme could be improved upon! |
| 1305 | */ |
| 1306 | for (i = 0; i < QH_END; i++) { |
| 1307 | ep_queue = &priv->qh_list[i]; |
| 1308 | list_for_each_entry_safe(qh, qh_next, ep_queue, qh_list) |
| 1309 | enqueue_qtds(hcd, qh); |
| 1310 | } |
| 1311 | } |
| 1312 | |
| 1313 | #define PTD_STATE_QTD_DONE 1 |
| 1314 | #define PTD_STATE_QTD_RELOAD 2 |
| 1315 | #define PTD_STATE_URB_RETIRE 3 |
| 1316 | |
| 1317 | static int check_int_transfer(struct usb_hcd *hcd, struct ptd *ptd, |
| 1318 | struct urb *urb) |
| 1319 | { |
| 1320 | u32 dw4; |
| 1321 | int i; |
| 1322 | |
| 1323 | dw4 = TO_U32(ptd->dw4); |
| 1324 | dw4 >>= 8; |
| 1325 | |
| 1326 | /* |
| 1327 | * FIXME: ISP1761 datasheet does not say what to do with these. Do we |
| 1328 | * need to handle these errors? Is it done in hardware? |
| 1329 | */ |
| 1330 | if (ptd->dw3 & DW3_HALT_BIT) { |
| 1331 | urb->status = -EPROTO; /* Default unknown error */ |
| 1332 | |
| 1333 | for (i = 0; i < 8; i++) { |
| 1334 | switch (dw4 & 0x7) { |
| 1335 | case INT_UNDERRUN: |
| 1336 | printf("underrun during uFrame %d\n", i); |
| 1337 | urb->status = -ECOMM; /* Could not write data */ |
| 1338 | break; |
| 1339 | case INT_EXACT: |
| 1340 | printf("transaction error uFrame %d\n", i); |
| 1341 | /* timeout, bad CRC, PID error etc. */ |
| 1342 | urb->status = -EPROTO; |
| 1343 | break; |
| 1344 | case INT_BABBLE: |
| 1345 | printf("babble error during uFrame %d\n", i); |
| 1346 | urb->status = -EOVERFLOW; |
| 1347 | break; |
| 1348 | } |
| 1349 | dw4 >>= 3; |
| 1350 | } |
| 1351 | |
| 1352 | return PTD_STATE_URB_RETIRE; |
| 1353 | } |
| 1354 | |
| 1355 | return PTD_STATE_QTD_DONE; |
| 1356 | } |
| 1357 | |
| 1358 | static int check_atl_transfer(struct usb_hcd *hcd, struct ptd *ptd, |
| 1359 | struct urb *urb) |
| 1360 | { |
| 1361 | WARN_ON(!ptd); |
| 1362 | if (ptd->dw3 & DW3_HALT_BIT) { |
| 1363 | if (ptd->dw3 & DW3_BABBLE_BIT) |
| 1364 | urb->status = -EOVERFLOW; |
| 1365 | else if (FROM_DW3_CERR(ptd->dw3)) |
| 1366 | urb->status = -EPIPE; /* Stall */ |
| 1367 | else |
| 1368 | urb->status = -EPROTO; /* Unknown */ |
| 1369 | |
| 1370 | /* |
| 1371 | * useful debug |
| 1372 | * printf("%s: ptd error:\n" |
| 1373 | * " dw0: %08x dw1: %08x dw2: %08x dw3: %08x\n" |
| 1374 | * " dw4: %08x dw5: %08x dw6: %08x dw7: %08x\n", |
| 1375 | * __func__, |
| 1376 | * ptd->dw0, ptd->dw1, ptd->dw2, ptd->dw3, |
| 1377 | * ptd->dw4, ptd->dw5, ptd->dw6, ptd->dw7); |
| 1378 | */ |
| 1379 | |
| 1380 | return PTD_STATE_URB_RETIRE; |
| 1381 | } |
| 1382 | |
| 1383 | /* Transfer Error, *but* active and no HALT -> reload */ |
| 1384 | if ((ptd->dw3 & DW3_ERROR_BIT) && (ptd->dw3 & DW3_ACTIVE_BIT)) |
| 1385 | return PTD_STATE_QTD_RELOAD; |
| 1386 | |
| 1387 | /* |
| 1388 | * NAKs are handled in HW by the chip. Usually if the |
| 1389 | * device is not able to send data fast enough. |
| 1390 | * This happens mostly on slower hardware. |
| 1391 | */ |
| 1392 | if (!FROM_DW3_NAKCOUNT(ptd->dw3) && (ptd->dw3 & DW3_ACTIVE_BIT)) |
| 1393 | return PTD_STATE_QTD_RELOAD; |
| 1394 | |
| 1395 | return PTD_STATE_QTD_DONE; |
| 1396 | } |
| 1397 | |
| 1398 | static void handle_done_ptds(struct usb_hcd *hcd) |
| 1399 | { |
| 1400 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
| 1401 | struct isp1760_slotinfo *slots; |
| 1402 | struct isp1760_qtd *qtd; |
| 1403 | struct isp1760_qh *qh; |
| 1404 | struct ptd ptd; |
| 1405 | u32 ptd_offset; |
| 1406 | int modified; |
| 1407 | int skip_map; |
| 1408 | int state; |
| 1409 | int slot; |
| 1410 | |
| 1411 | skip_map = isp1760_hcd_read(hcd, HC_INT_PTD_SKIPMAP); |
| 1412 | priv->int_done_map &= ~skip_map; |
| 1413 | skip_map = isp1760_hcd_read(hcd, HC_ATL_PTD_SKIPMAP); |
| 1414 | priv->atl_done_map &= ~skip_map; |
| 1415 | |
| 1416 | modified = priv->int_done_map || priv->atl_done_map; |
| 1417 | |
| 1418 | while (priv->int_done_map || priv->atl_done_map) { |
| 1419 | if (priv->int_done_map) { |
| 1420 | /* INT ptd */ |
| 1421 | slot = __ffs(priv->int_done_map); |
| 1422 | priv->int_done_map &= ~(1 << slot); |
| 1423 | slots = priv->int_slots; |
| 1424 | /* |
| 1425 | * This should not trigger, and could be removed if |
| 1426 | * noone have any problems with it triggering: |
| 1427 | */ |
| 1428 | if (!slots[slot].qh) { |
| 1429 | WARN_ON(1); |
| 1430 | continue; |
| 1431 | } |
| 1432 | ptd_offset = INT_PTD_OFFSET; |
| 1433 | ptd_read(hcd, INT_PTD_OFFSET, slot, &ptd); |
| 1434 | state = check_int_transfer(hcd, &ptd, |
| 1435 | slots[slot].qtd->urb); |
| 1436 | } else { |
| 1437 | /* ATL ptd */ |
| 1438 | slot = __ffs(priv->atl_done_map); |
| 1439 | priv->atl_done_map &= ~(1 << slot); |
| 1440 | slots = priv->atl_slots; |
| 1441 | /* |
| 1442 | * This should not trigger, and could be removed if |
| 1443 | * noone have any problems with it triggering: |
| 1444 | */ |
| 1445 | if (!slots[slot].qh) { |
| 1446 | WARN_ON(1); |
| 1447 | continue; |
| 1448 | } |
| 1449 | ptd_offset = ATL_PTD_OFFSET; |
| 1450 | ptd_read(hcd, ATL_PTD_OFFSET, slot, &ptd); |
| 1451 | state = check_atl_transfer(hcd, &ptd, |
| 1452 | slots[slot].qtd->urb); |
| 1453 | } |
| 1454 | |
| 1455 | qtd = slots[slot].qtd; |
| 1456 | slots[slot].qtd = NULL; |
| 1457 | qh = slots[slot].qh; |
| 1458 | slots[slot].qh = NULL; |
| 1459 | qh->slot = -1; |
| 1460 | |
| 1461 | WARN_ON(qtd->status != QTD_XFER_STARTED); |
| 1462 | |
| 1463 | switch (state) { |
| 1464 | case PTD_STATE_QTD_DONE: |
| 1465 | if (usb_pipeint(qtd->urb->pipe) && |
| 1466 | qtd->urb->dev->speed != USB_SPEED_HIGH) |
| 1467 | qtd->actual_length = |
| 1468 | FROM_DW3_SCS_NRBYTESTRANSFERRED(ptd.dw3); |
| 1469 | else |
| 1470 | qtd->actual_length = |
| 1471 | FROM_DW3_NRBYTESTRANSFERRED(ptd.dw3); |
| 1472 | |
| 1473 | qtd->status = QTD_XFER_COMPLETE; |
| 1474 | |
| 1475 | if (list_is_last(&qtd->qtd_list, &qh->qtd_list) || |
| 1476 | is_short_bulk(qtd)) |
| 1477 | qtd = NULL; |
| 1478 | else |
| 1479 | qtd = list_entry(qtd->qtd_list.next, |
| 1480 | typeof(*qtd), qtd_list); |
| 1481 | |
| 1482 | qh->toggle = FROM_DW3_DATA_TOGGLE(ptd.dw3); |
| 1483 | qh->ping = FROM_DW3_PING(ptd.dw3); |
| 1484 | |
| 1485 | break; |
| 1486 | |
| 1487 | case PTD_STATE_QTD_RELOAD: /* QTD_RETRY, for atls only */ |
| 1488 | qtd->status = QTD_PAYLOAD_ALLOC; |
| 1489 | ptd.dw0 |= DW0_VALID_BIT; |
| 1490 | /* RL counter = ERR counter */ |
| 1491 | ptd.dw3 &= ~TO_DW3_NAKCOUNT(0xf); |
| 1492 | ptd.dw3 |= TO_DW3_NAKCOUNT(FROM_DW2_RL(ptd.dw2)); |
| 1493 | ptd.dw3 &= ~TO_DW3_CERR(3); |
| 1494 | ptd.dw3 |= TO_DW3_CERR(ERR_COUNTER); |
| 1495 | |
| 1496 | qh->toggle = FROM_DW3_DATA_TOGGLE(ptd.dw3); |
| 1497 | qh->ping = FROM_DW3_PING(ptd.dw3); |
| 1498 | break; |
| 1499 | |
| 1500 | case PTD_STATE_URB_RETIRE: |
| 1501 | qtd->status = QTD_RETIRE; |
| 1502 | qtd = NULL; |
| 1503 | qh->toggle = 0; |
| 1504 | qh->ping = 0; |
| 1505 | break; |
| 1506 | |
| 1507 | default: |
| 1508 | WARN_ON(1); |
| 1509 | continue; |
| 1510 | } |
| 1511 | |
| 1512 | if (qtd && qtd->status == QTD_PAYLOAD_ALLOC) { |
| 1513 | if (slots == priv->int_slots) { |
| 1514 | if (state == PTD_STATE_QTD_RELOAD) |
| 1515 | dev_err(priv->dev, |
| 1516 | "PTD_STATE_QTD_RELOAD on interrupt packet\n"); |
| 1517 | if (state != PTD_STATE_QTD_RELOAD) |
| 1518 | create_ptd_int(qh, qtd, &ptd); |
| 1519 | } else { |
| 1520 | if (state != PTD_STATE_QTD_RELOAD) |
| 1521 | create_ptd_atl(qh, qtd, &ptd); |
| 1522 | } |
| 1523 | |
| 1524 | start_bus_transfer(hcd, ptd_offset, slot, slots, qtd, |
| 1525 | qh, &ptd); |
| 1526 | } |
| 1527 | } |
| 1528 | |
| 1529 | if (modified) |
| 1530 | schedule_ptds(hcd); |
| 1531 | } |
| 1532 | |
| 1533 | static irqreturn_t isp1760_irq(int irq, void *__hci) |
| 1534 | { |
| 1535 | struct usb_hcd *hcd = __hci; |
| 1536 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
| 1537 | irqreturn_t irqret = IRQ_NONE; |
| 1538 | u32 int_reg; |
| 1539 | u32 imask; |
| 1540 | |
| 1541 | imask = isp1760_hcd_read(hcd, HC_INTERRUPT); |
| 1542 | if (unlikely(!imask)) |
| 1543 | return irqret; |
| 1544 | |
| 1545 | int_reg = priv->is_isp1763 ? ISP1763_HC_INTERRUPT : |
| 1546 | ISP176x_HC_INTERRUPT; |
| 1547 | isp1760_reg_write(priv->regs, int_reg, imask); |
| 1548 | |
| 1549 | priv->int_done_map |= isp1760_hcd_read(hcd, HC_INT_PTD_DONEMAP); |
| 1550 | priv->atl_done_map |= isp1760_hcd_read(hcd, HC_ATL_PTD_DONEMAP); |
| 1551 | |
| 1552 | handle_done_ptds(hcd); |
| 1553 | |
| 1554 | irqret = IRQ_HANDLED; |
| 1555 | |
| 1556 | return irqret; |
| 1557 | } |
| 1558 | |
| 1559 | static int isp1763_run(struct usb_hcd *hcd) |
| 1560 | { |
| 1561 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
| 1562 | int retval; |
| 1563 | u32 chipid_h; |
| 1564 | u32 chipid_l; |
| 1565 | u32 chip_rev; |
| 1566 | u32 ptd_atl_int; |
| 1567 | u32 ptd_iso; |
| 1568 | |
| 1569 | chipid_h = isp1760_hcd_read(hcd, HC_CHIP_ID_HIGH); |
| 1570 | chipid_l = isp1760_hcd_read(hcd, HC_CHIP_ID_LOW); |
| 1571 | chip_rev = isp1760_hcd_read(hcd, HC_CHIP_REV); |
| 1572 | printf("USB ISP %02x%02x HW rev. %d started\n", chipid_h, |
| 1573 | chipid_l, chip_rev); |
| 1574 | |
| 1575 | isp1760_hcd_clear(hcd, ISO_BUF_FILL); |
| 1576 | isp1760_hcd_clear(hcd, INT_BUF_FILL); |
| 1577 | isp1760_hcd_clear(hcd, ATL_BUF_FILL); |
| 1578 | |
| 1579 | isp1760_hcd_set(hcd, HC_ATL_PTD_SKIPMAP); |
| 1580 | isp1760_hcd_set(hcd, HC_INT_PTD_SKIPMAP); |
| 1581 | isp1760_hcd_set(hcd, HC_ISO_PTD_SKIPMAP); |
| 1582 | ndelay(100); |
| 1583 | isp1760_hcd_clear(hcd, HC_ATL_PTD_DONEMAP); |
| 1584 | isp1760_hcd_clear(hcd, HC_INT_PTD_DONEMAP); |
| 1585 | isp1760_hcd_clear(hcd, HC_ISO_PTD_DONEMAP); |
| 1586 | |
| 1587 | isp1760_hcd_set(hcd, HW_OTG_DISABLE); |
| 1588 | isp1760_reg_write(priv->regs, ISP1763_HC_OTG_CTRL_CLEAR, BIT(7)); |
| 1589 | isp1760_reg_write(priv->regs, ISP1763_HC_OTG_CTRL_CLEAR, BIT(15)); |
| 1590 | mdelay(10); |
| 1591 | |
| 1592 | isp1760_hcd_set(hcd, HC_INT_IRQ_ENABLE); |
| 1593 | isp1760_hcd_set(hcd, HC_ATL_IRQ_ENABLE); |
| 1594 | |
| 1595 | isp1760_hcd_set(hcd, HW_GLOBAL_INTR_EN); |
| 1596 | |
| 1597 | isp1760_hcd_clear(hcd, HC_ATL_IRQ_MASK_AND); |
| 1598 | isp1760_hcd_clear(hcd, HC_INT_IRQ_MASK_AND); |
| 1599 | isp1760_hcd_clear(hcd, HC_ISO_IRQ_MASK_AND); |
| 1600 | |
| 1601 | isp1760_hcd_set(hcd, HC_ATL_IRQ_MASK_OR); |
| 1602 | isp1760_hcd_set(hcd, HC_INT_IRQ_MASK_OR); |
| 1603 | isp1760_hcd_set(hcd, HC_ISO_IRQ_MASK_OR); |
| 1604 | |
| 1605 | ptd_atl_int = 0x8000; |
| 1606 | ptd_iso = 0x0001; |
| 1607 | |
| 1608 | isp1760_hcd_write(hcd, HC_ATL_PTD_LASTPTD, ptd_atl_int); |
| 1609 | isp1760_hcd_write(hcd, HC_INT_PTD_LASTPTD, ptd_atl_int); |
| 1610 | isp1760_hcd_write(hcd, HC_ISO_PTD_LASTPTD, ptd_iso); |
| 1611 | |
| 1612 | isp1760_hcd_set(hcd, ATL_BUF_FILL); |
| 1613 | isp1760_hcd_set(hcd, INT_BUF_FILL); |
| 1614 | |
| 1615 | isp1760_hcd_clear(hcd, CMD_LRESET); |
| 1616 | isp1760_hcd_clear(hcd, CMD_RESET); |
| 1617 | |
| 1618 | retval = isp1760_hcd_set_and_wait(hcd, CMD_RUN, 250 * 1000); |
| 1619 | if (retval) |
| 1620 | return retval; |
| 1621 | |
| 1622 | down_write(&ehci_cf_port_reset_rwsem); |
| 1623 | retval = isp1760_hcd_set_and_wait(hcd, FLAG_CF, 250 * 1000); |
| 1624 | up_write(&ehci_cf_port_reset_rwsem); |
| 1625 | if (retval) |
| 1626 | return retval; |
| 1627 | |
| 1628 | return 0; |
| 1629 | } |
| 1630 | |
| 1631 | static int isp1760_run(struct usb_hcd *hcd) |
| 1632 | { |
| 1633 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
| 1634 | int retval; |
| 1635 | u32 chipid_h; |
| 1636 | u32 chipid_l; |
| 1637 | u32 chip_rev; |
| 1638 | u32 ptd_atl_int; |
| 1639 | u32 ptd_iso; |
| 1640 | |
| 1641 | /* |
| 1642 | * ISP1763 have some differences in the setup and order to enable |
| 1643 | * the ports, disable otg, setup buffers, and ATL, INT, ISO status. |
| 1644 | * So, just handle it a separate sequence. |
| 1645 | */ |
| 1646 | if (priv->is_isp1763) |
| 1647 | return isp1763_run(hcd); |
| 1648 | |
| 1649 | /* Set PTD interrupt AND & OR maps */ |
| 1650 | isp1760_hcd_clear(hcd, HC_ATL_IRQ_MASK_AND); |
| 1651 | isp1760_hcd_clear(hcd, HC_INT_IRQ_MASK_AND); |
| 1652 | isp1760_hcd_clear(hcd, HC_ISO_IRQ_MASK_AND); |
| 1653 | |
| 1654 | isp1760_hcd_set(hcd, HC_ATL_IRQ_MASK_OR); |
| 1655 | isp1760_hcd_set(hcd, HC_INT_IRQ_MASK_OR); |
| 1656 | isp1760_hcd_set(hcd, HC_ISO_IRQ_MASK_OR); |
| 1657 | |
| 1658 | /* step 23 passed */ |
| 1659 | |
| 1660 | isp1760_hcd_set(hcd, HW_GLOBAL_INTR_EN); |
| 1661 | |
| 1662 | isp1760_hcd_clear(hcd, CMD_LRESET); |
| 1663 | isp1760_hcd_clear(hcd, CMD_RESET); |
| 1664 | |
| 1665 | retval = isp1760_hcd_set_and_wait(hcd, CMD_RUN, 250 * 1000); |
| 1666 | if (retval) |
| 1667 | return retval; |
| 1668 | |
| 1669 | /* |
| 1670 | * XXX |
| 1671 | * Spec says to write FLAG_CF as last config action, priv code grabs |
| 1672 | * the semaphore while doing so. |
| 1673 | */ |
| 1674 | down_write(&ehci_cf_port_reset_rwsem); |
| 1675 | |
| 1676 | retval = isp1760_hcd_set_and_wait(hcd, FLAG_CF, 250 * 1000); |
| 1677 | up_write(&ehci_cf_port_reset_rwsem); |
| 1678 | if (retval) |
| 1679 | return retval; |
| 1680 | |
| 1681 | chipid_h = isp1760_hcd_read(hcd, HC_CHIP_ID_HIGH); |
| 1682 | chipid_l = isp1760_hcd_read(hcd, HC_CHIP_ID_LOW); |
| 1683 | chip_rev = isp1760_hcd_read(hcd, HC_CHIP_REV); |
| 1684 | dev_info(priv->dev, "USB ISP %02x%02x HW rev. %d started\n", |
| 1685 | chipid_h, chipid_l, chip_rev); |
| 1686 | |
| 1687 | /* PTD Register Init Part 2, Step 28 */ |
| 1688 | |
| 1689 | /* Setup registers controlling PTD checking */ |
| 1690 | ptd_atl_int = 0x80000000; |
| 1691 | ptd_iso = 0x00000001; |
| 1692 | |
| 1693 | isp1760_hcd_write(hcd, HC_ATL_PTD_LASTPTD, ptd_atl_int); |
| 1694 | isp1760_hcd_write(hcd, HC_INT_PTD_LASTPTD, ptd_atl_int); |
| 1695 | isp1760_hcd_write(hcd, HC_ISO_PTD_LASTPTD, ptd_iso); |
| 1696 | |
| 1697 | isp1760_hcd_set(hcd, HC_ATL_PTD_SKIPMAP); |
| 1698 | isp1760_hcd_set(hcd, HC_INT_PTD_SKIPMAP); |
| 1699 | isp1760_hcd_set(hcd, HC_ISO_PTD_SKIPMAP); |
| 1700 | |
| 1701 | isp1760_hcd_set(hcd, ATL_BUF_FILL); |
| 1702 | isp1760_hcd_set(hcd, INT_BUF_FILL); |
| 1703 | |
| 1704 | /* GRR this is run-once init(), being done every time the HC starts. |
| 1705 | * So long as they're part of class devices, we can't do it init() |
| 1706 | * since the class device isn't created that early. |
| 1707 | */ |
| 1708 | return 0; |
| 1709 | } |
| 1710 | |
| 1711 | static int qtd_fill(struct isp1760_qtd *qtd, void *databuffer, size_t len) |
| 1712 | { |
| 1713 | qtd->data_buffer = databuffer; |
| 1714 | |
| 1715 | qtd->length = len; |
| 1716 | |
| 1717 | return qtd->length; |
| 1718 | } |
| 1719 | |
| 1720 | static void qtd_list_free(struct list_head *qtd_list) |
| 1721 | { |
| 1722 | struct isp1760_qtd *qtd, *qtd_next; |
| 1723 | |
| 1724 | list_for_each_entry_safe(qtd, qtd_next, qtd_list, qtd_list) { |
| 1725 | list_del(&qtd->qtd_list); |
| 1726 | qtd_free(qtd); |
| 1727 | } |
| 1728 | } |
| 1729 | |
| 1730 | /* |
| 1731 | * Packetize urb->transfer_buffer into list of packets of size wMaxPacketSize. |
| 1732 | * Also calculate the PID type (SETUP/IN/OUT) for each packet. |
| 1733 | */ |
| 1734 | #define max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff) |
| 1735 | static void packetize_urb(struct usb_hcd *hcd, struct urb *urb, |
| 1736 | struct list_head *head, gfp_t flags) |
| 1737 | { |
| 1738 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
| 1739 | const struct isp1760_memory_layout *mem = priv->memory_layout; |
| 1740 | struct isp1760_qtd *qtd; |
| 1741 | void *buf; |
| 1742 | int len, maxpacketsize; |
| 1743 | u8 packet_type; |
| 1744 | |
| 1745 | /* |
| 1746 | * URBs map to sequences of QTDs: one logical transaction |
| 1747 | */ |
| 1748 | |
| 1749 | if (!urb->transfer_buffer && urb->transfer_buffer_length) { |
| 1750 | /* XXX This looks like usb storage / SCSI bug */ |
| 1751 | dev_err(priv->dev, "buf is null, dma is %08lx len is %d\n", |
| 1752 | (unsigned long)urb->transfer_dma, |
| 1753 | urb->transfer_buffer_length); |
| 1754 | WARN_ON(1); |
| 1755 | } |
| 1756 | |
| 1757 | if (usb_pipein(urb->pipe)) |
| 1758 | packet_type = IN_PID; |
| 1759 | else |
| 1760 | packet_type = OUT_PID; |
| 1761 | |
| 1762 | if (usb_pipecontrol(urb->pipe)) { |
| 1763 | qtd = qtd_alloc(flags, urb, SETUP_PID); |
| 1764 | if (!qtd) |
| 1765 | goto cleanup; |
| 1766 | qtd_fill(qtd, urb->setup_packet, sizeof(struct usb_ctrlrequest)); |
| 1767 | list_add_tail(&qtd->qtd_list, head); |
| 1768 | |
| 1769 | /* for zero length DATA stages, STATUS is always IN */ |
| 1770 | if (urb->transfer_buffer_length == 0) |
| 1771 | packet_type = IN_PID; |
| 1772 | } |
| 1773 | |
| 1774 | maxpacketsize = max_packet(usb_maxpacket(urb->dev, urb->pipe)); |
| 1775 | |
| 1776 | /* |
| 1777 | * buffer gets wrapped in one or more qtds; |
| 1778 | * last one may be "short" (including zero len) |
| 1779 | * and may serve as a control status ack |
| 1780 | */ |
| 1781 | buf = urb->transfer_buffer; |
| 1782 | len = urb->transfer_buffer_length; |
| 1783 | |
| 1784 | for (;;) { |
| 1785 | int this_qtd_len; |
| 1786 | |
| 1787 | qtd = qtd_alloc(flags, urb, packet_type); |
| 1788 | if (!qtd) |
| 1789 | goto cleanup; |
| 1790 | |
| 1791 | if (len > mem->blocks_size[ISP176x_BLOCK_NUM - 1]) |
| 1792 | this_qtd_len = mem->blocks_size[ISP176x_BLOCK_NUM - 1]; |
| 1793 | else |
| 1794 | this_qtd_len = len; |
| 1795 | |
| 1796 | this_qtd_len = qtd_fill(qtd, buf, this_qtd_len); |
| 1797 | list_add_tail(&qtd->qtd_list, head); |
| 1798 | |
| 1799 | len -= this_qtd_len; |
| 1800 | buf += this_qtd_len; |
| 1801 | |
| 1802 | if (len <= 0) |
| 1803 | break; |
| 1804 | } |
| 1805 | |
| 1806 | /* |
| 1807 | * control requests may need a terminating data "status" ack; |
| 1808 | * bulk ones may need a terminating short packet (zero length). |
| 1809 | */ |
| 1810 | if (urb->transfer_buffer_length != 0) { |
| 1811 | int one_more = 0; |
| 1812 | |
| 1813 | if (usb_pipecontrol(urb->pipe)) { |
| 1814 | one_more = 1; |
| 1815 | if (packet_type == IN_PID) |
| 1816 | packet_type = OUT_PID; |
| 1817 | else |
| 1818 | packet_type = IN_PID; |
| 1819 | } else if (usb_pipebulk(urb->pipe) && maxpacketsize && |
| 1820 | (urb->transfer_flags & URB_ZERO_PACKET) && |
| 1821 | !(urb->transfer_buffer_length % maxpacketsize)) { |
| 1822 | one_more = 1; |
| 1823 | } |
| 1824 | if (one_more) { |
| 1825 | qtd = qtd_alloc(flags, urb, packet_type); |
| 1826 | if (!qtd) |
| 1827 | goto cleanup; |
| 1828 | |
| 1829 | /* never any data in such packets */ |
| 1830 | qtd_fill(qtd, NULL, 0); |
| 1831 | list_add_tail(&qtd->qtd_list, head); |
| 1832 | } |
| 1833 | } |
| 1834 | |
| 1835 | return; |
| 1836 | |
| 1837 | cleanup: |
| 1838 | qtd_list_free(head); |
| 1839 | } |
| 1840 | |
| 1841 | static int isp1760_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, |
| 1842 | gfp_t mem_flags) |
| 1843 | { |
| 1844 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
| 1845 | struct isp1760_qh *qh = NULL; |
| 1846 | struct list_head *ep_queue; |
| 1847 | LIST_HEAD(new_qtds); |
| 1848 | int qh_in_queue; |
| 1849 | int retval; |
| 1850 | int epnum; |
| 1851 | |
| 1852 | switch (usb_pipetype(urb->pipe)) { |
| 1853 | case PIPE_CONTROL: |
| 1854 | ep_queue = &priv->qh_list[QH_CONTROL]; |
| 1855 | break; |
| 1856 | case PIPE_BULK: |
| 1857 | ep_queue = &priv->qh_list[QH_BULK]; |
| 1858 | break; |
| 1859 | case PIPE_INTERRUPT: |
| 1860 | ep_queue = &priv->qh_list[QH_INTERRUPT]; |
| 1861 | break; |
| 1862 | case PIPE_ISOCHRONOUS: |
| 1863 | printf("isochronous USB packets not yet supported\n"); |
| 1864 | return -EPIPE; |
| 1865 | default: |
| 1866 | printf("unknown pipe type\n"); |
| 1867 | return -EPIPE; |
| 1868 | } |
| 1869 | |
| 1870 | if (usb_pipein(urb->pipe)) |
| 1871 | urb->actual_length = 0; |
| 1872 | |
| 1873 | packetize_urb(hcd, urb, &new_qtds, mem_flags); |
| 1874 | if (list_empty(&new_qtds)) |
| 1875 | return -ENOMEM; |
| 1876 | |
| 1877 | retval = usb_hcd_link_urb_to_ep(hcd, urb); |
| 1878 | if (retval) { |
| 1879 | qtd_list_free(&new_qtds); |
| 1880 | goto out; |
| 1881 | } |
| 1882 | |
| 1883 | epnum = usb_pipeendpoint(urb->pipe); |
| 1884 | |
| 1885 | qh_in_queue = 0; |
| 1886 | list_for_each_entry(qh, ep_queue, qh_list) { |
| 1887 | if (qh->epnum == epnum) { |
| 1888 | qh_in_queue = 1; |
| 1889 | break; |
| 1890 | } |
| 1891 | } |
| 1892 | |
| 1893 | if (!qh_in_queue) { |
| 1894 | qh = qh_alloc(GFP_ATOMIC); |
| 1895 | if (!qh) { |
| 1896 | retval = -ENOMEM; |
| 1897 | usb_hcd_unlink_urb_from_ep(hcd, urb); |
| 1898 | qtd_list_free(&new_qtds); |
| 1899 | goto out; |
| 1900 | } |
| 1901 | |
| 1902 | qh->epnum = epnum; |
| 1903 | list_add_tail(&qh->qh_list, ep_queue); |
| 1904 | urb->ep->hcpriv = qh; |
| 1905 | } |
| 1906 | |
| 1907 | list_splice_tail(&new_qtds, &qh->qtd_list); |
| 1908 | schedule_ptds(hcd); |
| 1909 | |
| 1910 | out: |
| 1911 | return retval; |
| 1912 | } |
| 1913 | |
| 1914 | static void kill_transfer(struct usb_hcd *hcd, struct urb *urb, |
| 1915 | struct isp1760_qh *qh) |
| 1916 | { |
| 1917 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
| 1918 | int skip_map; |
| 1919 | |
| 1920 | WARN_ON(qh->slot == -1); |
| 1921 | |
| 1922 | /* |
| 1923 | * We need to forcefully reclaim the slot since some transfers never |
| 1924 | * return, e.g. interrupt transfers and NAKed bulk transfers. |
| 1925 | */ |
| 1926 | if (usb_pipecontrol(urb->pipe) || usb_pipebulk(urb->pipe)) { |
| 1927 | if (qh->slot != -1) { |
| 1928 | skip_map = isp1760_hcd_read(hcd, HC_ATL_PTD_SKIPMAP); |
| 1929 | skip_map |= (1 << qh->slot); |
| 1930 | isp1760_hcd_write(hcd, HC_ATL_PTD_SKIPMAP, skip_map); |
| 1931 | ndelay(100); |
| 1932 | } |
| 1933 | priv->atl_slots[qh->slot].qh = NULL; |
| 1934 | priv->atl_slots[qh->slot].qtd = NULL; |
| 1935 | } else { |
| 1936 | if (qh->slot != -1) { |
| 1937 | skip_map = isp1760_hcd_read(hcd, HC_INT_PTD_SKIPMAP); |
| 1938 | skip_map |= (1 << qh->slot); |
| 1939 | isp1760_hcd_write(hcd, HC_INT_PTD_SKIPMAP, skip_map); |
| 1940 | } |
| 1941 | priv->int_slots[qh->slot].qh = NULL; |
| 1942 | priv->int_slots[qh->slot].qtd = NULL; |
| 1943 | } |
| 1944 | |
| 1945 | qh->slot = -1; |
| 1946 | } |
| 1947 | |
| 1948 | /* |
| 1949 | * Retire the qtds beginning at 'qtd' and belonging all to the same urb, killing |
| 1950 | * any active transfer belonging to the urb in the process. |
| 1951 | */ |
| 1952 | static void dequeue_urb_from_qtd(struct usb_hcd *hcd, struct isp1760_qh *qh, |
| 1953 | struct isp1760_qtd *qtd) |
| 1954 | { |
| 1955 | struct urb *urb; |
| 1956 | int urb_was_running; |
| 1957 | |
| 1958 | urb = qtd->urb; |
| 1959 | urb_was_running = 0; |
| 1960 | list_for_each_entry_from(qtd, &qh->qtd_list, qtd_list) { |
| 1961 | if (qtd->urb != urb) |
| 1962 | break; |
| 1963 | |
| 1964 | if (qtd->status >= QTD_XFER_STARTED) |
| 1965 | urb_was_running = 1; |
| 1966 | if (last_qtd_of_urb(qtd, qh) && |
| 1967 | qtd->status >= QTD_XFER_COMPLETE) |
| 1968 | urb_was_running = 0; |
| 1969 | |
| 1970 | if (qtd->status == QTD_XFER_STARTED) |
| 1971 | kill_transfer(hcd, urb, qh); |
| 1972 | qtd->status = QTD_RETIRE; |
| 1973 | } |
| 1974 | } |
| 1975 | |
| 1976 | int isp1760_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) |
| 1977 | { |
| 1978 | struct isp1760_qtd *qtd; |
| 1979 | struct isp1760_qh *qh; |
| 1980 | int retval = 0; |
| 1981 | |
| 1982 | retval = usb_hcd_check_unlink_urb(hcd, urb, status); |
| 1983 | if (retval) |
| 1984 | goto out; |
| 1985 | |
| 1986 | qh = urb->ep->hcpriv; |
| 1987 | if (!qh) { |
| 1988 | retval = -EINVAL; |
| 1989 | goto out; |
| 1990 | } |
| 1991 | |
| 1992 | list_for_each_entry(qtd, &qh->qtd_list, qtd_list) |
| 1993 | if (qtd->urb == urb) { |
| 1994 | dequeue_urb_from_qtd(hcd, qh, qtd); |
| 1995 | list_move(&qtd->qtd_list, &qh->qtd_list); |
| 1996 | break; |
| 1997 | } |
| 1998 | |
| 1999 | urb->status = status; |
| 2000 | schedule_ptds(hcd); |
| 2001 | |
| 2002 | out: |
| 2003 | return retval; |
| 2004 | } |
| 2005 | |
| 2006 | static void isp1760_hub_descriptor(struct isp1760_hcd *priv, |
| 2007 | struct usb_hub_descriptor *desc) |
| 2008 | { |
| 2009 | int ports; |
| 2010 | u16 temp; |
| 2011 | |
| 2012 | ports = isp1760_hcd_n_ports(priv->hcd); |
| 2013 | |
| 2014 | desc->bDescriptorType = USB_DT_HUB; |
| 2015 | /* priv 1.0, 2.3.9 says 20ms max */ |
| 2016 | desc->bPwrOn2PwrGood = 10; |
| 2017 | desc->bHubContrCurrent = 0; |
| 2018 | |
| 2019 | desc->bNbrPorts = ports; |
| 2020 | temp = 1 + (ports / 8); |
| 2021 | desc->bLength = 7 + 2 * temp; |
| 2022 | |
| 2023 | /* ports removable, and usb 1.0 legacy PortPwrCtrlMask */ |
| 2024 | memset(&desc->u.hs.DeviceRemovable[0], 0, temp); |
| 2025 | memset(&desc->u.hs.DeviceRemovable[temp], 0xff, temp); |
| 2026 | |
| 2027 | /* per-port overcurrent reporting */ |
| 2028 | temp = HUB_CHAR_INDV_PORT_OCPM; |
| 2029 | if (isp1760_hcd_ppc_is_set(priv->hcd)) |
| 2030 | /* per-port power control */ |
| 2031 | temp |= HUB_CHAR_INDV_PORT_LPSM; |
| 2032 | else |
| 2033 | /* no power switching */ |
| 2034 | temp |= HUB_CHAR_NO_LPSM; |
| 2035 | desc->wHubCharacteristics = cpu_to_le16(temp); |
| 2036 | } |
| 2037 | |
| 2038 | #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E) |
| 2039 | |
| 2040 | static void check_reset_complete(struct usb_hcd *hcd, int index) |
| 2041 | { |
| 2042 | if (!(isp1760_hcd_is_set(hcd, PORT_CONNECT))) |
| 2043 | return; |
| 2044 | |
| 2045 | /* if reset finished and it's still not enabled -- handoff */ |
| 2046 | if (!isp1760_hcd_is_set(hcd, PORT_PE)) { |
| 2047 | printf("port %d full speed --> companion\n", index + 1); |
| 2048 | |
| 2049 | isp1760_hcd_set(hcd, PORT_OWNER); |
| 2050 | |
| 2051 | isp1760_hcd_clear(hcd, PORT_CSC); |
| 2052 | } else { |
| 2053 | printf("port %d high speed\n", index + 1); |
| 2054 | } |
| 2055 | } |
| 2056 | |
| 2057 | static int isp1760_hub_control(struct usb_hcd *hcd, struct usb_device *dev, |
| 2058 | unsigned long pipe, void *buffer, int length, |
| 2059 | struct devrequest *setup) |
| 2060 | { |
| 2061 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
| 2062 | u16 typeReq, wValue, wIndex; |
| 2063 | char *buf = buffer; |
| 2064 | void *src = NULL; |
| 2065 | int src_len = 0; |
| 2066 | int retval = 0; |
| 2067 | u32 status; |
| 2068 | int ports; |
| 2069 | |
| 2070 | if (!setup) |
| 2071 | return -EINVAL; |
| 2072 | |
| 2073 | ports = isp1760_hcd_n_ports(hcd); |
| 2074 | |
| 2075 | typeReq = setup->request | (setup->requesttype << 8); |
| 2076 | wValue = le16_to_cpu(setup->value); |
| 2077 | wIndex = le16_to_cpu(setup->index); |
| 2078 | |
| 2079 | /* |
| 2080 | * FIXME: support SetPortFeatures USB_PORT_FEAT_INDICATOR. |
| 2081 | * HCS_INDICATOR may say we can change LEDs to off/amber/green. |
| 2082 | * (track current state ourselves) ... blink for diagnostics, |
| 2083 | * power, "this is the one", etc. EHCI spec supports this. |
| 2084 | */ |
| 2085 | |
| 2086 | switch (typeReq) { |
| 2087 | case DeviceOutRequest | USB_REQ_SET_ADDRESS: |
| 2088 | break; |
| 2089 | case DeviceOutRequest | USB_REQ_SET_CONFIGURATION: |
| 2090 | /* Nothing to do */ |
| 2091 | break; |
| 2092 | case DeviceRequest | USB_REQ_GET_DESCRIPTOR: |
| 2093 | switch (wValue & 0xff00) { |
| 2094 | case USB_DT_DEVICE << 8: |
| 2095 | src = &rh_descriptor.device; |
| 2096 | src_len = 0x12; |
| 2097 | break; |
| 2098 | case USB_DT_CONFIG << 8: |
| 2099 | src = &rh_descriptor.config; |
| 2100 | src_len = 0x09; |
| 2101 | break; |
| 2102 | case USB_DT_STRING << 8: |
| 2103 | switch (wValue & 0xff) { |
| 2104 | case 0: /* Language */ |
| 2105 | src = ISP1760_LANGUAGE_DESC; |
| 2106 | src_len = 4; |
| 2107 | break; |
| 2108 | case 1: /* Vendor String */ |
| 2109 | src = ISP1760_VENDOR_DESC; |
| 2110 | src_len = 14; |
| 2111 | break; |
| 2112 | case 2: /* Product Name */ |
| 2113 | src = ISP1760_PRODUCT_NAME_DESC; |
| 2114 | src_len = 42; |
| 2115 | break; |
| 2116 | default: |
| 2117 | goto error; |
| 2118 | } |
| 2119 | break; |
| 2120 | } |
| 2121 | break; |
| 2122 | case ClearHubFeature: |
| 2123 | switch (wValue) { |
| 2124 | case C_HUB_LOCAL_POWER: |
| 2125 | case C_HUB_OVER_CURRENT: |
| 2126 | /* no hub-wide feature/status flags */ |
| 2127 | break; |
| 2128 | default: |
| 2129 | goto error; |
| 2130 | } |
| 2131 | break; |
| 2132 | case ClearPortFeature: |
| 2133 | if (!wIndex || wIndex > ports) |
| 2134 | goto error; |
| 2135 | wIndex--; |
| 2136 | |
| 2137 | /* |
| 2138 | * Even if OWNER is set, so the port is owned by the |
| 2139 | * companion controller, hub_wq needs to be able to clear |
| 2140 | * the port-change status bits (especially |
| 2141 | * USB_PORT_STAT_C_CONNECTION). |
| 2142 | */ |
| 2143 | |
| 2144 | switch (wValue) { |
| 2145 | case USB_PORT_FEAT_ENABLE: |
| 2146 | isp1760_hcd_clear(hcd, PORT_PE); |
| 2147 | break; |
| 2148 | case USB_PORT_FEAT_C_ENABLE: |
| 2149 | /* XXX error? */ |
| 2150 | break; |
| 2151 | case USB_PORT_FEAT_SUSPEND: |
| 2152 | if (isp1760_hcd_is_set(hcd, PORT_RESET)) |
| 2153 | goto error; |
| 2154 | |
| 2155 | if (isp1760_hcd_is_set(hcd, PORT_SUSPEND)) { |
| 2156 | if (!isp1760_hcd_is_set(hcd, PORT_PE)) |
| 2157 | goto error; |
| 2158 | /* resume signaling for 20 msec */ |
| 2159 | isp1760_hcd_clear(hcd, PORT_CSC); |
| 2160 | isp1760_hcd_set(hcd, PORT_RESUME); |
| 2161 | |
| 2162 | priv->reset_done = get_timer(0) + 40; |
| 2163 | } |
| 2164 | break; |
| 2165 | case USB_PORT_FEAT_C_SUSPEND: |
| 2166 | /* we auto-clear this feature */ |
| 2167 | break; |
| 2168 | case USB_PORT_FEAT_POWER: |
| 2169 | if (isp1760_hcd_ppc_is_set(hcd)) |
| 2170 | isp1760_hcd_clear(hcd, PORT_POWER); |
| 2171 | break; |
| 2172 | case USB_PORT_FEAT_C_CONNECTION: |
| 2173 | isp1760_hcd_set(hcd, PORT_CSC); |
| 2174 | break; |
| 2175 | case USB_PORT_FEAT_C_OVER_CURRENT: |
| 2176 | /* XXX error ?*/ |
| 2177 | break; |
| 2178 | case USB_PORT_FEAT_C_RESET: |
| 2179 | /* GetPortStatus clears reset */ |
| 2180 | break; |
| 2181 | default: |
| 2182 | goto error; |
| 2183 | } |
| 2184 | isp1760_hcd_read(hcd, CMD_RUN); |
| 2185 | break; |
| 2186 | case GetHubDescriptor: |
| 2187 | isp1760_hub_descriptor(priv, (struct usb_hub_descriptor *)buf); |
| 2188 | break; |
| 2189 | case GetHubStatus: |
| 2190 | /* no hub-wide feature/status flags */ |
| 2191 | memset(buf, 0, 4); |
| 2192 | break; |
| 2193 | case GetPortStatus: |
| 2194 | if (!wIndex || wIndex > ports) |
| 2195 | goto error; |
| 2196 | wIndex--; |
| 2197 | status = 0; |
| 2198 | |
| 2199 | /* wPortChange bits */ |
| 2200 | if (isp1760_hcd_is_set(hcd, PORT_CSC)) |
| 2201 | status |= USB_PORT_STAT_C_CONNECTION << 16; |
| 2202 | |
| 2203 | /* whoever resumes must GetPortStatus to complete it!! */ |
| 2204 | if (isp1760_hcd_is_set(hcd, PORT_RESUME)) { |
| 2205 | status |= USB_PORT_STAT_C_SUSPEND << 16; |
| 2206 | |
| 2207 | if (!priv->reset_done) { |
| 2208 | priv->reset_done = get_timer(0) + 20; |
| 2209 | } else if (get_timer(0) > priv->reset_done) { |
| 2210 | /* stop resume signaling */ |
| 2211 | isp1760_hcd_clear(hcd, PORT_CSC); |
| 2212 | |
| 2213 | retval = isp1760_hcd_clear_and_wait(hcd, |
| 2214 | PORT_RESUME, |
| 2215 | 2000); |
| 2216 | if (retval != 0) { |
| 2217 | printf("port %d resume error %d\n", |
| 2218 | wIndex + 1, retval); |
| 2219 | goto error; |
| 2220 | } |
| 2221 | } |
| 2222 | } |
| 2223 | |
| 2224 | /* whoever resets must GetPortStatus to complete it!! */ |
| 2225 | if (isp1760_hcd_is_set(hcd, PORT_RESET) && |
| 2226 | get_timer(0) > priv->reset_done) { |
| 2227 | status |= USB_PORT_STAT_C_RESET << 16; |
| 2228 | priv->reset_done = 0; |
| 2229 | |
| 2230 | /* force reset to complete */ |
| 2231 | /* REVISIT: some hardware needs 550+ usec to clear |
| 2232 | * this bit; seems too long to spin routinely... |
| 2233 | */ |
| 2234 | retval = isp1760_hcd_clear_and_wait(hcd, PORT_RESET, |
| 2235 | 750); |
| 2236 | if (retval != 0) { |
| 2237 | printf("port %d reset error %d\n", wIndex + 1, |
| 2238 | retval); |
| 2239 | goto error; |
| 2240 | } |
| 2241 | |
| 2242 | /* see what we found out */ |
| 2243 | check_reset_complete(hcd, wIndex); |
| 2244 | } |
| 2245 | /* |
| 2246 | * Even if OWNER is set, there's no harm letting hub_wq |
| 2247 | * see the wPortStatus values (they should all be 0 except |
| 2248 | * for PORT_POWER anyway). |
| 2249 | */ |
| 2250 | |
| 2251 | if (isp1760_hcd_is_set(hcd, PORT_OWNER)) |
| 2252 | printf("PORT_OWNER is set\n"); |
| 2253 | |
| 2254 | if (isp1760_hcd_is_set(hcd, PORT_CONNECT)) { |
| 2255 | status |= USB_PORT_STAT_CONNECTION; |
| 2256 | |
| 2257 | /* status may be from integrated TT */ |
| 2258 | status |= USB_PORT_STAT_HIGH_SPEED; |
| 2259 | } |
| 2260 | if (isp1760_hcd_is_set(hcd, PORT_PE)) |
| 2261 | status |= USB_PORT_STAT_ENABLE; |
| 2262 | if (isp1760_hcd_is_set(hcd, PORT_SUSPEND) && |
| 2263 | isp1760_hcd_is_set(hcd, PORT_RESUME)) |
| 2264 | status |= USB_PORT_STAT_SUSPEND; |
| 2265 | if (isp1760_hcd_is_set(hcd, PORT_RESET)) |
| 2266 | status |= USB_PORT_STAT_RESET; |
| 2267 | if (isp1760_hcd_is_set(hcd, PORT_POWER)) |
| 2268 | status |= USB_PORT_STAT_POWER; |
| 2269 | |
| 2270 | put_unaligned(cpu_to_le32(status), (__le32 *)buf); |
| 2271 | break; |
| 2272 | case SetHubFeature: |
| 2273 | switch (wValue) { |
| 2274 | case C_HUB_LOCAL_POWER: |
| 2275 | case C_HUB_OVER_CURRENT: |
| 2276 | /* no hub-wide feature/status flags */ |
| 2277 | break; |
| 2278 | default: |
| 2279 | goto error; |
| 2280 | } |
| 2281 | break; |
| 2282 | case SetPortFeature: |
| 2283 | wIndex &= 0xff; |
| 2284 | if (!wIndex || wIndex > ports) |
| 2285 | goto error; |
| 2286 | wIndex--; |
| 2287 | |
| 2288 | if (isp1760_hcd_is_set(hcd, PORT_OWNER)) |
| 2289 | break; |
| 2290 | |
| 2291 | switch (wValue) { |
| 2292 | case USB_PORT_FEAT_ENABLE: |
| 2293 | isp1760_hcd_set(hcd, PORT_PE); |
| 2294 | break; |
| 2295 | |
| 2296 | case USB_PORT_FEAT_SUSPEND: |
| 2297 | if (!isp1760_hcd_is_set(hcd, PORT_PE) || |
| 2298 | isp1760_hcd_is_set(hcd, PORT_RESET)) |
| 2299 | goto error; |
| 2300 | |
| 2301 | isp1760_hcd_set(hcd, PORT_SUSPEND); |
| 2302 | break; |
| 2303 | case USB_PORT_FEAT_POWER: |
| 2304 | if (isp1760_hcd_ppc_is_set(hcd)) |
| 2305 | isp1760_hcd_set(hcd, PORT_POWER); |
| 2306 | break; |
| 2307 | case USB_PORT_FEAT_RESET: |
| 2308 | if (isp1760_hcd_is_set(hcd, PORT_RESUME)) |
| 2309 | goto error; |
| 2310 | /* line status bits may report this as low speed, |
| 2311 | * which can be fine if this root hub has a |
| 2312 | * transaction translator built in. |
| 2313 | */ |
| 2314 | if ((isp1760_hcd_is_set(hcd, PORT_CONNECT) && |
| 2315 | !isp1760_hcd_is_set(hcd, PORT_PE)) && |
| 2316 | (isp1760_hcd_read(hcd, PORT_LSTATUS) == 1)) { |
| 2317 | isp1760_hcd_set(hcd, PORT_OWNER); |
| 2318 | } else { |
| 2319 | isp1760_hcd_set(hcd, PORT_RESET); |
| 2320 | isp1760_hcd_clear(hcd, PORT_PE); |
| 2321 | |
| 2322 | priv->reset_done = get_timer(0) + 50; |
| 2323 | } |
| 2324 | break; |
| 2325 | default: |
| 2326 | goto error; |
| 2327 | } |
| 2328 | break; |
| 2329 | |
| 2330 | default: |
| 2331 | printf("root: unknown request: 0x%0x\n", typeReq); |
| 2332 | goto error; |
| 2333 | } |
| 2334 | |
| 2335 | if (src_len) { |
| 2336 | length = min(src_len, length); |
| 2337 | |
| 2338 | if (src && length > 0) |
| 2339 | memcpy(buffer, src, length); |
| 2340 | else |
| 2341 | printf("zero copy USB descriptor\n"); |
| 2342 | } |
| 2343 | |
| 2344 | dev->act_len = length; |
| 2345 | dev->status = 0; |
| 2346 | |
| 2347 | return 0; |
| 2348 | |
| 2349 | error: |
| 2350 | /* "stall" on error */ |
| 2351 | dev->act_len = 0; |
| 2352 | dev->status = USB_ST_STALLED; |
| 2353 | return -EPIPE; |
| 2354 | } |
| 2355 | |
| 2356 | int __init isp1760_init_kmem_once(void) |
| 2357 | { |
| 2358 | urb_listitem_cachep = kmem_cache_create("isp1760_urb_listitem", |
| 2359 | sizeof(struct urb_listitem), 0, |
| 2360 | SLAB_TEMPORARY | |
| 2361 | SLAB_MEM_SPREAD, NULL); |
| 2362 | |
| 2363 | if (!urb_listitem_cachep) |
| 2364 | return -ENOMEM; |
| 2365 | |
| 2366 | qtd_cachep = kmem_cache_create("isp1760_qtd", |
| 2367 | sizeof(struct isp1760_qtd), 0, |
| 2368 | SLAB_TEMPORARY | SLAB_MEM_SPREAD, NULL); |
| 2369 | |
| 2370 | if (!qtd_cachep) |
| 2371 | goto destroy_urb_listitem; |
| 2372 | |
| 2373 | qh_cachep = kmem_cache_create("isp1760_qh", sizeof(struct isp1760_qh), |
| 2374 | 0, SLAB_TEMPORARY | SLAB_MEM_SPREAD, |
| 2375 | NULL); |
| 2376 | |
| 2377 | if (!qh_cachep) |
| 2378 | goto destroy_qtd; |
| 2379 | |
| 2380 | return 0; |
| 2381 | |
| 2382 | destroy_qtd: |
| 2383 | kmem_cache_destroy(qtd_cachep); |
| 2384 | |
| 2385 | destroy_urb_listitem: |
| 2386 | kmem_cache_destroy(urb_listitem_cachep); |
| 2387 | |
| 2388 | return -ENOMEM; |
| 2389 | } |
| 2390 | |
| 2391 | void isp1760_deinit_kmem_cache(void) |
| 2392 | { |
| 2393 | kmem_cache_destroy(qtd_cachep); |
| 2394 | kmem_cache_destroy(qh_cachep); |
| 2395 | kmem_cache_destroy(urb_listitem_cachep); |
| 2396 | } |
| 2397 | |
| 2398 | int isp1760_hcd_lowlevel_init(struct isp1760_hcd *priv) |
| 2399 | { |
| 2400 | int ret; |
| 2401 | |
| 2402 | ret = isp1760_hc_setup(priv->hcd); |
| 2403 | if (ret < 0) |
| 2404 | return ret; |
| 2405 | |
| 2406 | ret = isp1760_run(priv->hcd); |
| 2407 | if (ret < 0) |
| 2408 | return ret; |
| 2409 | |
| 2410 | return 0; |
| 2411 | } |
| 2412 | |
| 2413 | static const struct usb_urb_ops isp1760_urb_ops = { |
| 2414 | .urb_enqueue = isp1760_urb_enqueue, |
| 2415 | .urb_dequeue = isp1760_urb_dequeue, |
| 2416 | .hub_control = isp1760_hub_control, |
| 2417 | .isr = isp1760_irq, |
| 2418 | }; |
| 2419 | |
| 2420 | int isp1760_hcd_register(struct isp1760_hcd *priv, struct resource *mem, |
| 2421 | int irq, unsigned long irqflags, |
| 2422 | struct udevice *dev) |
| 2423 | { |
| 2424 | const struct isp1760_memory_layout *mem_layout = priv->memory_layout; |
| 2425 | struct isp1760_host_data *host = dev_get_priv(dev); |
| 2426 | struct usb_hcd *hcd = &host->hcd; |
| 2427 | int ret; |
| 2428 | |
| 2429 | priv->hcd = hcd; |
| 2430 | |
| 2431 | hcd->hcd_priv = priv; |
| 2432 | |
| 2433 | priv->hcd = hcd; |
| 2434 | |
| 2435 | hcd->urb_ops = &isp1760_urb_ops; |
| 2436 | |
| 2437 | priv->atl_slots = kcalloc(mem_layout->slot_num, |
| 2438 | sizeof(struct isp1760_slotinfo), GFP_KERNEL); |
| 2439 | if (!priv->atl_slots) |
| 2440 | return -ENOMEM; |
| 2441 | |
| 2442 | priv->int_slots = kcalloc(mem_layout->slot_num, |
| 2443 | sizeof(struct isp1760_slotinfo), GFP_KERNEL); |
| 2444 | if (!priv->int_slots) { |
| 2445 | ret = -ENOMEM; |
| 2446 | goto free_atl_slots; |
| 2447 | } |
| 2448 | |
| 2449 | host->host_speed = USB_SPEED_HIGH; |
| 2450 | |
| 2451 | init_memory(priv); |
| 2452 | |
| 2453 | return 0; |
| 2454 | |
| 2455 | free_atl_slots: |
| 2456 | kfree(priv->atl_slots); |
| 2457 | |
| 2458 | return ret; |
| 2459 | } |
| 2460 | |
| 2461 | void isp1760_hcd_unregister(struct isp1760_hcd *priv) |
| 2462 | { |
| 2463 | struct isp1760_qh *qh, *qh_next; |
| 2464 | int i; |
| 2465 | |
| 2466 | for (i = 0; i < QH_END; i++) |
| 2467 | list_for_each_entry_safe(qh, qh_next, &priv->qh_list[i], |
| 2468 | qh_list) { |
| 2469 | qtd_list_free(&qh->qtd_list); |
| 2470 | list_del(&qh->qh_list); |
| 2471 | qh_free(qh); |
| 2472 | } |
| 2473 | |
| 2474 | kfree(priv->atl_slots); |
| 2475 | kfree(priv->int_slots); |
| 2476 | } |