Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 2 | /* |
Wolfgang Denk | 331dfe8 | 2008-03-26 15:38:47 +0100 | [diff] [blame] | 3 | * (C) Copyright 2001-2008 |
Biwen Li | 247dac6 | 2020-05-01 20:03:56 +0800 | [diff] [blame] | 4 | * Copyright 2020 NXP |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 5 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 6 | * Keith Outwater, keith_outwater@mvis.com` |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 7 | */ |
| 8 | |
| 9 | /* |
| 10 | * Date & Time support (no alarms) for Dallas Semiconductor (now Maxim) |
| 11 | * DS1337 Real Time Clock (RTC). |
| 12 | */ |
| 13 | |
Tom Rini | dec7ea0 | 2024-05-20 13:35:03 -0600 | [diff] [blame] | 14 | #include <config.h> |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 15 | #include <command.h> |
Biwen Li | 247dac6 | 2020-05-01 20:03:56 +0800 | [diff] [blame] | 16 | #include <dm.h> |
Simon Glass | 0f2af88 | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 17 | #include <log.h> |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 18 | #include <rtc.h> |
| 19 | #include <i2c.h> |
| 20 | |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 21 | /* |
| 22 | * RTC register addresses |
| 23 | */ |
Kenth Eriksson | 7819633 | 2012-07-12 19:59:44 +0000 | [diff] [blame] | 24 | #if defined CONFIG_RTC_DS1337 |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 25 | #define RTC_SEC_REG_ADDR 0x0 |
| 26 | #define RTC_MIN_REG_ADDR 0x1 |
| 27 | #define RTC_HR_REG_ADDR 0x2 |
| 28 | #define RTC_DAY_REG_ADDR 0x3 |
| 29 | #define RTC_DATE_REG_ADDR 0x4 |
| 30 | #define RTC_MON_REG_ADDR 0x5 |
| 31 | #define RTC_YR_REG_ADDR 0x6 |
| 32 | #define RTC_CTL_REG_ADDR 0x0e |
| 33 | #define RTC_STAT_REG_ADDR 0x0f |
Werner Pfister | 3563ca4 | 2009-09-21 14:49:55 +0200 | [diff] [blame] | 34 | #define RTC_TC_REG_ADDR 0x10 |
Kenth Eriksson | 7819633 | 2012-07-12 19:59:44 +0000 | [diff] [blame] | 35 | #elif defined CONFIG_RTC_DS1388 |
| 36 | #define RTC_SEC_REG_ADDR 0x1 |
| 37 | #define RTC_MIN_REG_ADDR 0x2 |
| 38 | #define RTC_HR_REG_ADDR 0x3 |
| 39 | #define RTC_DAY_REG_ADDR 0x4 |
| 40 | #define RTC_DATE_REG_ADDR 0x5 |
| 41 | #define RTC_MON_REG_ADDR 0x6 |
| 42 | #define RTC_YR_REG_ADDR 0x7 |
| 43 | #define RTC_CTL_REG_ADDR 0x0c |
| 44 | #define RTC_STAT_REG_ADDR 0x0b |
| 45 | #define RTC_TC_REG_ADDR 0x0a |
| 46 | #endif |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 47 | |
| 48 | /* |
| 49 | * RTC control register bits |
| 50 | */ |
Wolfgang Denk | 331dfe8 | 2008-03-26 15:38:47 +0100 | [diff] [blame] | 51 | #define RTC_CTL_BIT_A1IE 0x1 /* Alarm 1 interrupt enable */ |
| 52 | #define RTC_CTL_BIT_A2IE 0x2 /* Alarm 2 interrupt enable */ |
| 53 | #define RTC_CTL_BIT_INTCN 0x4 /* Interrupt control */ |
| 54 | #define RTC_CTL_BIT_RS1 0x8 /* Rate select 1 */ |
| 55 | #define RTC_CTL_BIT_RS2 0x10 /* Rate select 2 */ |
| 56 | #define RTC_CTL_BIT_DOSC 0x80 /* Disable Oscillator */ |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 57 | |
| 58 | /* |
| 59 | * RTC status register bits |
| 60 | */ |
Wolfgang Denk | 331dfe8 | 2008-03-26 15:38:47 +0100 | [diff] [blame] | 61 | #define RTC_STAT_BIT_A1F 0x1 /* Alarm 1 flag */ |
| 62 | #define RTC_STAT_BIT_A2F 0x2 /* Alarm 2 flag */ |
| 63 | #define RTC_STAT_BIT_OSF 0x80 /* Oscillator stop flag */ |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 64 | |
Biwen Li | 247dac6 | 2020-05-01 20:03:56 +0800 | [diff] [blame] | 65 | #if !CONFIG_IS_ENABLED(DM_RTC) |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 66 | static uchar rtc_read (uchar reg); |
| 67 | static void rtc_write (uchar reg, uchar val); |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 68 | |
| 69 | /* |
| 70 | * Get the current time from the RTC |
| 71 | */ |
Yuri Tikhonov | 9bacd94 | 2008-03-20 17:56:04 +0300 | [diff] [blame] | 72 | int rtc_get (struct rtc_time *tmp) |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 73 | { |
Yuri Tikhonov | 9bacd94 | 2008-03-20 17:56:04 +0300 | [diff] [blame] | 74 | int rel = 0; |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 75 | uchar sec, min, hour, mday, wday, mon_cent, year, control, status; |
| 76 | |
| 77 | control = rtc_read (RTC_CTL_REG_ADDR); |
| 78 | status = rtc_read (RTC_STAT_REG_ADDR); |
| 79 | sec = rtc_read (RTC_SEC_REG_ADDR); |
| 80 | min = rtc_read (RTC_MIN_REG_ADDR); |
| 81 | hour = rtc_read (RTC_HR_REG_ADDR); |
| 82 | wday = rtc_read (RTC_DAY_REG_ADDR); |
| 83 | mday = rtc_read (RTC_DATE_REG_ADDR); |
| 84 | mon_cent = rtc_read (RTC_MON_REG_ADDR); |
| 85 | year = rtc_read (RTC_YR_REG_ADDR); |
| 86 | |
Kenth Eriksson | 7819633 | 2012-07-12 19:59:44 +0000 | [diff] [blame] | 87 | /* No century bit, assume year 2000 */ |
| 88 | #ifdef CONFIG_RTC_DS1388 |
| 89 | mon_cent |= 0x80; |
| 90 | #endif |
| 91 | |
Wolfgang Denk | c0b15f0 | 2011-10-29 09:39:11 +0000 | [diff] [blame] | 92 | debug("Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x " |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 93 | "hr: %02x min: %02x sec: %02x control: %02x status: %02x\n", |
| 94 | year, mon_cent, mday, wday, hour, min, sec, control, status); |
| 95 | |
| 96 | if (status & RTC_STAT_BIT_OSF) { |
| 97 | printf ("### Warning: RTC oscillator has stopped\n"); |
| 98 | /* clear the OSF flag */ |
| 99 | rtc_write (RTC_STAT_REG_ADDR, |
| 100 | rtc_read (RTC_STAT_REG_ADDR) & ~RTC_STAT_BIT_OSF); |
Yuri Tikhonov | 9bacd94 | 2008-03-20 17:56:04 +0300 | [diff] [blame] | 101 | rel = -1; |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 102 | } |
| 103 | |
| 104 | tmp->tm_sec = bcd2bin (sec & 0x7F); |
| 105 | tmp->tm_min = bcd2bin (min & 0x7F); |
| 106 | tmp->tm_hour = bcd2bin (hour & 0x3F); |
| 107 | tmp->tm_mday = bcd2bin (mday & 0x3F); |
| 108 | tmp->tm_mon = bcd2bin (mon_cent & 0x1F); |
| 109 | tmp->tm_year = bcd2bin (year) + ((mon_cent & 0x80) ? 2000 : 1900); |
| 110 | tmp->tm_wday = bcd2bin ((wday - 1) & 0x07); |
| 111 | tmp->tm_yday = 0; |
| 112 | tmp->tm_isdst= 0; |
| 113 | |
Wolfgang Denk | c0b15f0 | 2011-10-29 09:39:11 +0000 | [diff] [blame] | 114 | debug("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 115 | tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, |
| 116 | tmp->tm_hour, tmp->tm_min, tmp->tm_sec); |
Yuri Tikhonov | 9bacd94 | 2008-03-20 17:56:04 +0300 | [diff] [blame] | 117 | |
| 118 | return rel; |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 119 | } |
| 120 | |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 121 | /* |
| 122 | * Set the RTC |
| 123 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 97a2e10 | 2008-09-01 23:06:23 +0200 | [diff] [blame] | 124 | int rtc_set (struct rtc_time *tmp) |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 125 | { |
| 126 | uchar century; |
| 127 | |
Wolfgang Denk | c0b15f0 | 2011-10-29 09:39:11 +0000 | [diff] [blame] | 128 | debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 129 | tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, |
| 130 | tmp->tm_hour, tmp->tm_min, tmp->tm_sec); |
| 131 | |
| 132 | rtc_write (RTC_YR_REG_ADDR, bin2bcd (tmp->tm_year % 100)); |
| 133 | |
| 134 | century = (tmp->tm_year >= 2000) ? 0x80 : 0; |
| 135 | rtc_write (RTC_MON_REG_ADDR, bin2bcd (tmp->tm_mon) | century); |
| 136 | |
| 137 | rtc_write (RTC_DAY_REG_ADDR, bin2bcd (tmp->tm_wday + 1)); |
| 138 | rtc_write (RTC_DATE_REG_ADDR, bin2bcd (tmp->tm_mday)); |
| 139 | rtc_write (RTC_HR_REG_ADDR, bin2bcd (tmp->tm_hour)); |
| 140 | rtc_write (RTC_MIN_REG_ADDR, bin2bcd (tmp->tm_min)); |
| 141 | rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec)); |
Jean-Christophe PLAGNIOL-VILLARD | 97a2e10 | 2008-09-01 23:06:23 +0200 | [diff] [blame] | 142 | |
| 143 | return 0; |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 144 | } |
| 145 | |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 146 | /* |
| 147 | * Reset the RTC. We also enable the oscillator output on the |
| 148 | * SQW/INTB* pin and program it for 32,768 Hz output. Note that |
| 149 | * according to the datasheet, turning on the square wave output |
| 150 | * increases the current drain on the backup battery from about |
Chris Packham | 2d3ac51 | 2017-05-30 12:03:33 +1200 | [diff] [blame] | 151 | * 600 nA to 2uA. Define CONFIG_RTC_DS1337_NOOSC if you wish to turn |
Joakim Tjernlund | 2ef2731 | 2008-03-26 13:02:13 +0100 | [diff] [blame] | 152 | * off the OSC output. |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 153 | */ |
Kenth Eriksson | 7819633 | 2012-07-12 19:59:44 +0000 | [diff] [blame] | 154 | |
Chris Packham | 2d3ac51 | 2017-05-30 12:03:33 +1200 | [diff] [blame] | 155 | #ifdef CONFIG_RTC_DS1337_NOOSC |
Joakim Tjernlund | 2ef2731 | 2008-03-26 13:02:13 +0100 | [diff] [blame] | 156 | #define RTC_DS1337_RESET_VAL \ |
Wolfgang Denk | 331dfe8 | 2008-03-26 15:38:47 +0100 | [diff] [blame] | 157 | (RTC_CTL_BIT_INTCN | RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS2) |
Joakim Tjernlund | 2ef2731 | 2008-03-26 13:02:13 +0100 | [diff] [blame] | 158 | #else |
| 159 | #define RTC_DS1337_RESET_VAL (RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS2) |
| 160 | #endif |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 161 | void rtc_reset (void) |
| 162 | { |
Chris Packham | 2d3ac51 | 2017-05-30 12:03:33 +1200 | [diff] [blame] | 163 | #ifdef CONFIG_RTC_DS1337 |
Joakim Tjernlund | 2ef2731 | 2008-03-26 13:02:13 +0100 | [diff] [blame] | 164 | rtc_write (RTC_CTL_REG_ADDR, RTC_DS1337_RESET_VAL); |
Chris Packham | 2d3ac51 | 2017-05-30 12:03:33 +1200 | [diff] [blame] | 165 | #elif defined CONFIG_RTC_DS1388 |
Kenth Eriksson | 7819633 | 2012-07-12 19:59:44 +0000 | [diff] [blame] | 166 | rtc_write(RTC_CTL_REG_ADDR, 0x0); /* hw default */ |
| 167 | #endif |
Chris Packham | 2d3ac51 | 2017-05-30 12:03:33 +1200 | [diff] [blame] | 168 | #ifdef CONFIG_RTC_DS1339_TCR_VAL |
| 169 | rtc_write (RTC_TC_REG_ADDR, CONFIG_RTC_DS1339_TCR_VAL); |
Werner Pfister | 3563ca4 | 2009-09-21 14:49:55 +0200 | [diff] [blame] | 170 | #endif |
Chris Packham | 2d3ac51 | 2017-05-30 12:03:33 +1200 | [diff] [blame] | 171 | #ifdef CONFIG_RTC_DS1388_TCR_VAL |
| 172 | rtc_write(RTC_TC_REG_ADDR, CONFIG_RTC_DS1388_TCR_VAL); |
Kenth Eriksson | 7819633 | 2012-07-12 19:59:44 +0000 | [diff] [blame] | 173 | #endif |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 174 | } |
| 175 | |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 176 | /* |
| 177 | * Helper functions |
| 178 | */ |
| 179 | |
| 180 | static |
| 181 | uchar rtc_read (uchar reg) |
| 182 | { |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 183 | return (i2c_reg_read (CFG_SYS_I2C_RTC_ADDR, reg)); |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 184 | } |
| 185 | |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 186 | static void rtc_write (uchar reg, uchar val) |
| 187 | { |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 188 | i2c_reg_write (CFG_SYS_I2C_RTC_ADDR, reg, val); |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 189 | } |
Biwen Li | 247dac6 | 2020-05-01 20:03:56 +0800 | [diff] [blame] | 190 | #else |
| 191 | static uchar rtc_read(struct udevice *dev, uchar reg) |
| 192 | { |
| 193 | return dm_i2c_reg_read(dev, reg); |
| 194 | } |
| 195 | |
| 196 | static void rtc_write(struct udevice *dev, uchar reg, uchar val) |
| 197 | { |
| 198 | dm_i2c_reg_write(dev, reg, val); |
| 199 | } |
| 200 | |
| 201 | static int ds1337_rtc_get(struct udevice *dev, struct rtc_time *tmp) |
| 202 | { |
| 203 | int rel = 0; |
| 204 | uchar sec, min, hour, mday, wday, mon_cent, year, control, status; |
| 205 | |
| 206 | control = rtc_read(dev, RTC_CTL_REG_ADDR); |
| 207 | status = rtc_read(dev, RTC_STAT_REG_ADDR); |
| 208 | sec = rtc_read(dev, RTC_SEC_REG_ADDR); |
| 209 | min = rtc_read(dev, RTC_MIN_REG_ADDR); |
| 210 | hour = rtc_read(dev, RTC_HR_REG_ADDR); |
| 211 | wday = rtc_read(dev, RTC_DAY_REG_ADDR); |
| 212 | mday = rtc_read(dev, RTC_DATE_REG_ADDR); |
| 213 | mon_cent = rtc_read(dev, RTC_MON_REG_ADDR); |
| 214 | year = rtc_read(dev, RTC_YR_REG_ADDR); |
| 215 | |
| 216 | /* No century bit, assume year 2000 */ |
| 217 | #ifdef CONFIG_RTC_DS1388 |
| 218 | mon_cent |= 0x80; |
| 219 | #endif |
| 220 | |
| 221 | debug("Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x\n", |
| 222 | year, mon_cent, mday, wday); |
| 223 | debug("hr: %02x min: %02x sec: %02x control: %02x status: %02x\n", |
| 224 | hour, min, sec, control, status); |
| 225 | |
| 226 | if (status & RTC_STAT_BIT_OSF) { |
| 227 | printf("### Warning: RTC oscillator has stopped\n"); |
| 228 | /* clear the OSF flag */ |
| 229 | rtc_write(dev, RTC_STAT_REG_ADDR, |
| 230 | rtc_read(dev, RTC_STAT_REG_ADDR) & ~RTC_STAT_BIT_OSF); |
| 231 | rel = -1; |
| 232 | } |
| 233 | |
| 234 | tmp->tm_sec = bcd2bin(sec & 0x7F); |
| 235 | tmp->tm_min = bcd2bin(min & 0x7F); |
| 236 | tmp->tm_hour = bcd2bin(hour & 0x3F); |
| 237 | tmp->tm_mday = bcd2bin(mday & 0x3F); |
| 238 | tmp->tm_mon = bcd2bin(mon_cent & 0x1F); |
| 239 | tmp->tm_year = bcd2bin(year) + ((mon_cent & 0x80) ? 2000 : 1900); |
| 240 | tmp->tm_wday = bcd2bin((wday - 1) & 0x07); |
| 241 | tmp->tm_yday = 0; |
| 242 | tmp->tm_isdst = 0; |
| 243 | |
| 244 | debug("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", |
| 245 | tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, |
| 246 | tmp->tm_hour, tmp->tm_min, tmp->tm_sec); |
| 247 | |
| 248 | return rel; |
| 249 | } |
| 250 | |
| 251 | static int ds1337_rtc_set(struct udevice *dev, const struct rtc_time *tmp) |
| 252 | { |
| 253 | uchar century; |
| 254 | |
| 255 | debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", |
| 256 | tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, |
| 257 | tmp->tm_hour, tmp->tm_min, tmp->tm_sec); |
| 258 | |
| 259 | rtc_write(dev, RTC_YR_REG_ADDR, bin2bcd(tmp->tm_year % 100)); |
| 260 | |
| 261 | century = (tmp->tm_year >= 2000) ? 0x80 : 0; |
| 262 | rtc_write(dev, RTC_MON_REG_ADDR, bin2bcd(tmp->tm_mon) | century); |
| 263 | |
| 264 | rtc_write(dev, RTC_DAY_REG_ADDR, bin2bcd(tmp->tm_wday + 1)); |
| 265 | rtc_write(dev, RTC_DATE_REG_ADDR, bin2bcd(tmp->tm_mday)); |
| 266 | rtc_write(dev, RTC_HR_REG_ADDR, bin2bcd(tmp->tm_hour)); |
| 267 | rtc_write(dev, RTC_MIN_REG_ADDR, bin2bcd(tmp->tm_min)); |
| 268 | rtc_write(dev, RTC_SEC_REG_ADDR, bin2bcd(tmp->tm_sec)); |
| 269 | |
| 270 | return 0; |
| 271 | } |
| 272 | |
| 273 | #ifdef CONFIG_RTC_DS1337_NOOSC |
| 274 | #define RTC_DS1337_RESET_VAL \ |
| 275 | (RTC_CTL_BIT_INTCN | RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS2) |
| 276 | #else |
| 277 | #define RTC_DS1337_RESET_VAL (RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS2) |
| 278 | #endif |
| 279 | static int ds1337_rtc_reset(struct udevice *dev) |
| 280 | { |
| 281 | #ifdef CONFIG_RTC_DS1337 |
| 282 | rtc_write(dev, RTC_CTL_REG_ADDR, RTC_DS1337_RESET_VAL); |
| 283 | #elif defined CONFIG_RTC_DS1388 |
| 284 | rtc_write(dev, RTC_CTL_REG_ADDR, 0x0); /* hw default */ |
| 285 | #endif |
| 286 | #ifdef CONFIG_RTC_DS1339_TCR_VAL |
| 287 | rtc_write(dev, RTC_TC_REG_ADDR, CONFIG_RTC_DS1339_TCR_VAL); |
| 288 | #endif |
| 289 | #ifdef CONFIG_RTC_DS1388_TCR_VAL |
| 290 | rtc_write(dev, RTC_TC_REG_ADDR, CONFIG_RTC_DS1388_TCR_VAL); |
| 291 | #endif |
| 292 | return 0; |
| 293 | } |
| 294 | |
| 295 | static const struct rtc_ops ds1337_rtc_ops = { |
| 296 | .get = ds1337_rtc_get, |
| 297 | .set = ds1337_rtc_set, |
| 298 | .reset = ds1337_rtc_reset, |
| 299 | }; |
| 300 | |
| 301 | static const struct udevice_id ds1337_rtc_ids[] = { |
| 302 | { .compatible = "ds1337" }, |
| 303 | { .compatible = "ds1338" }, |
Clemens Gruber | e015c61 | 2021-11-05 14:46:50 +0100 | [diff] [blame] | 304 | { .compatible = "ds1339" }, |
Biwen Li | 247dac6 | 2020-05-01 20:03:56 +0800 | [diff] [blame] | 305 | { } |
| 306 | }; |
| 307 | |
| 308 | U_BOOT_DRIVER(rtc_ds1337) = { |
| 309 | .name = "rtc-ds1337", |
| 310 | .id = UCLASS_RTC, |
| 311 | .of_match = ds1337_rtc_ids, |
| 312 | .ops = &ds1337_rtc_ops, |
| 313 | }; |
| 314 | #endif |