Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2015-2016 Marvell International Ltd. |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 4 | */ |
| 5 | |
Marek Behún | 5d6b448 | 2022-01-20 01:04:42 +0100 | [diff] [blame] | 6 | #include <fdt_support.h> |
Simon Glass | 0f2af88 | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 7 | #include <log.h> |
Simon Glass | 3ba929a | 2020-10-30 21:38:53 -0600 | [diff] [blame] | 8 | #include <asm/global_data.h> |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 9 | #include <asm/io.h> |
| 10 | #include <asm/arch/cpu.h> |
| 11 | #include <asm/arch/soc.h> |
Simon Glass | dbd7954 | 2020-05-10 11:40:11 -0600 | [diff] [blame] | 12 | #include <linux/delay.h> |
Pali Rohár | 04c9347 | 2021-11-26 14:57:13 +0100 | [diff] [blame] | 13 | #include <phy.h> |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 14 | |
| 15 | #include "comphy_a3700.h" |
| 16 | |
| 17 | DECLARE_GLOBAL_DATA_PTR; |
| 18 | |
Marek Behún | 817c2ce | 2018-04-24 17:21:23 +0200 | [diff] [blame] | 19 | struct comphy_mux_data a3700_comphy_mux_data[] = { |
Igal Liberman | ffd5d2f | 2017-04-26 15:40:00 +0300 | [diff] [blame] | 20 | /* Lane 0 */ |
Marek Behún | 817c2ce | 2018-04-24 17:21:23 +0200 | [diff] [blame] | 21 | { |
| 22 | 4, |
| 23 | { |
Igal Liberman | ffd5d2f | 2017-04-26 15:40:00 +0300 | [diff] [blame] | 24 | { COMPHY_TYPE_UNCONNECTED, 0x0 }, |
| 25 | { COMPHY_TYPE_SGMII1, 0x0 }, |
| 26 | { COMPHY_TYPE_USB3_HOST0, 0x1 }, |
| 27 | { COMPHY_TYPE_USB3_DEVICE, 0x1 } |
Marek Behún | 817c2ce | 2018-04-24 17:21:23 +0200 | [diff] [blame] | 28 | } |
| 29 | }, |
Igal Liberman | ffd5d2f | 2017-04-26 15:40:00 +0300 | [diff] [blame] | 30 | /* Lane 1 */ |
Marek Behún | 817c2ce | 2018-04-24 17:21:23 +0200 | [diff] [blame] | 31 | { |
| 32 | 3, |
| 33 | { |
Igal Liberman | ffd5d2f | 2017-04-26 15:40:00 +0300 | [diff] [blame] | 34 | { COMPHY_TYPE_UNCONNECTED, 0x0}, |
| 35 | { COMPHY_TYPE_SGMII0, 0x0}, |
| 36 | { COMPHY_TYPE_PEX0, 0x1} |
Marek Behún | 817c2ce | 2018-04-24 17:21:23 +0200 | [diff] [blame] | 37 | } |
| 38 | }, |
Igal Liberman | ffd5d2f | 2017-04-26 15:40:00 +0300 | [diff] [blame] | 39 | /* Lane 2 */ |
Marek Behún | 817c2ce | 2018-04-24 17:21:23 +0200 | [diff] [blame] | 40 | { |
| 41 | 4, |
| 42 | { |
Igal Liberman | ffd5d2f | 2017-04-26 15:40:00 +0300 | [diff] [blame] | 43 | { COMPHY_TYPE_UNCONNECTED, 0x0}, |
| 44 | { COMPHY_TYPE_SATA0, 0x0}, |
| 45 | { COMPHY_TYPE_USB3_HOST0, 0x1}, |
| 46 | { COMPHY_TYPE_USB3_DEVICE, 0x1} |
Marek Behún | 817c2ce | 2018-04-24 17:21:23 +0200 | [diff] [blame] | 47 | } |
| 48 | }, |
| 49 | }; |
| 50 | |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 51 | struct sgmii_phy_init_data_fix { |
| 52 | u16 addr; |
| 53 | u16 value; |
| 54 | }; |
| 55 | |
| 56 | /* Changes to 40M1G25 mode data required for running 40M3G125 init mode */ |
| 57 | static struct sgmii_phy_init_data_fix sgmii_phy_init_fix[] = { |
| 58 | {0x005, 0x07CC}, {0x015, 0x0000}, {0x01B, 0x0000}, {0x01D, 0x0000}, |
| 59 | {0x01E, 0x0000}, {0x01F, 0x0000}, {0x020, 0x0000}, {0x021, 0x0030}, |
| 60 | {0x026, 0x0888}, {0x04D, 0x0152}, {0x04F, 0xA020}, {0x050, 0x07CC}, |
| 61 | {0x053, 0xE9CA}, {0x055, 0xBD97}, {0x071, 0x3015}, {0x076, 0x03AA}, |
| 62 | {0x07C, 0x0FDF}, {0x0C2, 0x3030}, {0x0C3, 0x8000}, {0x0E2, 0x5550}, |
| 63 | {0x0E3, 0x12A4}, {0x0E4, 0x7D00}, {0x0E6, 0x0C83}, {0x101, 0xFCC0}, |
| 64 | {0x104, 0x0C10} |
| 65 | }; |
| 66 | |
| 67 | /* 40M1G25 mode init data */ |
| 68 | static u16 sgmii_phy_init[512] = { |
| 69 | /* 0 1 2 3 4 5 6 7 */ |
| 70 | /*-----------------------------------------------------------*/ |
| 71 | /* 8 9 A B C D E F */ |
| 72 | 0x3110, 0xFD83, 0x6430, 0x412F, 0x82C0, 0x06FA, 0x4500, 0x6D26, /* 00 */ |
| 73 | 0xAFC0, 0x8000, 0xC000, 0x0000, 0x2000, 0x49CC, 0x0BC9, 0x2A52, /* 08 */ |
| 74 | 0x0BD2, 0x0CDE, 0x13D2, 0x0CE8, 0x1149, 0x10E0, 0x0000, 0x0000, /* 10 */ |
| 75 | 0x0000, 0x0000, 0x0000, 0x0001, 0x0000, 0x4134, 0x0D2D, 0xFFFF, /* 18 */ |
| 76 | 0xFFE0, 0x4030, 0x1016, 0x0030, 0x0000, 0x0800, 0x0866, 0x0000, /* 20 */ |
| 77 | 0x0000, 0x0000, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, /* 28 */ |
| 78 | 0xFFFF, 0xFFFF, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* 30 */ |
| 79 | 0x0000, 0x0000, 0x000F, 0x6A62, 0x1988, 0x3100, 0x3100, 0x3100, /* 38 */ |
| 80 | 0x3100, 0xA708, 0x2430, 0x0830, 0x1030, 0x4610, 0xFF00, 0xFF00, /* 40 */ |
| 81 | 0x0060, 0x1000, 0x0400, 0x0040, 0x00F0, 0x0155, 0x1100, 0xA02A, /* 48 */ |
| 82 | 0x06FA, 0x0080, 0xB008, 0xE3ED, 0x5002, 0xB592, 0x7A80, 0x0001, /* 50 */ |
| 83 | 0x020A, 0x8820, 0x6014, 0x8054, 0xACAA, 0xFC88, 0x2A02, 0x45CF, /* 58 */ |
| 84 | 0x000F, 0x1817, 0x2860, 0x064F, 0x0000, 0x0204, 0x1800, 0x6000, /* 60 */ |
| 85 | 0x810F, 0x4F23, 0x4000, 0x4498, 0x0850, 0x0000, 0x000E, 0x1002, /* 68 */ |
| 86 | 0x9D3A, 0x3009, 0xD066, 0x0491, 0x0001, 0x6AB0, 0x0399, 0x3780, /* 70 */ |
| 87 | 0x0040, 0x5AC0, 0x4A80, 0x0000, 0x01DF, 0x0000, 0x0007, 0x0000, /* 78 */ |
| 88 | 0x2D54, 0x00A1, 0x4000, 0x0100, 0xA20A, 0x0000, 0x0000, 0x0000, /* 80 */ |
| 89 | 0x0000, 0x0000, 0x0000, 0x7400, 0x0E81, 0x1000, 0x1242, 0x0210, /* 88 */ |
| 90 | 0x80DF, 0x0F1F, 0x2F3F, 0x4F5F, 0x6F7F, 0x0F1F, 0x2F3F, 0x4F5F, /* 90 */ |
| 91 | 0x6F7F, 0x4BAD, 0x0000, 0x0000, 0x0800, 0x0000, 0x2400, 0xB651, /* 98 */ |
| 92 | 0xC9E0, 0x4247, 0x0A24, 0x0000, 0xAF19, 0x1004, 0x0000, 0x0000, /* A0 */ |
| 93 | 0x0000, 0x0013, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* A8 */ |
| 94 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* B0 */ |
| 95 | 0x0000, 0x0000, 0x0000, 0x0060, 0x0000, 0x0000, 0x0000, 0x0000, /* B8 */ |
| 96 | 0x0000, 0x0000, 0x3010, 0xFA00, 0x0000, 0x0000, 0x0000, 0x0003, /* C0 */ |
| 97 | 0x1618, 0x8200, 0x8000, 0x0400, 0x050F, 0x0000, 0x0000, 0x0000, /* C8 */ |
| 98 | 0x4C93, 0x0000, 0x1000, 0x1120, 0x0010, 0x1242, 0x1242, 0x1E00, /* D0 */ |
| 99 | 0x0000, 0x0000, 0x0000, 0x00F8, 0x0000, 0x0041, 0x0800, 0x0000, /* D8 */ |
| 100 | 0x82A0, 0x572E, 0x2490, 0x14A9, 0x4E00, 0x0000, 0x0803, 0x0541, /* E0 */ |
| 101 | 0x0C15, 0x0000, 0x0000, 0x0400, 0x2626, 0x0000, 0x0000, 0x4200, /* E8 */ |
| 102 | 0x0000, 0xAA55, 0x1020, 0x0000, 0x0000, 0x5010, 0x0000, 0x0000, /* F0 */ |
| 103 | 0x0000, 0x0000, 0x5000, 0x0000, 0x0000, 0x0000, 0x02F2, 0x0000, /* F8 */ |
| 104 | 0x101F, 0xFDC0, 0x4000, 0x8010, 0x0110, 0x0006, 0x0000, 0x0000, /*100 */ |
| 105 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*108 */ |
| 106 | 0x04CF, 0x0000, 0x04CF, 0x0000, 0x04CF, 0x0000, 0x04C6, 0x0000, /*110 */ |
| 107 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*118 */ |
| 108 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*120 */ |
| 109 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*128 */ |
| 110 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*130 */ |
| 111 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*138 */ |
| 112 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*140 */ |
| 113 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*148 */ |
| 114 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*150 */ |
| 115 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*158 */ |
| 116 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*160 */ |
| 117 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*168 */ |
| 118 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*170 */ |
| 119 | 0x0000, 0x0000, 0x0000, 0x00F0, 0x08A2, 0x3112, 0x0A14, 0x0000, /*178 */ |
| 120 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*180 */ |
| 121 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*188 */ |
| 122 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*190 */ |
| 123 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*198 */ |
| 124 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1A0 */ |
| 125 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1A8 */ |
| 126 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1B0 */ |
| 127 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1B8 */ |
| 128 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1C0 */ |
| 129 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1C8 */ |
| 130 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1D0 */ |
| 131 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1D8 */ |
| 132 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1E0 */ |
| 133 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1E8 */ |
| 134 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1F0 */ |
| 135 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 /*1F8 */ |
| 136 | }; |
| 137 | |
| 138 | /* |
| 139 | * comphy_poll_reg |
| 140 | * |
| 141 | * return: 1 on success, 0 on timeout |
| 142 | */ |
Marek Behún | 69fb636 | 2018-04-24 17:21:15 +0200 | [diff] [blame] | 143 | static u32 comphy_poll_reg(void *addr, u32 val, u32 mask, u8 op_type) |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 144 | { |
Marek Behún | 69fb636 | 2018-04-24 17:21:15 +0200 | [diff] [blame] | 145 | u32 rval = 0xDEAD, timeout; |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 146 | |
Marek Behún | 69fb636 | 2018-04-24 17:21:15 +0200 | [diff] [blame] | 147 | for (timeout = PLL_LOCK_TIMEOUT; timeout > 0; timeout--) { |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 148 | if (op_type == POLL_16B_REG) |
| 149 | rval = readw(addr); /* 16 bit */ |
| 150 | else |
| 151 | rval = readl(addr) ; /* 32 bit */ |
| 152 | |
| 153 | if ((rval & mask) == val) |
| 154 | return 1; |
| 155 | |
| 156 | udelay(10000); |
| 157 | } |
| 158 | |
| 159 | debug("Time out waiting (%p = %#010x)\n", addr, rval); |
| 160 | return 0; |
| 161 | } |
| 162 | |
| 163 | /* |
| 164 | * comphy_pcie_power_up |
| 165 | * |
| 166 | * return: 1 if PLL locked (OK), 0 otherwise (FAIL) |
| 167 | */ |
| 168 | static int comphy_pcie_power_up(u32 speed, u32 invert) |
| 169 | { |
Marek Behún | ef6f36e | 2018-04-24 17:21:18 +0200 | [diff] [blame] | 170 | int ret; |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 171 | |
| 172 | debug_enter(); |
| 173 | |
| 174 | /* |
| 175 | * 1. Enable max PLL. |
| 176 | */ |
Marek Behún | a89ae13 | 2018-04-24 17:21:14 +0200 | [diff] [blame] | 177 | reg_set16(phy_addr(PCIE, LANE_CFG1), bf_use_max_pll_rate, 0); |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 178 | |
| 179 | /* |
| 180 | * 2. Select 20 bit SERDES interface. |
| 181 | */ |
Marek Behún | a89ae13 | 2018-04-24 17:21:14 +0200 | [diff] [blame] | 182 | reg_set16(phy_addr(PCIE, GLOB_CLK_SRC_LO), bf_cfg_sel_20b, 0); |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 183 | |
| 184 | /* |
| 185 | * 3. Force to use reg setting for PCIe mode |
| 186 | */ |
Marek Behún | a89ae13 | 2018-04-24 17:21:14 +0200 | [diff] [blame] | 187 | reg_set16(phy_addr(PCIE, MISC_REG1), bf_sel_bits_pcie_force, 0); |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 188 | |
| 189 | /* |
| 190 | * 4. Change RX wait |
| 191 | */ |
Marek Behún | a89ae13 | 2018-04-24 17:21:14 +0200 | [diff] [blame] | 192 | reg_set16(phy_addr(PCIE, PWR_MGM_TIM1), 0x10C, 0xFFFF); |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 193 | |
| 194 | /* |
| 195 | * 5. Enable idle sync |
| 196 | */ |
Marek Behún | a89ae13 | 2018-04-24 17:21:14 +0200 | [diff] [blame] | 197 | reg_set16(phy_addr(PCIE, UNIT_CTRL), 0x60 | rb_idle_sync_en, 0xFFFF); |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 198 | |
| 199 | /* |
| 200 | * 6. Enable the output of 100M/125M/500M clock |
| 201 | */ |
Marek Behún | a89ae13 | 2018-04-24 17:21:14 +0200 | [diff] [blame] | 202 | reg_set16(phy_addr(PCIE, MISC_REG0), |
Pali Rohár | 81b1d62 | 2021-09-24 16:11:55 +0200 | [diff] [blame] | 203 | 0xA00D | rb_clk500m_en | rb_txdclk_2x_sel | rb_clk100m_125m_en, 0xFFFF); |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 204 | |
| 205 | /* |
| 206 | * 7. Enable TX |
| 207 | */ |
Marek Behún | a89ae13 | 2018-04-24 17:21:14 +0200 | [diff] [blame] | 208 | reg_set(PCIE_REF_CLK_ADDR, 0x1342, 0xFFFFFFFF); |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 209 | |
| 210 | /* |
| 211 | * 8. Check crystal jumper setting and program the Power and PLL |
| 212 | * Control accordingly |
| 213 | */ |
| 214 | if (get_ref_clk() == 40) { |
Marek Behún | a89ae13 | 2018-04-24 17:21:14 +0200 | [diff] [blame] | 215 | /* 40 MHz */ |
| 216 | reg_set16(phy_addr(PCIE, PWR_PLL_CTRL), 0xFC63, 0xFFFF); |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 217 | } else { |
Marek Behún | a89ae13 | 2018-04-24 17:21:14 +0200 | [diff] [blame] | 218 | /* 25 MHz */ |
| 219 | reg_set16(phy_addr(PCIE, PWR_PLL_CTRL), 0xFC62, 0xFFFF); |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 220 | } |
| 221 | |
| 222 | /* |
| 223 | * 9. Override Speed_PLL value and use MAC PLL |
| 224 | */ |
Marek Behún | a89ae13 | 2018-04-24 17:21:14 +0200 | [diff] [blame] | 225 | reg_set16(phy_addr(PCIE, KVCO_CAL_CTRL), 0x0040 | rb_use_max_pll_rate, |
Marek Behún | 4c02f73 | 2018-04-24 17:21:12 +0200 | [diff] [blame] | 226 | 0xFFFF); |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 227 | |
| 228 | /* |
| 229 | * 10. Check the Polarity invert bit |
| 230 | */ |
Igal Liberman | ffd5d2f | 2017-04-26 15:40:00 +0300 | [diff] [blame] | 231 | if (invert & COMPHY_POLARITY_TXD_INVERT) |
Marek Behún | a89ae13 | 2018-04-24 17:21:14 +0200 | [diff] [blame] | 232 | reg_set16(phy_addr(PCIE, SYNC_PATTERN), phy_txd_inv, 0); |
Pali Rohár | 6148ea6 | 2021-09-24 16:11:56 +0200 | [diff] [blame] | 233 | else |
| 234 | reg_set16(phy_addr(PCIE, SYNC_PATTERN), 0, phy_txd_inv); |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 235 | |
Igal Liberman | ffd5d2f | 2017-04-26 15:40:00 +0300 | [diff] [blame] | 236 | if (invert & COMPHY_POLARITY_RXD_INVERT) |
Marek Behún | a89ae13 | 2018-04-24 17:21:14 +0200 | [diff] [blame] | 237 | reg_set16(phy_addr(PCIE, SYNC_PATTERN), phy_rxd_inv, 0); |
Pali Rohár | 6148ea6 | 2021-09-24 16:11:56 +0200 | [diff] [blame] | 238 | else |
| 239 | reg_set16(phy_addr(PCIE, SYNC_PATTERN), 0, phy_rxd_inv); |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 240 | |
| 241 | /* |
| 242 | * 11. Release SW reset |
| 243 | */ |
Marek Behún | a89ae13 | 2018-04-24 17:21:14 +0200 | [diff] [blame] | 244 | reg_set16(phy_addr(PCIE, GLOB_PHY_CTRL0), |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 245 | rb_mode_core_clk_freq_sel | rb_mode_pipe_width_32, |
| 246 | bf_soft_rst | bf_mode_refdiv); |
| 247 | |
| 248 | /* Wait for > 55 us to allow PCLK be enabled */ |
| 249 | udelay(PLL_SET_DELAY_US); |
| 250 | |
| 251 | /* Assert PCLK enabled */ |
Marek Behún | a89ae13 | 2018-04-24 17:21:14 +0200 | [diff] [blame] | 252 | ret = comphy_poll_reg(phy_addr(PCIE, LANE_STAT1), /* address */ |
| 253 | rb_txdclk_pclk_en, /* value */ |
| 254 | rb_txdclk_pclk_en, /* mask */ |
Marek Behún | a89ae13 | 2018-04-24 17:21:14 +0200 | [diff] [blame] | 255 | POLL_16B_REG); /* 16bit */ |
Marek Behún | e3183c6 | 2018-04-24 17:21:16 +0200 | [diff] [blame] | 256 | if (!ret) |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 257 | printf("Failed to lock PCIe PLL\n"); |
| 258 | |
| 259 | debug_exit(); |
| 260 | |
| 261 | /* Return the status of the PLL */ |
| 262 | return ret; |
| 263 | } |
| 264 | |
| 265 | /* |
Marek Behún | fbf651d | 2018-04-24 17:21:17 +0200 | [diff] [blame] | 266 | * reg_set_indirect |
| 267 | * |
| 268 | * return: void |
| 269 | */ |
| 270 | static void reg_set_indirect(u32 reg, u16 data, u16 mask) |
| 271 | { |
| 272 | reg_set(rh_vsreg_addr, reg, 0xFFFFFFFF); |
| 273 | reg_set(rh_vsreg_data, data, mask); |
| 274 | } |
| 275 | |
| 276 | /* |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 277 | * comphy_sata_power_up |
| 278 | * |
| 279 | * return: 1 if PLL locked (OK), 0 otherwise (FAIL) |
| 280 | */ |
zachary | ba42e84 | 2020-08-28 16:56:29 +0200 | [diff] [blame] | 281 | static int comphy_sata_power_up(u32 invert) |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 282 | { |
Marek Behún | fbf651d | 2018-04-24 17:21:17 +0200 | [diff] [blame] | 283 | int ret; |
zachary | ba42e84 | 2020-08-28 16:56:29 +0200 | [diff] [blame] | 284 | u32 data = 0; |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 285 | |
| 286 | debug_enter(); |
| 287 | |
| 288 | /* |
zachary | ba42e84 | 2020-08-28 16:56:29 +0200 | [diff] [blame] | 289 | * 0. Check the Polarity invert bits |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 290 | */ |
Igal Liberman | ffd5d2f | 2017-04-26 15:40:00 +0300 | [diff] [blame] | 291 | if (invert & COMPHY_POLARITY_TXD_INVERT) |
zachary | ba42e84 | 2020-08-28 16:56:29 +0200 | [diff] [blame] | 292 | data |= bs_txd_inv; |
| 293 | |
Igal Liberman | ffd5d2f | 2017-04-26 15:40:00 +0300 | [diff] [blame] | 294 | if (invert & COMPHY_POLARITY_RXD_INVERT) |
zachary | ba42e84 | 2020-08-28 16:56:29 +0200 | [diff] [blame] | 295 | data |= bs_rxd_inv; |
| 296 | |
| 297 | reg_set_indirect(vphy_sync_pattern_reg, data, bs_txd_inv | bs_rxd_inv); |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 298 | |
| 299 | /* |
| 300 | * 1. Select 40-bit data width width |
| 301 | */ |
Marek Behún | fbf651d | 2018-04-24 17:21:17 +0200 | [diff] [blame] | 302 | reg_set_indirect(vphy_loopback_reg0, 0x800, bs_phyintf_40bit); |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 303 | |
| 304 | /* |
| 305 | * 2. Select reference clock and PHY mode (SATA) |
| 306 | */ |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 307 | if (get_ref_clk() == 40) { |
Marek Behún | fbf651d | 2018-04-24 17:21:17 +0200 | [diff] [blame] | 308 | /* 40 MHz */ |
| 309 | reg_set_indirect(vphy_power_reg0, 0x3, 0x00FF); |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 310 | } else { |
Marek Behún | fbf651d | 2018-04-24 17:21:17 +0200 | [diff] [blame] | 311 | /* 20 MHz */ |
| 312 | reg_set_indirect(vphy_power_reg0, 0x1, 0x00FF); |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 313 | } |
| 314 | |
| 315 | /* |
| 316 | * 3. Use maximum PLL rate (no power save) |
| 317 | */ |
Marek Behún | fbf651d | 2018-04-24 17:21:17 +0200 | [diff] [blame] | 318 | reg_set_indirect(vphy_calctl_reg, bs_max_pll_rate, bs_max_pll_rate); |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 319 | |
| 320 | /* |
| 321 | * 4. Reset reserved bit (??) |
| 322 | */ |
Marek Behún | fbf651d | 2018-04-24 17:21:17 +0200 | [diff] [blame] | 323 | reg_set_indirect(vphy_reserve_reg, 0, bs_phyctrl_frm_pin); |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 324 | |
| 325 | /* |
| 326 | * 5. Set vendor-specific configuration (??) |
| 327 | */ |
Marek Behún | 4c02f73 | 2018-04-24 17:21:12 +0200 | [diff] [blame] | 328 | reg_set(rh_vs0_a, vsata_ctrl_reg, 0xFFFFFFFF); |
| 329 | reg_set(rh_vs0_d, bs_phy_pu_pll, bs_phy_pu_pll); |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 330 | |
| 331 | /* Wait for > 55 us to allow PLL be enabled */ |
| 332 | udelay(PLL_SET_DELAY_US); |
| 333 | |
| 334 | /* Assert SATA PLL enabled */ |
Marek Behún | 4c02f73 | 2018-04-24 17:21:12 +0200 | [diff] [blame] | 335 | reg_set(rh_vsreg_addr, vphy_loopback_reg0, 0xFFFFFFFF); |
| 336 | ret = comphy_poll_reg(rh_vsreg_data, /* address */ |
| 337 | bs_pll_ready_tx, /* value */ |
| 338 | bs_pll_ready_tx, /* mask */ |
Marek Behún | 4c02f73 | 2018-04-24 17:21:12 +0200 | [diff] [blame] | 339 | POLL_32B_REG); /* 32bit */ |
Marek Behún | e3183c6 | 2018-04-24 17:21:16 +0200 | [diff] [blame] | 340 | if (!ret) |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 341 | printf("Failed to lock SATA PLL\n"); |
| 342 | |
| 343 | debug_exit(); |
| 344 | |
| 345 | return ret; |
| 346 | } |
| 347 | |
| 348 | /* |
Marek Behún | ef6f36e | 2018-04-24 17:21:18 +0200 | [diff] [blame] | 349 | * usb3_reg_set16 |
| 350 | * |
| 351 | * return: void |
| 352 | */ |
| 353 | static void usb3_reg_set16(u32 reg, u16 data, u16 mask, u32 lane) |
| 354 | { |
| 355 | /* |
| 356 | * When Lane 2 PHY is for USB3, access the PHY registers |
| 357 | * through indirect Address and Data registers INDIR_ACC_PHY_ADDR |
| 358 | * (RD00E0178h [31:0]) and INDIR_ACC_PHY_DATA (RD00E017Ch [31:0]) |
| 359 | * within the SATA Host Controller registers, Lane 2 base register |
| 360 | * offset is 0x200 |
| 361 | */ |
| 362 | |
| 363 | if (lane == 2) |
| 364 | reg_set_indirect(USB3PHY_LANE2_REG_BASE_OFFSET + reg, data, |
| 365 | mask); |
| 366 | else |
| 367 | reg_set16(phy_addr(USB3, reg), data, mask); |
| 368 | } |
| 369 | |
| 370 | /* |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 371 | * comphy_usb3_power_up |
| 372 | * |
| 373 | * return: 1 if PLL locked (OK), 0 otherwise (FAIL) |
| 374 | */ |
Marek Behún | ef6f36e | 2018-04-24 17:21:18 +0200 | [diff] [blame] | 375 | static int comphy_usb3_power_up(u32 lane, u32 type, u32 speed, u32 invert) |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 376 | { |
Marek Behún | ef6f36e | 2018-04-24 17:21:18 +0200 | [diff] [blame] | 377 | int ret; |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 378 | |
| 379 | debug_enter(); |
| 380 | |
| 381 | /* |
| 382 | * 1. Power up OTG module |
| 383 | */ |
Marek Behún | 4c02f73 | 2018-04-24 17:21:12 +0200 | [diff] [blame] | 384 | reg_set(USB2_PHY_OTG_CTRL_ADDR, rb_pu_otg, 0); |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 385 | |
| 386 | /* |
| 387 | * 2. Set counter for 100us pulse in USB3 Host and Device |
| 388 | * restore default burst size limit (Reference Clock 31:24) |
| 389 | */ |
Marek Behún | 4c02f73 | 2018-04-24 17:21:12 +0200 | [diff] [blame] | 390 | reg_set(USB3_CTRPUL_VAL_REG, 0x8 << 24, rb_usb3_ctr_100ns); |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 391 | |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 392 | /* 0xd005c300 = 0x1001 */ |
| 393 | /* set PRD_TXDEEMPH (3.5db de-emph) */ |
Marek Behún | ef6f36e | 2018-04-24 17:21:18 +0200 | [diff] [blame] | 394 | usb3_reg_set16(LANE_CFG0, 0x1, 0xFF, lane); |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 395 | |
| 396 | /* |
zachary | 2684a39 | 2018-04-24 17:21:20 +0200 | [diff] [blame] | 397 | * Set BIT0: enable transmitter in high impedance mode |
| 398 | * Set BIT[3:4]: delay 2 clock cycles for HiZ off latency |
| 399 | * Set BIT6: Tx detect Rx at HiZ mode |
| 400 | * Unset BIT15: set to 0 to set USB3 De-emphasize level to -3.5db |
| 401 | * together with bit 0 of COMPHY_REG_LANE_CFG0_ADDR |
| 402 | * register |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 403 | */ |
zachary | 2684a39 | 2018-04-24 17:21:20 +0200 | [diff] [blame] | 404 | usb3_reg_set16(LANE_CFG1, |
| 405 | tx_det_rx_mode | gen2_tx_data_dly_deft |
| 406 | | tx_elec_idle_mode_en, |
| 407 | prd_txdeemph1_mask | tx_det_rx_mode |
| 408 | | gen2_tx_data_dly_mask | tx_elec_idle_mode_en, lane); |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 409 | |
Marek Behún | ef6f36e | 2018-04-24 17:21:18 +0200 | [diff] [blame] | 410 | /* 0xd005c310 = 0x93: set Spread Spectrum Clock Enabled */ |
| 411 | usb3_reg_set16(LANE_CFG4, bf_spread_spectrum_clock_en, 0x80, lane); |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 412 | |
| 413 | /* |
| 414 | * set Override Margining Controls From the MAC: Use margining signals |
| 415 | * from lane configuration |
| 416 | */ |
Marek Behún | ef6f36e | 2018-04-24 17:21:18 +0200 | [diff] [blame] | 417 | usb3_reg_set16(TEST_MODE_CTRL, rb_mode_margin_override, 0xFFFF, lane); |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 418 | |
| 419 | /* set Lane-to-Lane Bundle Clock Sampling Period = per PCLK cycles */ |
| 420 | /* set Mode Clock Source = PCLK is generated from REFCLK */ |
Marek Behún | ef6f36e | 2018-04-24 17:21:18 +0200 | [diff] [blame] | 421 | usb3_reg_set16(GLOB_CLK_SRC_LO, 0x0, 0xFF, lane); |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 422 | |
| 423 | /* set G2 Spread Spectrum Clock Amplitude at 4K */ |
Marek Behún | ef6f36e | 2018-04-24 17:21:18 +0200 | [diff] [blame] | 424 | usb3_reg_set16(GEN2_SETTINGS_2, g2_tx_ssc_amp, 0xF000, lane); |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 425 | |
| 426 | /* |
| 427 | * unset G3 Spread Spectrum Clock Amplitude & set G3 TX and RX Register |
| 428 | * Master Current Select |
| 429 | */ |
Marek Behún | ef6f36e | 2018-04-24 17:21:18 +0200 | [diff] [blame] | 430 | usb3_reg_set16(GEN2_SETTINGS_3, 0x0, 0xFFFF, lane); |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 431 | |
| 432 | /* |
| 433 | * 3. Check crystal jumper setting and program the Power and PLL |
| 434 | * Control accordingly |
Marek Behún | b3b7e21 | 2018-04-24 17:21:19 +0200 | [diff] [blame] | 435 | * 4. Change RX wait |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 436 | */ |
| 437 | if (get_ref_clk() == 40) { |
Marek Behún | a89ae13 | 2018-04-24 17:21:14 +0200 | [diff] [blame] | 438 | /* 40 MHz */ |
Marek Behún | ef6f36e | 2018-04-24 17:21:18 +0200 | [diff] [blame] | 439 | usb3_reg_set16(PWR_PLL_CTRL, 0xFCA3, 0xFFFF, lane); |
Marek Behún | b3b7e21 | 2018-04-24 17:21:19 +0200 | [diff] [blame] | 440 | usb3_reg_set16(PWR_MGM_TIM1, 0x10C, 0xFFFF, lane); |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 441 | } else { |
Marek Behún | a89ae13 | 2018-04-24 17:21:14 +0200 | [diff] [blame] | 442 | /* 25 MHz */ |
Marek Behún | ef6f36e | 2018-04-24 17:21:18 +0200 | [diff] [blame] | 443 | usb3_reg_set16(PWR_PLL_CTRL, 0xFCA2, 0xFFFF, lane); |
Marek Behún | b3b7e21 | 2018-04-24 17:21:19 +0200 | [diff] [blame] | 444 | usb3_reg_set16(PWR_MGM_TIM1, 0x107, 0xFFFF, lane); |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 445 | } |
| 446 | |
| 447 | /* |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 448 | * 5. Enable idle sync |
| 449 | */ |
Marek Behún | ef6f36e | 2018-04-24 17:21:18 +0200 | [diff] [blame] | 450 | usb3_reg_set16(UNIT_CTRL, 0x60 | rb_idle_sync_en, 0xFFFF, lane); |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 451 | |
| 452 | /* |
| 453 | * 6. Enable the output of 500M clock |
| 454 | */ |
Marek Behún | ef6f36e | 2018-04-24 17:21:18 +0200 | [diff] [blame] | 455 | usb3_reg_set16(MISC_REG0, 0xA00D | rb_clk500m_en, 0xFFFF, lane); |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 456 | |
| 457 | /* |
| 458 | * 7. Set 20-bit data width |
| 459 | */ |
Marek Behún | ef6f36e | 2018-04-24 17:21:18 +0200 | [diff] [blame] | 460 | usb3_reg_set16(DIG_LB_EN, 0x0400, 0xFFFF, lane); |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 461 | |
| 462 | /* |
| 463 | * 8. Override Speed_PLL value and use MAC PLL |
| 464 | */ |
Marek Behún | ef6f36e | 2018-04-24 17:21:18 +0200 | [diff] [blame] | 465 | usb3_reg_set16(KVCO_CAL_CTRL, 0x0040 | rb_use_max_pll_rate, 0xFFFF, |
| 466 | lane); |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 467 | |
| 468 | /* |
| 469 | * 9. Check the Polarity invert bit |
| 470 | */ |
Igal Liberman | ffd5d2f | 2017-04-26 15:40:00 +0300 | [diff] [blame] | 471 | if (invert & COMPHY_POLARITY_TXD_INVERT) |
Marek Behún | ef6f36e | 2018-04-24 17:21:18 +0200 | [diff] [blame] | 472 | usb3_reg_set16(SYNC_PATTERN, phy_txd_inv, 0, lane); |
Pali Rohár | 6148ea6 | 2021-09-24 16:11:56 +0200 | [diff] [blame] | 473 | else |
| 474 | usb3_reg_set16(SYNC_PATTERN, 0, phy_txd_inv, lane); |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 475 | |
Igal Liberman | ffd5d2f | 2017-04-26 15:40:00 +0300 | [diff] [blame] | 476 | if (invert & COMPHY_POLARITY_RXD_INVERT) |
Marek Behún | ef6f36e | 2018-04-24 17:21:18 +0200 | [diff] [blame] | 477 | usb3_reg_set16(SYNC_PATTERN, phy_rxd_inv, 0, lane); |
Pali Rohár | 6148ea6 | 2021-09-24 16:11:56 +0200 | [diff] [blame] | 478 | else |
| 479 | usb3_reg_set16(SYNC_PATTERN, 0, phy_rxd_inv, lane); |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 480 | |
| 481 | /* |
zachary | 2684a39 | 2018-04-24 17:21:20 +0200 | [diff] [blame] | 482 | * 10. Set max speed generation to USB3.0 5Gbps |
| 483 | */ |
| 484 | usb3_reg_set16(SYNC_MASK_GEN, 0x0400, 0x0C00, lane); |
| 485 | |
| 486 | /* |
| 487 | * 11. Set capacitor value for FFE gain peaking to 0xF |
| 488 | */ |
| 489 | usb3_reg_set16(GEN3_SETTINGS_3, 0xF, 0xF, lane); |
| 490 | |
| 491 | /* |
| 492 | * 12. Release SW reset |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 493 | */ |
Marek Behún | ef6f36e | 2018-04-24 17:21:18 +0200 | [diff] [blame] | 494 | usb3_reg_set16(GLOB_PHY_CTRL0, |
| 495 | rb_mode_core_clk_freq_sel | rb_mode_pipe_width_32 |
| 496 | | 0x20, 0xFFFF, lane); |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 497 | |
| 498 | /* Wait for > 55 us to allow PCLK be enabled */ |
| 499 | udelay(PLL_SET_DELAY_US); |
| 500 | |
| 501 | /* Assert PCLK enabled */ |
Marek Behún | ef6f36e | 2018-04-24 17:21:18 +0200 | [diff] [blame] | 502 | if (lane == 2) { |
| 503 | reg_set(rh_vsreg_addr, |
| 504 | LANE_STAT1 + USB3PHY_LANE2_REG_BASE_OFFSET, |
| 505 | 0xFFFFFFFF); |
| 506 | ret = comphy_poll_reg(rh_vsreg_data, /* address */ |
| 507 | rb_txdclk_pclk_en, /* value */ |
| 508 | rb_txdclk_pclk_en, /* mask */ |
| 509 | POLL_32B_REG); /* 32bit */ |
| 510 | } else { |
| 511 | ret = comphy_poll_reg(phy_addr(USB3, LANE_STAT1), /* address */ |
| 512 | rb_txdclk_pclk_en, /* value */ |
| 513 | rb_txdclk_pclk_en, /* mask */ |
| 514 | POLL_16B_REG); /* 16bit */ |
| 515 | } |
Marek Behún | e3183c6 | 2018-04-24 17:21:16 +0200 | [diff] [blame] | 516 | if (!ret) |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 517 | printf("Failed to lock USB3 PLL\n"); |
| 518 | |
| 519 | /* |
| 520 | * Set Soft ID for Host mode (Device mode works with Hard ID |
| 521 | * detection) |
| 522 | */ |
Igal Liberman | ffd5d2f | 2017-04-26 15:40:00 +0300 | [diff] [blame] | 523 | if (type == COMPHY_TYPE_USB3_HOST0) { |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 524 | /* |
| 525 | * set BIT0: set ID_MODE of Host/Device = "Soft ID" (BIT1) |
| 526 | * clear BIT1: set SOFT_ID = Host |
| 527 | * set BIT4: set INT_MODE = ID. Interrupt Mode: enable |
| 528 | * interrupt by ID instead of using both interrupts |
| 529 | * of HOST and Device ORed simultaneously |
| 530 | * INT_MODE=ID in order to avoid unexpected |
| 531 | * behaviour or both interrupts together |
| 532 | */ |
Marek Behún | 4c02f73 | 2018-04-24 17:21:12 +0200 | [diff] [blame] | 533 | reg_set(USB32_CTRL_BASE, |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 534 | usb32_ctrl_id_mode | usb32_ctrl_int_mode, |
| 535 | usb32_ctrl_id_mode | usb32_ctrl_soft_id | |
| 536 | usb32_ctrl_int_mode); |
| 537 | } |
| 538 | |
| 539 | debug_exit(); |
| 540 | |
| 541 | return ret; |
| 542 | } |
| 543 | |
| 544 | /* |
| 545 | * comphy_usb2_power_up |
| 546 | * |
| 547 | * return: 1 if PLL locked (OK), 0 otherwise (FAIL) |
| 548 | */ |
| 549 | static int comphy_usb2_power_up(u8 usb32) |
| 550 | { |
Marek Behún | ef6f36e | 2018-04-24 17:21:18 +0200 | [diff] [blame] | 551 | int ret; |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 552 | |
| 553 | debug_enter(); |
| 554 | |
| 555 | if (usb32 != 0 && usb32 != 1) { |
| 556 | printf("invalid usb32 value: (%d), should be either 0 or 1\n", |
| 557 | usb32); |
| 558 | debug_exit(); |
| 559 | return 0; |
| 560 | } |
| 561 | |
| 562 | /* |
| 563 | * 0. Setup PLL. 40MHz clock uses defaults. |
| 564 | * See "PLL Settings for Typical REFCLK" table |
| 565 | */ |
| 566 | if (get_ref_clk() == 25) { |
Marek Behún | 4c02f73 | 2018-04-24 17:21:12 +0200 | [diff] [blame] | 567 | reg_set(USB2_PHY_BASE(usb32), 5 | (96 << 16), |
| 568 | 0x3F | (0xFF << 16) | (0x3 << 28)); |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 569 | } |
| 570 | |
| 571 | /* |
| 572 | * 1. PHY pull up and disable USB2 suspend |
| 573 | */ |
Marek Behún | 4c02f73 | 2018-04-24 17:21:12 +0200 | [diff] [blame] | 574 | reg_set(USB2_PHY_CTRL_ADDR(usb32), |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 575 | RB_USB2PHY_SUSPM(usb32) | RB_USB2PHY_PU(usb32), 0); |
| 576 | |
| 577 | if (usb32 != 0) { |
| 578 | /* |
| 579 | * 2. Power up OTG module |
| 580 | */ |
Marek Behún | 4c02f73 | 2018-04-24 17:21:12 +0200 | [diff] [blame] | 581 | reg_set(USB2_PHY_OTG_CTRL_ADDR, rb_pu_otg, 0); |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 582 | |
| 583 | /* |
| 584 | * 3. Configure PHY charger detection |
| 585 | */ |
Marek Behún | 4c02f73 | 2018-04-24 17:21:12 +0200 | [diff] [blame] | 586 | reg_set(USB2_PHY_CHRGR_DET_ADDR, 0, |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 587 | rb_cdp_en | rb_dcp_en | rb_pd_en | rb_cdp_dm_auto | |
| 588 | rb_enswitch_dp | rb_enswitch_dm | rb_pu_chrg_dtc); |
| 589 | } |
| 590 | |
| 591 | /* Assert PLL calibration done */ |
Marek Behún | 4c02f73 | 2018-04-24 17:21:12 +0200 | [diff] [blame] | 592 | ret = comphy_poll_reg(USB2_PHY_CAL_CTRL_ADDR(usb32), |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 593 | rb_usb2phy_pllcal_done, /* value */ |
| 594 | rb_usb2phy_pllcal_done, /* mask */ |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 595 | POLL_32B_REG); /* 32bit */ |
Pali Rohár | 1f72093 | 2021-09-24 16:11:57 +0200 | [diff] [blame] | 596 | if (!ret) { |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 597 | printf("Failed to end USB2 PLL calibration\n"); |
Pali Rohár | 1f72093 | 2021-09-24 16:11:57 +0200 | [diff] [blame] | 598 | goto out; |
| 599 | } |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 600 | |
| 601 | /* Assert impedance calibration done */ |
Marek Behún | 4c02f73 | 2018-04-24 17:21:12 +0200 | [diff] [blame] | 602 | ret = comphy_poll_reg(USB2_PHY_CAL_CTRL_ADDR(usb32), |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 603 | rb_usb2phy_impcal_done, /* value */ |
| 604 | rb_usb2phy_impcal_done, /* mask */ |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 605 | POLL_32B_REG); /* 32bit */ |
Pali Rohár | 1f72093 | 2021-09-24 16:11:57 +0200 | [diff] [blame] | 606 | if (!ret) { |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 607 | printf("Failed to end USB2 impedance calibration\n"); |
Pali Rohár | 1f72093 | 2021-09-24 16:11:57 +0200 | [diff] [blame] | 608 | goto out; |
| 609 | } |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 610 | |
| 611 | /* Assert squetch calibration done */ |
Marek Behún | 4c02f73 | 2018-04-24 17:21:12 +0200 | [diff] [blame] | 612 | ret = comphy_poll_reg(USB2_PHY_RX_CHAN_CTRL1_ADDR(usb32), |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 613 | rb_usb2phy_sqcal_done, /* value */ |
| 614 | rb_usb2phy_sqcal_done, /* mask */ |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 615 | POLL_32B_REG); /* 32bit */ |
Pali Rohár | 1f72093 | 2021-09-24 16:11:57 +0200 | [diff] [blame] | 616 | if (!ret) { |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 617 | printf("Failed to end USB2 unknown calibration\n"); |
Pali Rohár | 1f72093 | 2021-09-24 16:11:57 +0200 | [diff] [blame] | 618 | goto out; |
| 619 | } |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 620 | |
| 621 | /* Assert PLL is ready */ |
Marek Behún | 4c02f73 | 2018-04-24 17:21:12 +0200 | [diff] [blame] | 622 | ret = comphy_poll_reg(USB2_PHY_PLL_CTRL0_ADDR(usb32), |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 623 | rb_usb2phy_pll_ready, /* value */ |
| 624 | rb_usb2phy_pll_ready, /* mask */ |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 625 | POLL_32B_REG); /* 32bit */ |
| 626 | |
Pali Rohár | 1f72093 | 2021-09-24 16:11:57 +0200 | [diff] [blame] | 627 | if (!ret) { |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 628 | printf("Failed to lock USB2 PLL\n"); |
Pali Rohár | 1f72093 | 2021-09-24 16:11:57 +0200 | [diff] [blame] | 629 | goto out; |
| 630 | } |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 631 | |
Pali Rohár | 1f72093 | 2021-09-24 16:11:57 +0200 | [diff] [blame] | 632 | out: |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 633 | debug_exit(); |
| 634 | |
| 635 | return ret; |
| 636 | } |
| 637 | |
| 638 | /* |
| 639 | * comphy_emmc_power_up |
| 640 | * |
| 641 | * return: 1 if PLL locked (OK), 0 otherwise (FAIL) |
| 642 | */ |
| 643 | static int comphy_emmc_power_up(void) |
| 644 | { |
| 645 | debug_enter(); |
| 646 | |
| 647 | /* |
| 648 | * 1. Bus power ON, Bus voltage 1.8V |
| 649 | */ |
Marek Behún | 4c02f73 | 2018-04-24 17:21:12 +0200 | [diff] [blame] | 650 | reg_set(SDIO_HOST_CTRL1_ADDR, 0xB00, 0xF00); |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 651 | |
| 652 | /* |
| 653 | * 2. Set FIFO parameters |
| 654 | */ |
Marek Behún | 4c02f73 | 2018-04-24 17:21:12 +0200 | [diff] [blame] | 655 | reg_set(SDIO_SDHC_FIFO_ADDR, 0x315, 0xFFFFFFFF); |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 656 | |
| 657 | /* |
| 658 | * 3. Set Capabilities 1_2 |
| 659 | */ |
Marek Behún | 4c02f73 | 2018-04-24 17:21:12 +0200 | [diff] [blame] | 660 | reg_set(SDIO_CAP_12_ADDR, 0x25FAC8B2, 0xFFFFFFFF); |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 661 | |
| 662 | /* |
| 663 | * 4. Set Endian |
| 664 | */ |
Marek Behún | 4c02f73 | 2018-04-24 17:21:12 +0200 | [diff] [blame] | 665 | reg_set(SDIO_ENDIAN_ADDR, 0x00c00000, 0); |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 666 | |
| 667 | /* |
| 668 | * 4. Init PHY |
| 669 | */ |
Marek Behún | 4c02f73 | 2018-04-24 17:21:12 +0200 | [diff] [blame] | 670 | reg_set(SDIO_PHY_TIMING_ADDR, 0x80000000, 0x80000000); |
| 671 | reg_set(SDIO_PHY_PAD_CTRL0_ADDR, 0x50000000, 0xF0000000); |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 672 | |
| 673 | /* |
| 674 | * 5. DLL reset |
| 675 | */ |
Marek Behún | 4c02f73 | 2018-04-24 17:21:12 +0200 | [diff] [blame] | 676 | reg_set(SDIO_DLL_RST_ADDR, 0xFFFEFFFF, 0); |
| 677 | reg_set(SDIO_DLL_RST_ADDR, 0x00010000, 0); |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 678 | |
| 679 | debug_exit(); |
| 680 | |
| 681 | return 1; |
| 682 | } |
| 683 | |
| 684 | /* |
| 685 | * comphy_sgmii_power_up |
| 686 | * |
| 687 | * return: |
| 688 | */ |
| 689 | static void comphy_sgmii_phy_init(u32 lane, u32 speed) |
| 690 | { |
| 691 | const int fix_arr_sz = ARRAY_SIZE(sgmii_phy_init_fix); |
| 692 | int addr, fix_idx; |
| 693 | u16 val; |
| 694 | |
| 695 | fix_idx = 0; |
| 696 | for (addr = 0; addr < 512; addr++) { |
| 697 | /* |
| 698 | * All PHY register values are defined in full for 3.125Gbps |
| 699 | * SERDES speed. The values required for 1.25 Gbps are almost |
| 700 | * the same and only few registers should be "fixed" in |
| 701 | * comparison to 3.125 Gbps values. These register values are |
| 702 | * stored in "sgmii_phy_init_fix" array. |
| 703 | */ |
Igal Liberman | ffd5d2f | 2017-04-26 15:40:00 +0300 | [diff] [blame] | 704 | if (speed != COMPHY_SPEED_1_25G && |
| 705 | sgmii_phy_init_fix[fix_idx].addr == addr) { |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 706 | /* Use new value */ |
| 707 | val = sgmii_phy_init_fix[fix_idx].value; |
| 708 | if (fix_idx < fix_arr_sz) |
| 709 | fix_idx++; |
| 710 | } else { |
| 711 | val = sgmii_phy_init[addr]; |
| 712 | } |
| 713 | |
Marek Behún | ee3e2f6 | 2018-04-24 17:21:13 +0200 | [diff] [blame] | 714 | reg_set16(sgmiiphy_addr(lane, addr), val, 0xFFFF); |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 715 | } |
| 716 | } |
| 717 | |
| 718 | /* |
| 719 | * comphy_sgmii_power_up |
| 720 | * |
| 721 | * return: 1 if PLL locked (OK), 0 otherwise (FAIL) |
| 722 | */ |
| 723 | static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert) |
| 724 | { |
Marek Behún | ef6f36e | 2018-04-24 17:21:18 +0200 | [diff] [blame] | 725 | int ret; |
Marek Behún | 3c340ed | 2018-04-24 17:21:24 +0200 | [diff] [blame] | 726 | u32 saved_selector; |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 727 | |
| 728 | debug_enter(); |
| 729 | |
| 730 | /* |
| 731 | * 1. Configure PHY to SATA/SAS mode by setting pin PIN_PIPE_SEL=0 |
| 732 | */ |
Marek Behún | 3c340ed | 2018-04-24 17:21:24 +0200 | [diff] [blame] | 733 | saved_selector = readl(COMPHY_SEL_ADDR); |
| 734 | reg_set(COMPHY_SEL_ADDR, 0, 0xFFFFFFFF); |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 735 | |
| 736 | /* |
| 737 | * 2. Reset PHY by setting PHY input port PIN_RESET=1. |
| 738 | * 3. Set PHY input port PIN_TX_IDLE=1, PIN_PU_IVREF=1 to keep |
| 739 | * PHY TXP/TXN output to idle state during PHY initialization |
| 740 | * 4. Set PHY input port PIN_PU_PLL=0, PIN_PU_RX=0, PIN_PU_TX=0. |
| 741 | */ |
Marek Behún | 4c02f73 | 2018-04-24 17:21:12 +0200 | [diff] [blame] | 742 | reg_set(COMPHY_PHY_CFG1_ADDR(lane), |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 743 | rb_pin_reset_comphy | rb_pin_tx_idle | rb_pin_pu_iveref, |
| 744 | rb_pin_reset_core | rb_pin_pu_pll | |
| 745 | rb_pin_pu_rx | rb_pin_pu_tx); |
| 746 | |
| 747 | /* |
| 748 | * 5. Release reset to the PHY by setting PIN_RESET=0. |
| 749 | */ |
Marek Behún | 4c02f73 | 2018-04-24 17:21:12 +0200 | [diff] [blame] | 750 | reg_set(COMPHY_PHY_CFG1_ADDR(lane), 0, rb_pin_reset_comphy); |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 751 | |
| 752 | /* |
| 753 | * 7. Set PIN_PHY_GEN_TX[3:0] and PIN_PHY_GEN_RX[3:0] to decide |
| 754 | * COMPHY bit rate |
| 755 | */ |
Igal Liberman | ffd5d2f | 2017-04-26 15:40:00 +0300 | [diff] [blame] | 756 | if (speed == COMPHY_SPEED_3_125G) { /* 3.125 GHz */ |
Marek Behún | 4c02f73 | 2018-04-24 17:21:12 +0200 | [diff] [blame] | 757 | reg_set(COMPHY_PHY_CFG1_ADDR(lane), |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 758 | (0x8 << rf_gen_rx_sel_shift) | |
| 759 | (0x8 << rf_gen_tx_sel_shift), |
| 760 | rf_gen_rx_select | rf_gen_tx_select); |
| 761 | |
Igal Liberman | ffd5d2f | 2017-04-26 15:40:00 +0300 | [diff] [blame] | 762 | } else if (speed == COMPHY_SPEED_1_25G) { /* 1.25 GHz */ |
Marek Behún | 4c02f73 | 2018-04-24 17:21:12 +0200 | [diff] [blame] | 763 | reg_set(COMPHY_PHY_CFG1_ADDR(lane), |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 764 | (0x6 << rf_gen_rx_sel_shift) | |
| 765 | (0x6 << rf_gen_tx_sel_shift), |
| 766 | rf_gen_rx_select | rf_gen_tx_select); |
| 767 | } else { |
| 768 | printf("Unsupported COMPHY speed!\n"); |
| 769 | return 0; |
| 770 | } |
| 771 | |
| 772 | /* |
| 773 | * 8. Wait 1mS for bandgap and reference clocks to stabilize; |
| 774 | * then start SW programming. |
| 775 | */ |
| 776 | mdelay(10); |
| 777 | |
| 778 | /* 9. Program COMPHY register PHY_MODE */ |
Marek Behún | a89ae13 | 2018-04-24 17:21:14 +0200 | [diff] [blame] | 779 | reg_set16(sgmiiphy_addr(lane, PWR_PLL_CTRL), |
Marek Behún | ee3e2f6 | 2018-04-24 17:21:13 +0200 | [diff] [blame] | 780 | PHY_MODE_SGMII << rf_phy_mode_shift, rf_phy_mode_mask); |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 781 | |
| 782 | /* |
| 783 | * 10. Set COMPHY register REFCLK_SEL to select the correct REFCLK |
| 784 | * source |
| 785 | */ |
Marek Behún | a89ae13 | 2018-04-24 17:21:14 +0200 | [diff] [blame] | 786 | reg_set16(sgmiiphy_addr(lane, MISC_REG0), 0, rb_ref_clk_sel); |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 787 | |
| 788 | /* |
| 789 | * 11. Set correct reference clock frequency in COMPHY register |
| 790 | * REF_FREF_SEL. |
| 791 | */ |
| 792 | if (get_ref_clk() == 40) { |
Marek Behún | a89ae13 | 2018-04-24 17:21:14 +0200 | [diff] [blame] | 793 | reg_set16(sgmiiphy_addr(lane, PWR_PLL_CTRL), |
Marek Behún | ee3e2f6 | 2018-04-24 17:21:13 +0200 | [diff] [blame] | 794 | 0x4 << rf_ref_freq_sel_shift, rf_ref_freq_sel_mask); |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 795 | } else { |
| 796 | /* 25MHz */ |
Marek Behún | a89ae13 | 2018-04-24 17:21:14 +0200 | [diff] [blame] | 797 | reg_set16(sgmiiphy_addr(lane, PWR_PLL_CTRL), |
Marek Behún | ee3e2f6 | 2018-04-24 17:21:13 +0200 | [diff] [blame] | 798 | 0x1 << rf_ref_freq_sel_shift, rf_ref_freq_sel_mask); |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 799 | } |
| 800 | |
| 801 | /* 12. Program COMPHY register PHY_GEN_MAX[1:0] */ |
| 802 | /* |
| 803 | * This step is mentioned in the flow received from verification team. |
| 804 | * However the PHY_GEN_MAX value is only meaningful for other |
| 805 | * interfaces (not SGMII). For instance, it selects SATA speed |
| 806 | * 1.5/3/6 Gbps or PCIe speed 2.5/5 Gbps |
| 807 | */ |
| 808 | |
| 809 | /* |
| 810 | * 13. Program COMPHY register SEL_BITS to set correct parallel data |
| 811 | * bus width |
| 812 | */ |
| 813 | /* 10bit */ |
Marek Behún | a89ae13 | 2018-04-24 17:21:14 +0200 | [diff] [blame] | 814 | reg_set16(sgmiiphy_addr(lane, DIG_LB_EN), 0, rf_data_width_mask); |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 815 | |
| 816 | /* |
| 817 | * 14. As long as DFE function needs to be enabled in any mode, |
| 818 | * COMPHY register DFE_UPDATE_EN[5:0] shall be programmed to 0x3F |
| 819 | * for real chip during COMPHY power on. |
| 820 | */ |
| 821 | /* |
| 822 | * The step 14 exists (and empty) in the original initialization flow |
| 823 | * obtained from the verification team. According to the functional |
| 824 | * specification DFE_UPDATE_EN already has the default value 0x3F |
| 825 | */ |
| 826 | |
| 827 | /* |
| 828 | * 15. Program COMPHY GEN registers. |
| 829 | * These registers should be programmed based on the lab testing |
| 830 | * result to achieve optimal performance. Please contact the CEA |
| 831 | * group to get the related GEN table during real chip bring-up. |
| 832 | * We only requred to run though the entire registers programming |
| 833 | * flow defined by "comphy_sgmii_phy_init" when the REF clock is |
| 834 | * 40 MHz. For REF clock 25 MHz the default values stored in PHY |
| 835 | * registers are OK. |
| 836 | */ |
| 837 | debug("Running C-DPI phy init %s mode\n", |
Igal Liberman | ffd5d2f | 2017-04-26 15:40:00 +0300 | [diff] [blame] | 838 | speed == COMPHY_SPEED_3_125G ? "2G5" : "1G"); |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 839 | if (get_ref_clk() == 40) |
| 840 | comphy_sgmii_phy_init(lane, speed); |
| 841 | |
| 842 | /* |
| 843 | * 16. [Simulation Only] should not be used for real chip. |
| 844 | * By pass power up calibration by programming EXT_FORCE_CAL_DONE |
| 845 | * (R02h[9]) to 1 to shorten COMPHY simulation time. |
| 846 | */ |
| 847 | /* |
| 848 | * 17. [Simulation Only: should not be used for real chip] |
| 849 | * Program COMPHY register FAST_DFE_TIMER_EN=1 to shorten RX |
| 850 | * training simulation time. |
| 851 | */ |
| 852 | |
| 853 | /* |
| 854 | * 18. Check the PHY Polarity invert bit |
| 855 | */ |
Igal Liberman | ffd5d2f | 2017-04-26 15:40:00 +0300 | [diff] [blame] | 856 | if (invert & COMPHY_POLARITY_TXD_INVERT) |
Marek Behún | a89ae13 | 2018-04-24 17:21:14 +0200 | [diff] [blame] | 857 | reg_set16(sgmiiphy_addr(lane, SYNC_PATTERN), phy_txd_inv, 0); |
Pali Rohár | 6148ea6 | 2021-09-24 16:11:56 +0200 | [diff] [blame] | 858 | else |
| 859 | reg_set16(sgmiiphy_addr(lane, SYNC_PATTERN), 0, phy_txd_inv); |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 860 | |
Igal Liberman | ffd5d2f | 2017-04-26 15:40:00 +0300 | [diff] [blame] | 861 | if (invert & COMPHY_POLARITY_RXD_INVERT) |
Marek Behún | a89ae13 | 2018-04-24 17:21:14 +0200 | [diff] [blame] | 862 | reg_set16(sgmiiphy_addr(lane, SYNC_PATTERN), phy_rxd_inv, 0); |
Pali Rohár | 6148ea6 | 2021-09-24 16:11:56 +0200 | [diff] [blame] | 863 | else |
| 864 | reg_set16(sgmiiphy_addr(lane, SYNC_PATTERN), 0, phy_rxd_inv); |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 865 | |
| 866 | /* |
| 867 | * 19. Set PHY input ports PIN_PU_PLL, PIN_PU_TX and PIN_PU_RX to 1 |
| 868 | * to start PHY power up sequence. All the PHY register |
| 869 | * programming should be done before PIN_PU_PLL=1. There should be |
| 870 | * no register programming for normal PHY operation from this point. |
| 871 | */ |
Marek Behún | 4c02f73 | 2018-04-24 17:21:12 +0200 | [diff] [blame] | 872 | reg_set(COMPHY_PHY_CFG1_ADDR(lane), |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 873 | rb_pin_pu_pll | rb_pin_pu_rx | rb_pin_pu_tx, |
| 874 | rb_pin_pu_pll | rb_pin_pu_rx | rb_pin_pu_tx); |
| 875 | |
| 876 | /* |
| 877 | * 20. Wait for PHY power up sequence to finish by checking output ports |
| 878 | * PIN_PLL_READY_TX=1 and PIN_PLL_READY_RX=1. |
| 879 | */ |
Marek Behún | 4c02f73 | 2018-04-24 17:21:12 +0200 | [diff] [blame] | 880 | ret = comphy_poll_reg(COMPHY_PHY_STAT1_ADDR(lane), /* address */ |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 881 | rb_pll_ready_tx | rb_pll_ready_rx, /* value */ |
| 882 | rb_pll_ready_tx | rb_pll_ready_rx, /* mask */ |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 883 | POLL_32B_REG); /* 32bit */ |
Pali Rohár | 1f72093 | 2021-09-24 16:11:57 +0200 | [diff] [blame] | 884 | if (!ret) { |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 885 | printf("Failed to lock PLL for SGMII PHY %d\n", lane); |
Pali Rohár | 1f72093 | 2021-09-24 16:11:57 +0200 | [diff] [blame] | 886 | goto out; |
| 887 | } |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 888 | |
| 889 | /* |
| 890 | * 21. Set COMPHY input port PIN_TX_IDLE=0 |
| 891 | */ |
Marek Behún | 4c02f73 | 2018-04-24 17:21:12 +0200 | [diff] [blame] | 892 | reg_set(COMPHY_PHY_CFG1_ADDR(lane), 0x0, rb_pin_tx_idle); |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 893 | |
| 894 | /* |
| 895 | * 22. After valid data appear on PIN_RXDATA bus, set PIN_RX_INIT=1. |
| 896 | * to start RX initialization. PIN_RX_INIT_DONE will be cleared to |
| 897 | * 0 by the PHY. After RX initialization is done, PIN_RX_INIT_DONE |
| 898 | * will be set to 1 by COMPHY. Set PIN_RX_INIT=0 after |
| 899 | * PIN_RX_INIT_DONE= 1. |
| 900 | * Please refer to RX initialization part for details. |
| 901 | */ |
Marek Behún | 4c02f73 | 2018-04-24 17:21:12 +0200 | [diff] [blame] | 902 | reg_set(COMPHY_PHY_CFG1_ADDR(lane), rb_phy_rx_init, 0x0); |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 903 | |
Marek Behún | 4c02f73 | 2018-04-24 17:21:12 +0200 | [diff] [blame] | 904 | ret = comphy_poll_reg(COMPHY_PHY_STAT1_ADDR(lane), /* address */ |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 905 | rb_rx_init_done, /* value */ |
| 906 | rb_rx_init_done, /* mask */ |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 907 | POLL_32B_REG); /* 32bit */ |
Pali Rohár | 1f72093 | 2021-09-24 16:11:57 +0200 | [diff] [blame] | 908 | if (!ret) { |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 909 | printf("Failed to init RX of SGMII PHY %d\n", lane); |
Pali Rohár | 1f72093 | 2021-09-24 16:11:57 +0200 | [diff] [blame] | 910 | goto out; |
| 911 | } |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 912 | |
Marek Behún | 3c340ed | 2018-04-24 17:21:24 +0200 | [diff] [blame] | 913 | /* |
| 914 | * Restore saved selector. |
| 915 | */ |
| 916 | reg_set(COMPHY_SEL_ADDR, saved_selector, 0xFFFFFFFF); |
| 917 | |
Pali Rohár | 1f72093 | 2021-09-24 16:11:57 +0200 | [diff] [blame] | 918 | out: |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 919 | debug_exit(); |
| 920 | |
| 921 | return ret; |
| 922 | } |
| 923 | |
| 924 | void comphy_dedicated_phys_init(void) |
| 925 | { |
| 926 | int node, usb32, ret = 1; |
| 927 | const void *blob = gd->fdt_blob; |
| 928 | |
| 929 | debug_enter(); |
| 930 | |
| 931 | for (usb32 = 0; usb32 <= 1; usb32++) { |
| 932 | /* |
| 933 | * There are 2 UTMI PHYs in this SOC. |
| 934 | * One is independendent and one is paired with USB3 port (OTG) |
| 935 | */ |
| 936 | if (usb32 == 0) { |
| 937 | node = fdt_node_offset_by_compatible( |
Pali Rohár | ecdc7bf | 2022-02-14 11:34:24 +0100 | [diff] [blame] | 938 | blob, -1, "marvell,armada-3700-ehci"); |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 939 | } else { |
| 940 | node = fdt_node_offset_by_compatible( |
| 941 | blob, -1, "marvell,armada3700-xhci"); |
| 942 | } |
| 943 | |
| 944 | if (node > 0) { |
| 945 | if (fdtdec_get_is_enabled(blob, node)) { |
| 946 | ret = comphy_usb2_power_up(usb32); |
Marek Behún | e3183c6 | 2018-04-24 17:21:16 +0200 | [diff] [blame] | 947 | if (!ret) |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 948 | printf("Failed to initialize UTMI PHY\n"); |
| 949 | else |
| 950 | debug("UTMI PHY init succeed\n"); |
| 951 | } else { |
| 952 | debug("USB%d node is disabled\n", |
| 953 | usb32 == 0 ? 2 : 3); |
| 954 | } |
| 955 | } else { |
| 956 | debug("No USB%d node in DT\n", usb32 == 0 ? 2 : 3); |
| 957 | } |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 958 | } |
| 959 | |
| 960 | node = fdt_node_offset_by_compatible(blob, -1, |
Stefan Roese | 86928bf | 2017-01-12 16:37:49 +0100 | [diff] [blame] | 961 | "marvell,armada-8k-sdhci"); |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 962 | if (node <= 0) { |
Stefan Roese | 86928bf | 2017-01-12 16:37:49 +0100 | [diff] [blame] | 963 | node = fdt_node_offset_by_compatible( |
| 964 | blob, -1, "marvell,armada-3700-sdhci"); |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 965 | } |
| 966 | |
| 967 | if (node > 0) { |
| 968 | if (fdtdec_get_is_enabled(blob, node)) { |
| 969 | ret = comphy_emmc_power_up(); |
Marek Behún | e3183c6 | 2018-04-24 17:21:16 +0200 | [diff] [blame] | 970 | if (!ret) |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 971 | printf("Failed to initialize SDIO/eMMC PHY\n"); |
| 972 | else |
| 973 | debug("SDIO/eMMC PHY init succeed\n"); |
| 974 | } else { |
| 975 | debug("SDIO/eMMC node is disabled\n"); |
| 976 | } |
| 977 | } else { |
| 978 | debug("No SDIO/eMMC node in DT\n"); |
| 979 | } |
| 980 | |
| 981 | debug_exit(); |
| 982 | } |
| 983 | |
Pali Rohár | 04c9347 | 2021-11-26 14:57:13 +0100 | [diff] [blame] | 984 | static int find_available_node_by_compatible(int offset, const char *compatible) |
| 985 | { |
Marek Behún | 5d6b448 | 2022-01-20 01:04:42 +0100 | [diff] [blame] | 986 | fdt_for_each_node_by_compatible(offset, gd->fdt_blob, offset, |
| 987 | compatible) |
| 988 | if (fdtdec_get_is_enabled(gd->fdt_blob, offset)) |
| 989 | return offset; |
Pali Rohár | 04c9347 | 2021-11-26 14:57:13 +0100 | [diff] [blame] | 990 | |
Marek Behún | 5d6b448 | 2022-01-20 01:04:42 +0100 | [diff] [blame] | 991 | return -1; |
Pali Rohár | 04c9347 | 2021-11-26 14:57:13 +0100 | [diff] [blame] | 992 | } |
| 993 | |
| 994 | static bool comphy_a3700_find_lane(const int nodes[3], int node, |
| 995 | int port, int *lane, int *invert) |
| 996 | { |
| 997 | int res, i, j; |
| 998 | |
| 999 | for (i = 0; ; i++) { |
| 1000 | struct fdtdec_phandle_args args; |
| 1001 | |
| 1002 | res = fdtdec_parse_phandle_with_args(gd->fdt_blob, node, "phys", |
| 1003 | "#phy-cells", 0, i, &args); |
| 1004 | if (res) |
| 1005 | return false; |
| 1006 | |
| 1007 | for (j = 0; j < 3; j++) { |
| 1008 | if (nodes[j] >= 0 && args.node == nodes[j] && |
| 1009 | (args.args_count >= 1 ? args.args[0] : 0) == port) { |
| 1010 | *lane = j; |
| 1011 | *invert = args.args_count >= 2 ? args.args[1] |
| 1012 | : 0; |
| 1013 | return true; |
| 1014 | } |
| 1015 | } |
| 1016 | } |
| 1017 | |
| 1018 | return false; |
| 1019 | } |
| 1020 | |
| 1021 | static void comphy_a3700_fill_cfg(struct chip_serdes_phy_config *cfg, |
| 1022 | const int nodes[3], const char *compatible, |
| 1023 | int type) |
| 1024 | { |
| 1025 | int node, lane, port, speed, invert; |
| 1026 | |
| 1027 | port = (type == COMPHY_TYPE_SGMII1) ? 1 : 0; |
| 1028 | |
| 1029 | node = -1; |
| 1030 | while (1) { |
| 1031 | node = find_available_node_by_compatible(node, compatible); |
| 1032 | if (node < 0) |
| 1033 | return; |
| 1034 | |
| 1035 | if (comphy_a3700_find_lane(nodes, node, port, &lane, &invert)) |
| 1036 | break; |
| 1037 | } |
| 1038 | |
| 1039 | if (cfg->comphy_map_data[lane].type != COMPHY_TYPE_UNCONNECTED) { |
| 1040 | printf("Error: More PHYs defined for lane %d, skipping\n", |
| 1041 | lane); |
| 1042 | return; |
| 1043 | } |
| 1044 | |
| 1045 | if (type == COMPHY_TYPE_SGMII0 || type == COMPHY_TYPE_SGMII1) { |
| 1046 | const char *phy_mode; |
| 1047 | |
| 1048 | phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL); |
| 1049 | if (phy_mode && |
| 1050 | !strcmp(phy_mode, |
| 1051 | phy_string_for_interface(PHY_INTERFACE_MODE_2500BASEX))) |
| 1052 | speed = COMPHY_SPEED_3_125G; |
| 1053 | else |
| 1054 | speed = COMPHY_SPEED_1_25G; |
| 1055 | } else if (type == COMPHY_TYPE_SATA0) { |
| 1056 | speed = COMPHY_SPEED_6G; |
| 1057 | } else { |
| 1058 | speed = COMPHY_SPEED_5G; |
| 1059 | } |
| 1060 | |
| 1061 | cfg->comphy_map_data[lane].type = type; |
| 1062 | cfg->comphy_map_data[lane].speed = speed; |
| 1063 | cfg->comphy_map_data[lane].invert = invert; |
| 1064 | } |
| 1065 | |
| 1066 | static const fdt32_t comphy_a3700_mux_lane_order[3] = { |
| 1067 | __constant_cpu_to_be32(1), |
| 1068 | __constant_cpu_to_be32(0), |
| 1069 | __constant_cpu_to_be32(2), |
| 1070 | }; |
| 1071 | |
| 1072 | int comphy_a3700_init_serdes_map(int node, struct chip_serdes_phy_config *cfg) |
| 1073 | { |
| 1074 | int comphy_nodes[3]; |
| 1075 | int child, i; |
| 1076 | |
| 1077 | for (i = 0; i < ARRAY_SIZE(comphy_nodes); i++) |
| 1078 | comphy_nodes[i] = -FDT_ERR_NOTFOUND; |
| 1079 | |
| 1080 | fdt_for_each_subnode(child, gd->fdt_blob, node) { |
| 1081 | if (!fdtdec_get_is_enabled(gd->fdt_blob, child)) |
| 1082 | continue; |
| 1083 | |
| 1084 | i = fdtdec_get_int(gd->fdt_blob, child, "reg", -1); |
| 1085 | if (i < 0 || i >= ARRAY_SIZE(comphy_nodes)) |
| 1086 | continue; |
| 1087 | |
| 1088 | comphy_nodes[i] = child; |
| 1089 | } |
| 1090 | |
| 1091 | for (i = 0; i < ARRAY_SIZE(comphy_nodes); i++) { |
| 1092 | cfg->comphy_map_data[i].type = COMPHY_TYPE_UNCONNECTED; |
| 1093 | cfg->comphy_map_data[i].speed = COMPHY_SPEED_INVALID; |
| 1094 | } |
| 1095 | |
| 1096 | comphy_a3700_fill_cfg(cfg, comphy_nodes, "marvell,armada3700-u3d", |
| 1097 | COMPHY_TYPE_USB3_DEVICE); |
| 1098 | comphy_a3700_fill_cfg(cfg, comphy_nodes, "marvell,armada3700-xhci", |
| 1099 | COMPHY_TYPE_USB3_HOST0); |
| 1100 | comphy_a3700_fill_cfg(cfg, comphy_nodes, "marvell,armada-3700-pcie", |
| 1101 | COMPHY_TYPE_PEX0); |
| 1102 | comphy_a3700_fill_cfg(cfg, comphy_nodes, "marvell,armada-3700-ahci", |
| 1103 | COMPHY_TYPE_SATA0); |
| 1104 | comphy_a3700_fill_cfg(cfg, comphy_nodes, "marvell,armada-3700-neta", |
| 1105 | COMPHY_TYPE_SGMII0); |
| 1106 | comphy_a3700_fill_cfg(cfg, comphy_nodes, "marvell,armada-3700-neta", |
| 1107 | COMPHY_TYPE_SGMII1); |
| 1108 | |
| 1109 | cfg->comphy_lanes_count = 3; |
| 1110 | cfg->comphy_mux_bitcount = 4; |
| 1111 | cfg->comphy_mux_lane_order = comphy_a3700_mux_lane_order; |
| 1112 | |
| 1113 | return 0; |
| 1114 | } |
| 1115 | |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 1116 | int comphy_a3700_init(struct chip_serdes_phy_config *chip_cfg, |
| 1117 | struct comphy_map *serdes_map) |
| 1118 | { |
| 1119 | struct comphy_map *comphy_map; |
| 1120 | u32 comphy_max_count = chip_cfg->comphy_lanes_count; |
| 1121 | u32 lane, ret = 0; |
| 1122 | |
| 1123 | debug_enter(); |
| 1124 | |
Marek Behún | 817c2ce | 2018-04-24 17:21:23 +0200 | [diff] [blame] | 1125 | /* Initialize PHY mux */ |
| 1126 | chip_cfg->mux_data = a3700_comphy_mux_data; |
| 1127 | comphy_mux_init(chip_cfg, serdes_map, COMPHY_SEL_ADDR); |
| 1128 | |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 1129 | for (lane = 0, comphy_map = serdes_map; lane < comphy_max_count; |
| 1130 | lane++, comphy_map++) { |
| 1131 | debug("Initialize serdes number %d\n", lane); |
| 1132 | debug("Serdes type = 0x%x invert=%d\n", |
| 1133 | comphy_map->type, comphy_map->invert); |
| 1134 | |
| 1135 | switch (comphy_map->type) { |
Igal Liberman | ffd5d2f | 2017-04-26 15:40:00 +0300 | [diff] [blame] | 1136 | case COMPHY_TYPE_UNCONNECTED: |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 1137 | continue; |
| 1138 | break; |
| 1139 | |
Igal Liberman | ffd5d2f | 2017-04-26 15:40:00 +0300 | [diff] [blame] | 1140 | case COMPHY_TYPE_PEX0: |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 1141 | ret = comphy_pcie_power_up(comphy_map->speed, |
| 1142 | comphy_map->invert); |
| 1143 | break; |
| 1144 | |
Igal Liberman | ffd5d2f | 2017-04-26 15:40:00 +0300 | [diff] [blame] | 1145 | case COMPHY_TYPE_USB3_HOST0: |
| 1146 | case COMPHY_TYPE_USB3_DEVICE: |
Marek Behún | ef6f36e | 2018-04-24 17:21:18 +0200 | [diff] [blame] | 1147 | ret = comphy_usb3_power_up(lane, |
| 1148 | comphy_map->type, |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 1149 | comphy_map->speed, |
| 1150 | comphy_map->invert); |
| 1151 | break; |
| 1152 | |
Igal Liberman | ffd5d2f | 2017-04-26 15:40:00 +0300 | [diff] [blame] | 1153 | case COMPHY_TYPE_SGMII0: |
| 1154 | case COMPHY_TYPE_SGMII1: |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 1155 | ret = comphy_sgmii_power_up(lane, comphy_map->speed, |
| 1156 | comphy_map->invert); |
| 1157 | break; |
| 1158 | |
Igal Liberman | ffd5d2f | 2017-04-26 15:40:00 +0300 | [diff] [blame] | 1159 | case COMPHY_TYPE_SATA0: |
zachary | ba42e84 | 2020-08-28 16:56:29 +0200 | [diff] [blame] | 1160 | ret = comphy_sata_power_up(comphy_map->invert); |
| 1161 | break; |
| 1162 | |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 1163 | default: |
| 1164 | debug("Unknown SerDes type, skip initialize SerDes %d\n", |
| 1165 | lane); |
| 1166 | ret = 1; |
| 1167 | break; |
| 1168 | } |
Marek Behún | e3183c6 | 2018-04-24 17:21:16 +0200 | [diff] [blame] | 1169 | if (!ret) |
Stefan Roese | 8f64e26 | 2016-05-23 11:12:05 +0200 | [diff] [blame] | 1170 | printf("PLL is not locked - Failed to initialize lane %d\n", |
| 1171 | lane); |
| 1172 | } |
| 1173 | |
| 1174 | debug_exit(); |
| 1175 | return ret; |
| 1176 | } |