phy: marvell: rename comphy related definitions to COMPHY_XX
Currently, all comphy definitions are PHY_TYPE_XX and PHY_SPEEED_XX.
Those definition might be confused with MDIO PHY definitions.
This patch does the following changes:
- PHY_TYPE_XX --> COMPHY_TYPE_XX
- PHY_SPEED_XX --> COMPHY_SPEED_XX
This improves readability, no functional change.
Change-Id: I2bd1d9289ebbc5c16fa80f9870f797ea1bcaf5fa
Signed-off-by: Igal Liberman <igall@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
diff --git a/drivers/phy/marvell/comphy_a3700.c b/drivers/phy/marvell/comphy_a3700.c
index 12523d1..06822d1 100644
--- a/drivers/phy/marvell/comphy_a3700.c
+++ b/drivers/phy/marvell/comphy_a3700.c
@@ -17,33 +17,33 @@
DECLARE_GLOBAL_DATA_PTR;
struct comphy_mux_data a3700_comphy_mux_data[] = {
-/* Lane 0 */
+ /* Lane 0 */
{
4,
{
- { PHY_TYPE_UNCONNECTED, 0x0 },
- { PHY_TYPE_SGMII1, 0x0 },
- { PHY_TYPE_USB3_HOST0, 0x1 },
- { PHY_TYPE_USB3_DEVICE, 0x1 }
+ { COMPHY_TYPE_UNCONNECTED, 0x0 },
+ { COMPHY_TYPE_SGMII1, 0x0 },
+ { COMPHY_TYPE_USB3_HOST0, 0x1 },
+ { COMPHY_TYPE_USB3_DEVICE, 0x1 }
}
},
-/* Lane 1 */
+ /* Lane 1 */
{
3,
{
- { PHY_TYPE_UNCONNECTED, 0x0},
- { PHY_TYPE_SGMII0, 0x0},
- { PHY_TYPE_PEX0, 0x1}
+ { COMPHY_TYPE_UNCONNECTED, 0x0},
+ { COMPHY_TYPE_SGMII0, 0x0},
+ { COMPHY_TYPE_PEX0, 0x1}
}
},
-/* Lane 2 */
+ /* Lane 2 */
{
4,
{
- { PHY_TYPE_UNCONNECTED, 0x0},
- { PHY_TYPE_SATA0, 0x0},
- { PHY_TYPE_USB3_HOST0, 0x1},
- { PHY_TYPE_USB3_DEVICE, 0x1}
+ { COMPHY_TYPE_UNCONNECTED, 0x0},
+ { COMPHY_TYPE_SATA0, 0x0},
+ { COMPHY_TYPE_USB3_HOST0, 0x1},
+ { COMPHY_TYPE_USB3_DEVICE, 0x1}
}
},
};
@@ -228,10 +228,10 @@
/*
* 10. Check the Polarity invert bit
*/
- if (invert & PHY_POLARITY_TXD_INVERT)
+ if (invert & COMPHY_POLARITY_TXD_INVERT)
reg_set16(phy_addr(PCIE, SYNC_PATTERN), phy_txd_inv, 0);
- if (invert & PHY_POLARITY_RXD_INVERT)
+ if (invert & COMPHY_POLARITY_RXD_INVERT)
reg_set16(phy_addr(PCIE, SYNC_PATTERN), phy_rxd_inv, 0);
/*
@@ -284,10 +284,10 @@
/*
* 0. Check the Polarity invert bits
*/
- if (invert & PHY_POLARITY_TXD_INVERT)
+ if (invert & COMPHY_POLARITY_TXD_INVERT)
data |= bs_txd_inv;
- if (invert & PHY_POLARITY_RXD_INVERT)
+ if (invert & COMPHY_POLARITY_RXD_INVERT)
data |= bs_rxd_inv;
reg_set_indirect(vphy_sync_pattern_reg, data, bs_txd_inv | bs_rxd_inv);
@@ -465,10 +465,10 @@
/*
* 9. Check the Polarity invert bit
*/
- if (invert & PHY_POLARITY_TXD_INVERT)
+ if (invert & COMPHY_POLARITY_TXD_INVERT)
usb3_reg_set16(SYNC_PATTERN, phy_txd_inv, 0, lane);
- if (invert & PHY_POLARITY_RXD_INVERT)
+ if (invert & COMPHY_POLARITY_RXD_INVERT)
usb3_reg_set16(SYNC_PATTERN, phy_rxd_inv, 0, lane);
/*
@@ -513,7 +513,7 @@
* Set Soft ID for Host mode (Device mode works with Hard ID
* detection)
*/
- if (type == PHY_TYPE_USB3_HOST0) {
+ if (type == COMPHY_TYPE_USB3_HOST0) {
/*
* set BIT0: set ID_MODE of Host/Device = "Soft ID" (BIT1)
* clear BIT1: set SOFT_ID = Host
@@ -685,8 +685,8 @@
* comparison to 3.125 Gbps values. These register values are
* stored in "sgmii_phy_init_fix" array.
*/
- if ((speed != PHY_SPEED_1_25G) &&
- (sgmii_phy_init_fix[fix_idx].addr == addr)) {
+ if (speed != COMPHY_SPEED_1_25G &&
+ sgmii_phy_init_fix[fix_idx].addr == addr) {
/* Use new value */
val = sgmii_phy_init_fix[fix_idx].value;
if (fix_idx < fix_arr_sz)
@@ -737,13 +737,13 @@
* 7. Set PIN_PHY_GEN_TX[3:0] and PIN_PHY_GEN_RX[3:0] to decide
* COMPHY bit rate
*/
- if (speed == PHY_SPEED_3_125G) { /* 3.125 GHz */
+ if (speed == COMPHY_SPEED_3_125G) { /* 3.125 GHz */
reg_set(COMPHY_PHY_CFG1_ADDR(lane),
(0x8 << rf_gen_rx_sel_shift) |
(0x8 << rf_gen_tx_sel_shift),
rf_gen_rx_select | rf_gen_tx_select);
- } else if (speed == PHY_SPEED_1_25G) { /* 1.25 GHz */
+ } else if (speed == COMPHY_SPEED_1_25G) { /* 1.25 GHz */
reg_set(COMPHY_PHY_CFG1_ADDR(lane),
(0x6 << rf_gen_rx_sel_shift) |
(0x6 << rf_gen_tx_sel_shift),
@@ -819,7 +819,7 @@
* registers are OK.
*/
debug("Running C-DPI phy init %s mode\n",
- speed == PHY_SPEED_3_125G ? "2G5" : "1G");
+ speed == COMPHY_SPEED_3_125G ? "2G5" : "1G");
if (get_ref_clk() == 40)
comphy_sgmii_phy_init(lane, speed);
@@ -837,10 +837,10 @@
/*
* 18. Check the PHY Polarity invert bit
*/
- if (invert & PHY_POLARITY_TXD_INVERT)
+ if (invert & COMPHY_POLARITY_TXD_INVERT)
reg_set16(sgmiiphy_addr(lane, SYNC_PATTERN), phy_txd_inv, 0);
- if (invert & PHY_POLARITY_RXD_INVERT)
+ if (invert & COMPHY_POLARITY_RXD_INVERT)
reg_set16(sgmiiphy_addr(lane, SYNC_PATTERN), phy_rxd_inv, 0);
/*
@@ -976,30 +976,30 @@
comphy_map->type, comphy_map->invert);
switch (comphy_map->type) {
- case PHY_TYPE_UNCONNECTED:
+ case COMPHY_TYPE_UNCONNECTED:
continue;
break;
- case PHY_TYPE_PEX0:
+ case COMPHY_TYPE_PEX0:
ret = comphy_pcie_power_up(comphy_map->speed,
comphy_map->invert);
break;
- case PHY_TYPE_USB3_HOST0:
- case PHY_TYPE_USB3_DEVICE:
+ case COMPHY_TYPE_USB3_HOST0:
+ case COMPHY_TYPE_USB3_DEVICE:
ret = comphy_usb3_power_up(lane,
comphy_map->type,
comphy_map->speed,
comphy_map->invert);
break;
- case PHY_TYPE_SGMII0:
- case PHY_TYPE_SGMII1:
+ case COMPHY_TYPE_SGMII0:
+ case COMPHY_TYPE_SGMII1:
ret = comphy_sgmii_power_up(lane, comphy_map->speed,
comphy_map->invert);
break;
- case PHY_TYPE_SATA0:
+ case COMPHY_TYPE_SATA0:
ret = comphy_sata_power_up(comphy_map->invert);
break;