Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Bin Meng | 08e484c | 2014-12-17 15:50:36 +0800 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> |
Bin Meng | 08e484c | 2014-12-17 15:50:36 +0800 | [diff] [blame] | 4 | */ |
| 5 | |
Bin Meng | e0ff4b2 | 2016-02-01 01:40:54 -0800 | [diff] [blame] | 6 | #include <dm.h> |
Simon Glass | 9758973 | 2020-05-10 11:40:02 -0600 | [diff] [blame] | 7 | #include <init.h> |
Bin Meng | 4f6c577 | 2016-02-01 01:40:55 -0800 | [diff] [blame] | 8 | #include <dm/device-internal.h> |
Bin Meng | e0ff4b2 | 2016-02-01 01:40:54 -0800 | [diff] [blame] | 9 | #include <pci.h> |
Bin Meng | 08e484c | 2014-12-17 15:50:36 +0800 | [diff] [blame] | 10 | #include <asm/io.h> |
Bin Meng | 51c3b1e | 2015-05-25 22:35:04 +0800 | [diff] [blame] | 11 | #include <asm/irq.h> |
Bin Meng | 08e484c | 2014-12-17 15:50:36 +0800 | [diff] [blame] | 12 | #include <asm/post.h> |
Bin Meng | 1530536 | 2015-04-24 18:10:06 +0800 | [diff] [blame] | 13 | #include <asm/arch/device.h> |
Bin Meng | 51c3b1e | 2015-05-25 22:35:04 +0800 | [diff] [blame] | 14 | #include <asm/arch/tnc.h> |
Simon Glass | 6c34fc1 | 2019-09-25 08:00:11 -0600 | [diff] [blame] | 15 | #include <asm/fsp1/fsp_support.h> |
Bin Meng | 08e484c | 2014-12-17 15:50:36 +0800 | [diff] [blame] | 16 | #include <asm/processor.h> |
| 17 | |
Bin Meng | f041c56 | 2016-02-01 01:40:53 -0800 | [diff] [blame] | 18 | static int __maybe_unused disable_igd(void) |
Bin Meng | 2f0999e | 2015-10-01 00:36:04 -0700 | [diff] [blame] | 19 | { |
Bin Meng | 20ac76b | 2021-08-02 15:05:15 +0800 | [diff] [blame] | 20 | struct udevice *igd = NULL; |
| 21 | struct udevice *sdvo = NULL; |
Bin Meng | e0ff4b2 | 2016-02-01 01:40:54 -0800 | [diff] [blame] | 22 | int ret; |
| 23 | |
Bin Meng | 20ac76b | 2021-08-02 15:05:15 +0800 | [diff] [blame] | 24 | /* |
| 25 | * In case the IGD and SDVO devices were already in disabled state, |
| 26 | * we should return and not proceed any further. |
| 27 | */ |
| 28 | dm_pci_bus_find_bdf(TNC_IGD, &igd); |
| 29 | dm_pci_bus_find_bdf(TNC_SDVO, &sdvo); |
| 30 | if (!igd || !sdvo) |
Bin Meng | e0ff4b2 | 2016-02-01 01:40:54 -0800 | [diff] [blame] | 31 | return 0; |
| 32 | |
Bin Meng | 239a40a | 2015-10-22 19:13:32 -0700 | [diff] [blame] | 33 | /* |
| 34 | * According to Atom E6xx datasheet, setting VGA Disable (bit17) |
| 35 | * of Graphics Controller register (offset 0x50) prevents IGD |
| 36 | * (D2:F0) from reporting itself as a VGA display controller |
| 37 | * class in the PCI configuration space, and should also prevent |
| 38 | * it from responding to VGA legacy memory range and I/O addresses. |
| 39 | * |
| 40 | * However test result shows that with just VGA Disable bit set and |
| 41 | * a PCIe graphics card connected to one of the PCIe controllers on |
| 42 | * the E6xx, accessing the VGA legacy space still causes system hang. |
| 43 | * After a number of attempts, it turns out besides VGA Disable bit, |
| 44 | * the SDVO (D3:F0) device should be disabled to make it work. |
| 45 | * |
| 46 | * To simplify, use the Function Disable register (offset 0xc4) |
| 47 | * to disable both IGD (D2:F0) and SDVO (D3:F0) devices. Now these |
| 48 | * two devices will be completely disabled (invisible in the PCI |
| 49 | * configuration space) unless a system reset is performed. |
| 50 | */ |
Bin Meng | e0ff4b2 | 2016-02-01 01:40:54 -0800 | [diff] [blame] | 51 | dm_pci_write_config32(igd, IGD_FD, FUNC_DISABLE); |
| 52 | dm_pci_write_config32(sdvo, IGD_FD, FUNC_DISABLE); |
Bin Meng | f041c56 | 2016-02-01 01:40:53 -0800 | [diff] [blame] | 53 | |
Bin Meng | 4f6c577 | 2016-02-01 01:40:55 -0800 | [diff] [blame] | 54 | /* |
| 55 | * After setting the function disable bit, IGD and SDVO devices will |
| 56 | * disappear in the PCI configuration space. This however creates an |
| 57 | * inconsistent state from a driver model PCI controller point of view, |
| 58 | * as these two PCI devices are still attached to its parent's child |
| 59 | * device list as maintained by the driver model. Some driver model PCI |
| 60 | * APIs like dm_pci_find_class(), are referring to the list to speed up |
| 61 | * the finding process instead of re-enumerating the whole PCI bus, so |
| 62 | * it gets the stale cached data which is wrong. |
| 63 | * |
| 64 | * Note x86 PCI enueration normally happens twice, in pre-relocation |
| 65 | * phase and post-relocation. One option might be to call disable_igd() |
| 66 | * in one of the pre-relocation initialization hooks so that it gets |
| 67 | * disabled in the first round, and when it comes to the second round |
| 68 | * driver model PCI will construct a correct list. Unfortunately this |
| 69 | * does not work as Intel FSP is used on this platform to perform low |
| 70 | * level initialization, and fsp_init_phase_pci() is called only once |
| 71 | * in the post-relocation phase. If we disable IGD and SDVO devices, |
| 72 | * fsp_init_phase_pci() simply hangs and never returns. |
| 73 | * |
| 74 | * So the only option we have is to manually remove these two devices. |
| 75 | */ |
Stefan Roese | 80b5bc9 | 2017-03-20 12:51:48 +0100 | [diff] [blame] | 76 | ret = device_remove(igd, DM_REMOVE_NORMAL); |
Bin Meng | 4f6c577 | 2016-02-01 01:40:55 -0800 | [diff] [blame] | 77 | if (ret) |
| 78 | return ret; |
| 79 | ret = device_unbind(igd); |
| 80 | if (ret) |
| 81 | return ret; |
Stefan Roese | 80b5bc9 | 2017-03-20 12:51:48 +0100 | [diff] [blame] | 82 | ret = device_remove(sdvo, DM_REMOVE_NORMAL); |
Bin Meng | 4f6c577 | 2016-02-01 01:40:55 -0800 | [diff] [blame] | 83 | if (ret) |
| 84 | return ret; |
| 85 | ret = device_unbind(sdvo); |
| 86 | if (ret) |
| 87 | return ret; |
| 88 | |
Bin Meng | f041c56 | 2016-02-01 01:40:53 -0800 | [diff] [blame] | 89 | return 0; |
Bin Meng | 2f0999e | 2015-10-01 00:36:04 -0700 | [diff] [blame] | 90 | } |
| 91 | |
Bin Meng | 08e484c | 2014-12-17 15:50:36 +0800 | [diff] [blame] | 92 | int arch_cpu_init(void) |
| 93 | { |
| 94 | post_code(POST_CPU_INIT); |
Bin Meng | 08e484c | 2014-12-17 15:50:36 +0800 | [diff] [blame] | 95 | |
Masahiro Yamada | 1710321 | 2016-09-06 22:17:36 +0900 | [diff] [blame] | 96 | return x86_cpu_init_f(); |
Bin Meng | 08e484c | 2014-12-17 15:50:36 +0800 | [diff] [blame] | 97 | } |
Bin Meng | 1530536 | 2015-04-24 18:10:06 +0800 | [diff] [blame] | 98 | |
Bin Meng | 0c9f594 | 2018-06-03 19:04:22 -0700 | [diff] [blame] | 99 | static void tnc_irq_init(void) |
| 100 | { |
| 101 | struct tnc_rcba *rcba; |
| 102 | u32 base; |
| 103 | |
| 104 | pci_read_config32(TNC_LPC, LPC_RCBA, &base); |
| 105 | base &= ~MEM_BAR_EN; |
| 106 | rcba = (struct tnc_rcba *)base; |
| 107 | |
| 108 | /* Make sure all internal PCI devices are using INTA */ |
| 109 | writel(INTA, &rcba->d02ip); |
| 110 | writel(INTA, &rcba->d03ip); |
| 111 | writel(INTA, &rcba->d27ip); |
| 112 | writel(INTA, &rcba->d31ip); |
| 113 | writel(INTA, &rcba->d23ip); |
| 114 | writel(INTA, &rcba->d24ip); |
| 115 | writel(INTA, &rcba->d25ip); |
| 116 | writel(INTA, &rcba->d26ip); |
| 117 | |
| 118 | /* |
| 119 | * Route TunnelCreek PCI device interrupt pin to PIRQ |
| 120 | * |
| 121 | * Since PCIe downstream ports received INTx are routed to PIRQ |
| 122 | * A/B/C/D directly and not configurable, we have to route PCIe |
| 123 | * root ports' INTx to PIRQ A/B/C/D as well. For other devices |
| 124 | * on TunneCreek, route them to PIRQ E/F/G/H. |
| 125 | */ |
| 126 | writew(PIRQE, &rcba->d02ir); |
| 127 | writew(PIRQF, &rcba->d03ir); |
| 128 | writew(PIRQG, &rcba->d27ir); |
| 129 | writew(PIRQH, &rcba->d31ir); |
| 130 | writew(PIRQA, &rcba->d23ir); |
| 131 | writew(PIRQB, &rcba->d24ir); |
| 132 | writew(PIRQC, &rcba->d25ir); |
| 133 | writew(PIRQD, &rcba->d26ir); |
| 134 | } |
| 135 | |
Bin Meng | 2f0999e | 2015-10-01 00:36:04 -0700 | [diff] [blame] | 136 | int arch_early_init_r(void) |
| 137 | { |
Bin Meng | f041c56 | 2016-02-01 01:40:53 -0800 | [diff] [blame] | 138 | int ret = 0; |
| 139 | |
Bin Meng | 2f0999e | 2015-10-01 00:36:04 -0700 | [diff] [blame] | 140 | #ifdef CONFIG_DISABLE_IGD |
Bin Meng | f041c56 | 2016-02-01 01:40:53 -0800 | [diff] [blame] | 141 | ret = disable_igd(); |
Bin Meng | 2f0999e | 2015-10-01 00:36:04 -0700 | [diff] [blame] | 142 | #endif |
| 143 | |
Bin Meng | 0c9f594 | 2018-06-03 19:04:22 -0700 | [diff] [blame] | 144 | tnc_irq_init(); |
| 145 | |
Bin Meng | f041c56 | 2016-02-01 01:40:53 -0800 | [diff] [blame] | 146 | return ret; |
Bin Meng | 2f0999e | 2015-10-01 00:36:04 -0700 | [diff] [blame] | 147 | } |