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git01.mediatek.com / filogic / uboot / 1d52512b2e81dbfae2cf11f6ef886bc22a7cd4d8 / . / arch / x86 / cpu / intel_common / car.S
blob: 46d9ede09cb0faee04025e2ec11b9167aeca122a [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0 */
Simon Glass0b36ecd2014-11-12 22:42:07 -0700[diff] [blame]2/*
3 * Copyright (c) 2014 Google, Inc
4 *
5 * From Coreboot file cpu/intel/model_206ax/cache_as_ram.inc
6 *
7 * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
8 * Copyright (C) 2005 Tyan (written by Yinghai Lu for Tyan)
9 * Copyright (C) 2007-2008 coresystems GmbH
10 * Copyright (C) 2012 Kyösti Mälkki <kyosti.malkki@gmail.com>
Simon Glass0b36ecd2014-11-12 22:42:07 -0700[diff] [blame]11 */
12
Simon Glass2df61882016-03-11 22:06:54 -0700[diff] [blame]13#include <asm/microcode.h>
Simon Glass9281eb52015-01-01 16:18:14 -0700[diff] [blame]14#include <asm/msr-index.h>
Simon Glass98f139b2014-11-12 22:42:10 -0700[diff] [blame]15#include <asm/mtrr.h>
16#include <asm/post.h>
Simon Glassa9a44262015-04-29 22:25:59 -0600[diff] [blame]17#include <asm/processor.h>
Simon Glass98f139b2014-11-12 22:42:10 -0700[diff] [blame]18#include <asm/processor-flags.h>
Simon Glass0b36ecd2014-11-12 22:42:07 -0700[diff] [blame]19
Simon Glass98f139b2014-11-12 22:42:10 -0700[diff] [blame]20#define MTRR_PHYS_BASE_MSR(reg) (0x200 + 2 * (reg))
21#define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1)
22
23#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
24#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
25
26/* Cache 4GB - MRC_SIZE_KB for MRC */
27#define CACHE_MRC_BYTES ((CONFIG_CACHE_MRC_SIZE_KB << 10) - 1)
28#define CACHE_MRC_BASE (0xFFFFFFFF - CACHE_MRC_BYTES)
29#define CACHE_MRC_MASK (~CACHE_MRC_BYTES)
30
31#define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_ADDR_BITS - 32) - 1)
32
33#define NOEVICTMOD_MSR 0x2e0
34
35 /*
36 * Note: ebp must not be touched in this code as it holds the BIST
37 * value (built-in self test). We preserve this value until it can
38 * be written to global_data when CAR is ready for use.
39 */
Simon Glass0b36ecd2014-11-12 22:42:07 -0700[diff] [blame]40.globl car_init
41car_init:
Simon Glass98f139b2014-11-12 22:42:10 -0700[diff] [blame]42 post_code(POST_CAR_START)
43
44 /* Send INIT IPI to all excluding ourself */
45 movl $0x000C4500, %eax
46 movl $0xFEE00300, %esi
47 movl %eax, (%esi)
48
Simon Glass9281eb52015-01-01 16:18:14 -0700[diff] [blame]49 /* TODO: Load microcode later - the 'no eviction' mode breaks this */
50 movl $MSR_IA32_UCODE_WRITE, %ecx
51 xorl %edx, %edx
52 movl $_dt_ucode_base_size, %eax
53 movl (%eax), %eax
54 addl $UCODE_HEADER_LEN, %eax
55 wrmsr
56
Simon Glass98f139b2014-11-12 22:42:10 -0700[diff] [blame]57 post_code(POST_CAR_SIPI)
58 /* Zero out all fixed range and variable range MTRRs */
59 movl $mtrr_table, %esi
60 movl $((mtrr_table_end - mtrr_table) / 2), %edi
61 xorl %eax, %eax
62 xorl %edx, %edx
63clear_mtrrs:
64 movw (%esi), %bx
65 movzx %bx, %ecx
66 wrmsr
67 add $2, %esi
68 dec %edi
69 jnz clear_mtrrs
70
71 post_code(POST_CAR_MTRR)
72 /* Configure the default memory type to uncacheable */
Simon Glass7bf5b9e2015-01-01 16:18:07 -0700[diff] [blame]73 movl $MTRR_DEF_TYPE_MSR, %ecx
Simon Glass98f139b2014-11-12 22:42:10 -0700[diff] [blame]74 rdmsr
75 andl $(~0x00000cff), %eax
76 wrmsr
77
78 post_code(POST_CAR_UNCACHEABLE)
79 /* Set Cache-as-RAM base address */
80 movl $(MTRR_PHYS_BASE_MSR(0)), %ecx
81 movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax
82 xorl %edx, %edx
83 wrmsr
84
85 post_code(POST_CAR_BASE_ADDRESS)
86 /* Set Cache-as-RAM mask */
87 movl $(MTRR_PHYS_MASK_MSR(0)), %ecx
Simon Glass7bf5b9e2015-01-01 16:18:07 -0700[diff] [blame]88 movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
Simon Glass98f139b2014-11-12 22:42:10 -0700[diff] [blame]89 movl $CPU_PHYSMASK_HI, %edx
90 wrmsr
91
92 post_code(POST_CAR_MASK)
93
94 /* Enable MTRR */
Simon Glass7bf5b9e2015-01-01 16:18:07 -0700[diff] [blame]95 movl $MTRR_DEF_TYPE_MSR, %ecx
Simon Glass98f139b2014-11-12 22:42:10 -0700[diff] [blame]96 rdmsr
Simon Glass7bf5b9e2015-01-01 16:18:07 -0700[diff] [blame]97 orl $MTRR_DEF_TYPE_EN, %eax
Simon Glass98f139b2014-11-12 22:42:10 -0700[diff] [blame]98 wrmsr
99
100 /* Enable cache (CR0.CD = 0, CR0.NW = 0) */
101 movl %cr0, %eax
102 andl $(~(X86_CR0_CD | X86_CR0_NW)), %eax
103 invd
104 movl %eax, %cr0
105
106 /* enable the 'no eviction' mode */
107 movl $NOEVICTMOD_MSR, %ecx
108 rdmsr
109 orl $1, %eax
110 andl $~2, %eax
111 wrmsr
112
113 /* Clear the cache memory region. This will also fill up the cache */
114 movl $CACHE_AS_RAM_BASE, %esi
115 movl %esi, %edi
116 movl $(CACHE_AS_RAM_SIZE / 4), %ecx
117 xorl %eax, %eax
118 rep stosl
119
120 /* enable the 'no eviction run' state */
121 movl $NOEVICTMOD_MSR, %ecx
122 rdmsr
123 orl $3, %eax
124 wrmsr
125
126 post_code(POST_CAR_FILL)
127 /* Enable Cache-as-RAM mode by disabling cache */
128 movl %cr0, %eax
129 orl $X86_CR0_CD, %eax
130 movl %eax, %cr0
131
132 /* Enable cache for our code in Flash because we do XIP here */
133 movl $MTRR_PHYS_BASE_MSR(1), %ecx
134 xorl %edx, %edx
135 movl $car_init_ret, %eax
136 andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
137 orl $MTRR_TYPE_WRPROT, %eax
138 wrmsr
139
140 movl $MTRR_PHYS_MASK_MSR(1), %ecx
141 movl $CPU_PHYSMASK_HI, %edx
Simon Glass7bf5b9e2015-01-01 16:18:07 -0700[diff] [blame]142 movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
Simon Glass98f139b2014-11-12 22:42:10 -0700[diff] [blame]143 wrmsr
144
145 post_code(POST_CAR_ROM_CACHE)
146#ifdef CONFIG_CACHE_MRC_BIN
147 /* Enable caching for ram init code to run faster */
148 movl $MTRR_PHYS_BASE_MSR(2), %ecx
149 movl $(CACHE_MRC_BASE | MTRR_TYPE_WRPROT), %eax
150 xorl %edx, %edx
151 wrmsr
152 movl $MTRR_PHYS_MASK_MSR(2), %ecx
Simon Glass7bf5b9e2015-01-01 16:18:07 -0700[diff] [blame]153 movl $(CACHE_MRC_MASK | MTRR_PHYS_MASK_VALID), %eax
Simon Glass98f139b2014-11-12 22:42:10 -0700[diff] [blame]154 movl $CPU_PHYSMASK_HI, %edx
155 wrmsr
156#endif
157
158 post_code(POST_CAR_MRC_CACHE)
159 /* Enable cache */
160 movl %cr0, %eax
161 andl $(~(X86_CR0_CD | X86_CR0_NW)), %eax
162 movl %eax, %cr0
163
164 post_code(POST_CAR_CPU_CACHE)
165
166 /* All CPUs need to be in Wait for SIPI state */
167wait_for_sipi:
168 movl (%esi), %eax
169 bt $12, %eax
170 jc wait_for_sipi
171
172 /* return */
Simon Glass0b36ecd2014-11-12 22:42:07 -0700[diff] [blame]173 jmp car_init_ret
Simon Glass98f139b2014-11-12 22:42:10 -0700[diff] [blame]174
Simon Glasse5911012015-01-01 16:18:12 -0700[diff] [blame]175.globl car_uninit
176car_uninit:
177 /* Disable cache */
178 movl %cr0, %eax
179 orl $X86_CR0_CD, %eax
180 movl %eax, %cr0
181
182 /* Disable MTRRs */
183 movl $MTRR_DEF_TYPE_MSR, %ecx
184 rdmsr
185 andl $(~MTRR_DEF_TYPE_EN), %eax
186 wrmsr
187
188 /* Disable the no-eviction run state */
Simon Glass5d129802015-10-18 15:55:35 -0600[diff] [blame]189 movl $NOEVICTMOD_MSR, %ecx
Simon Glasse5911012015-01-01 16:18:12 -0700[diff] [blame]190 rdmsr
191 andl $~2, %eax
192 wrmsr
193
194 invd
195
196 /* Disable the no-eviction mode */
197 rdmsr
198 andl $~1, %eax
199 wrmsr
200
201#ifdef CONFIG_CACHE_MRC_BIN
202 /* Clear the MTRR that was used to cache MRC */
203 xorl %eax, %eax
204 xorl %edx, %edx
205 movl $MTRR_PHYS_BASE_MSR(2), %ecx
206 wrmsr
207 movl $MTRR_PHYS_MASK_MSR(2), %ecx
208 wrmsr
209#endif
210
211 /* Enable MTRRs */
212 movl $MTRR_DEF_TYPE_MSR, %ecx
213 rdmsr
214 orl $MTRR_DEF_TYPE_EN, %eax
215 wrmsr
216
217 invd
218
219 ret
220
Simon Glass98f139b2014-11-12 22:42:10 -0700[diff] [blame]221mtrr_table:
222 /* Fixed MTRRs */
223 .word 0x250, 0x258, 0x259
224 .word 0x268, 0x269, 0x26A
225 .word 0x26B, 0x26C, 0x26D
226 .word 0x26E, 0x26F
227 /* Variable MTRRs */
228 .word 0x200, 0x201, 0x202, 0x203
229 .word 0x204, 0x205, 0x206, 0x207
230 .word 0x208, 0x209, 0x20A, 0x20B
231 .word 0x20C, 0x20D, 0x20E, 0x20F
232 .word 0x210, 0x211, 0x212, 0x213
233mtrr_table_end:
Simon Glass9281eb52015-01-01 16:18:14 -0700[diff] [blame]234
235 .align 4
236_dt_ucode_base_size:
Simon Glasscb770c52019-04-25 21:58:44 -0600[diff] [blame]237 /* These next two fields are filled in by binman */
Simon Glass8dda5872016-03-11 22:07:11 -0700[diff] [blame]238.globl ucode_base
239ucode_base: /* Declared in microcode.h */
Simon Glass9281eb52015-01-01 16:18:14 -0700[diff] [blame]240 .long 0 /* microcode base */
Ivan Gorinov7fe40752018-06-21 21:16:16 -0700[diff] [blame]241.globl ucode_size
242ucode_size: /* Declared in microcode.h */
Simon Glass9281eb52015-01-01 16:18:14 -0700[diff] [blame]243 .long 0 /* microcode size */