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git01.mediatek.com / filogic / uboot / 1d36af30d75fa69a849ddfcbc968895f3d804ce8 / . / arch / arm / dts / imx8mp-verdin-wifi-dev-u-boot.dtsi
blob: 03f211d5f7d3b2bedf7bb829ce8fb14151b83eb1 [file] [log] [blame]
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2/*
3 * Copyright 2022 Toradex
4 */
5
6#include "imx8mp-u-boot.dtsi"
7
8/ {
Emanuele Ghidoliff939c22024-02-23 10:11:40 +0100[diff] [blame]9 aliases {
10 eeprom0 = &eeprom_module;
11 eeprom1 = &eeprom_carrier_board;
12 eeprom2 = &eeprom_display_adapter;
13 };
14
Emanuele Ghidoli26b5cba2024-02-23 10:11:41 +0100[diff] [blame]15 sysinfo {
16 compatible = "toradex,sysinfo";
17 };
18
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]19 wdt-reboot {
20 compatible = "wdt-reboot";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]21 bootph-pre-ram;
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]22 wdt = <&wdog1>;
23 };
24};
25
26&clk {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]27 bootph-all;
28 bootph-pre-ram;
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]29 /delete-property/ assigned-clocks;
30 /delete-property/ assigned-clock-parents;
31 /delete-property/ assigned-clock-rates;
32
33};
34
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]35&gpio1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]36 bootph-pre-ram;
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]37};
38
39&gpio2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]40 bootph-pre-ram;
Marcel Ziswilerf8621462022-07-21 15:46:44 +0200[diff] [blame]41
42 regulator-ethphy {
43 gpio-hog;
44 gpios = <20 GPIO_ACTIVE_HIGH>;
45 line-name = "reg_ethphy";
46 output-high;
47 pinctrl-names = "default";
48 pinctrl-0 = <&pinctrl_reg_eth>;
49 };
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]50};
51
52&gpio3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]53 bootph-pre-ram;
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]54};
55
56&gpio4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]57 bootph-pre-ram;
Andrejs Cainikovsdd1587c2023-07-11 11:09:18 +0200[diff] [blame]58
59 ctrl-sleep-moci-hog {
60 bootph-pre-ram;
61 };
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]62};
63
64&gpio5 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]65 bootph-pre-ram;
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]66};
67
68&i2c1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]69 bootph-pre-ram;
Marcel Ziswilerf8621462022-07-21 15:46:44 +0200[diff] [blame]70
71 eeprom_module: eeprom@50 {
72 compatible = "i2c-eeprom";
73 pagesize = <16>;
74 reg = <0x50>;
75 };
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]76};
77
78&i2c2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]79 bootph-pre-ram;
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]80};
81
82&i2c3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]83 bootph-pre-ram;
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]84};
85
Marcel Ziswilerf8621462022-07-21 15:46:44 +0200[diff] [blame]86&i2c4 {
87 /* EEPROM on display adapter (MIPI DSI Display Adapter) */
88 eeprom_display_adapter: eeprom@50 {
89 compatible = "i2c-eeprom";
90 pagesize = <16>;
91 reg = <0x50>;
92 };
93
94 /* EEPROM on carrier board */
95 eeprom_carrier_board: eeprom@57 {
96 compatible = "i2c-eeprom";
97 pagesize = <16>;
98 reg = <0x57>;
99 };
100};
101
102&pca9450 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]103 bootph-pre-ram;
Marcel Ziswilerf8621462022-07-21 15:46:44 +0200[diff] [blame]104};
105
Andrejs Cainikovsdd1587c2023-07-11 11:09:18 +0200[diff] [blame]106&pinctrl_ctrl_sleep_moci {
107 bootph-pre-ram;
108};
109
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]110&pinctrl_i2c1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]111 bootph-pre-ram;
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]112};
113
Marcel Ziswilerf8621462022-07-21 15:46:44 +0200[diff] [blame]114&pinctrl_usdhc2_pwr_en {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]115 bootph-pre-ram;
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]116 u-boot,off-on-delay-us = <20000>;
117};
118
119&pinctrl_uart3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]120 bootph-pre-ram;
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]121};
122
Marcel Ziswilerf8621462022-07-21 15:46:44 +0200[diff] [blame]123&pinctrl_usdhc2_cd {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]124 bootph-pre-ram;
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]125};
126
127&pinctrl_usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]128 bootph-pre-ram;
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]129};
130
131&pinctrl_usdhc3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]132 bootph-pre-ram;
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]133};
134
135&pinctrl_wdog {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]136 bootph-pre-ram;
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]137};
138
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]139&reg_usdhc2_vmmc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]140 bootph-pre-ram;
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]141};
142
143&uart3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]144 bootph-pre-ram;
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]145};
146
Marcel Ziswilerf8621462022-07-21 15:46:44 +0200[diff] [blame]147&usdhc1 {
148 status = "disabled";
149};
150
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]151&usdhc2 {
152 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
153 assigned-clock-rates = <400000000>;
154 assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
155 sd-uhs-ddr50;
156 sd-uhs-sdr104;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]157 bootph-pre-ram;
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]158};
159
160&usdhc3 {
161 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
162 assigned-clock-rates = <400000000>;
163 assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
164 mmc-hs400-1_8v;
165 mmc-hs400-enhanced-strobe;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]166 bootph-pre-ram;
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]167};
168
169&wdog1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]170 bootph-pre-ram;
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]171};