| Chia-Wei Wang | 1c7ed53 | 2024-09-10 17:39:16 +0800 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* |
| 3 | * Copyright (c) Aspeed Technology Inc. |
| 4 | */ |
| 5 | #ifndef __ASM_AST2700_SCU_H__ |
| 6 | #define __ASM_AST2700_SCU_H__ |
| 7 | |
| 8 | /* SCU0: CPU-die SCU */ |
| 9 | #define SCU0_HWSTRAP 0x010 |
| 10 | #define SCU0_HWSTRAP_DIS_RVAS BIT(30) |
| 11 | #define SCU0_HWSTRAP_DIS_WDTFULL BIT(25) |
| 12 | #define SCU0_HWSTRAP_DISARMICE_TZ BIT(22) |
| 13 | #define SCU0_HWSTRAP_DISABLE_XHCI BIT(21) |
| 14 | #define SCU0_HWSTRAP_BOOTEMMCSPEED BIT(20) |
| 15 | #define SCU0_HWSTRAP_VGA_CC BIT(18) |
| 16 | #define SCU0_HWSTRAP_EN_OPROM BIT(17) |
| 17 | #define SCU0_HWSTRAP_DISARMICE BIT(16) |
| 18 | #define SCU0_HWSTRAP_TSPRSNTSEL BIT(9) |
| 19 | #define SCU0_HWSTRAP_DISDEBUG BIT(8) |
| 20 | #define SCU0_HWSTRAP_HCLKHPLL BIT(7) |
| 21 | #define SCU0_HWSTRAP_HCLKSEL GENMASK(6, 5) |
| 22 | #define SCU0_HWSTRAP_CPUHPLL BIT(4) |
| 23 | #define SCU0_HWSTRAP_HPLLFREQ GENMASK(3, 2) |
| 24 | #define SCU0_HWSTRAP_BOOTSPI BIT(1) |
| 25 | #define SCU0_HWSTRAP_HWSTRAP_DISCPU BIT(0) |
| 26 | #define SCU0_DBGCTL 0x0c8 |
| 27 | #define SCU0_DBGCTL_MASK GENMASK(14, 0) |
| 28 | #define SCU0_DBGCTL_UARTDBG BIT(1) |
| 29 | #define SCU0_RSTCTL1 0x200 |
| 30 | #define SCU0_RSTCTL1_EMMC BIT(17) |
| 31 | #define SCU0_RSTCTL1_HACE BIT(4) |
| 32 | #define SCU0_RSTCTL1_CLR 0x204 |
| 33 | #define SCU0_RSTCTL1_CLR_EMMC BIT(17) |
| 34 | #define SCU0_RSTCTL1_CLR_HACE BIT(4) |
| 35 | #define SCU0_CLKGATE1 0x240 |
| 36 | #define SCU0_CLKGATE1_EMMC BIT(27) |
| 37 | #define SCU0_CLKGATE1_HACE BIT(13) |
| 38 | #define SCU0_CLKGATE1_DDRPHY BIT(11) |
| 39 | #define SCU0_CLKGATE1_CLR 0x244 |
| 40 | #define SCU0_CLKGATE1_CLR_EMMC BIT(27) |
| 41 | #define SCU0_CLKGATE1_CLR_HACE BIT(13) |
| 42 | #define SCU0_CLKGATE1_CLR_DDRPHY BIT(11) |
| 43 | #define SCU0_VGA0_SCRATCH 0x900 |
| 44 | #define SCU0_VGA0_SCRATCH_DRAM_INIT BIT(6) |
| 45 | #define SCU0_PCI_MISC70 0xa70 |
| 46 | #define SCU0_PCI_MISC70_EN_PCIEXHCI0 BIT(3) |
| 47 | #define SCU0_PCI_MISC70_EN_PCIEEHCI0 BIT(2) |
| 48 | #define SCU0_PCI_MISC70_EN_PCIEVGA0 BIT(0) |
| 49 | #define SCU0_PCI_MISC80 0xa80 |
| 50 | #define SCU0_PCI_MISC80_EN_PCIEXHCI1 BIT(3) |
| 51 | #define SCU0_PCI_MISC80_EN_PCIEEHCI1 BIT(2) |
| 52 | #define SCU0_PCI_MISC80_EN_PCIEVGA1 BIT(0) |
| 53 | #define SCU0_PCI_MISCF0 0xaf0 |
| 54 | #define SCU0_PCI_MISCF0_EN_PCIEXHCI1 BIT(3) |
| 55 | #define SCU0_PCI_MISCF0_EN_PCIEEHCI1 BIT(2) |
| 56 | #define SCU0_PCI_MISCF0_EN_PCIEVGA1 BIT(0) |
| 57 | #define SCU0_WPROT1 0xe04 |
| 58 | #define SCU0_WPROT1_0C8 BIT(18) |
| 59 | |
| 60 | /* SCU1: IO-die SCU */ |
| 61 | #define SCU1_REVISION 0x000 |
| 62 | #define SCU1_REVISION_HWID GENMASK(23, 16) |
| 63 | #define SCU1_REVISION_CHIP_EFUSE GENMASK(15, 8) |
| 64 | #define SCU1_HWSTRAP1 0x010 |
| 65 | #define SCU1_HWSTRAP1_DIS_CPTRA BIT(30) |
| 66 | #define SCU1_HWSTRAP1_RECOVERY_USB_PORT GENMASK(29, 28) |
| 67 | #define SCU1_HWSTRAP1_RECOVERY_INTERFACE GENMASK(27, 26) |
| 68 | #define SCU1_HWSTRAP1_RECOVERY_I3C (BIT(26) | BIT(27)) |
| 69 | #define SCU1_HWSTRAP1_RECOVERY_I2C BIT(27) |
| 70 | #define SCU1_HWSTRAP1_RECOVERY_USB BIT(26) |
| 71 | #define SCU1_HWSTRAP1_SPI_FLASH_4_BYTE_MODE BIT(25) |
| 72 | #define SCU1_HWSTRAP1_SPI_FLASH_WAIT_READY BIT(24) |
| 73 | #define SCU1_HWSTRAP1_BOOT_UFS BIT(23) |
| 74 | #define SCU1_HWSTRAP1_DIS_ROM BIT(22) |
| 75 | #define SCU1_HWSTRAP1_DIS_CPTRAJTAG BIT(20) |
| 76 | #define SCU1_HWSTRAP1_UARTDBGSEL BIT(19) |
| 77 | #define SCU1_HWSTRAP1_DIS_UARTDBG BIT(18) |
| 78 | #define SCU1_HWSTRAP1_DIS_WDTFULL BIT(17) |
| 79 | #define SCU1_HWSTRAP1_DISDEBUG1 BIT(16) |
| 80 | #define SCU1_HWSTRAP1_LTPI0_IO_DRIVING GENMASK(15, 14) |
| 81 | #define SCU1_HWSTRAP1_ACPI_1 BIT(13) |
| 82 | #define SCU1_HWSTRAP1_ACPI_0 BIT(12) |
| 83 | #define SCU1_HWSTRAP1_BOOT_EMMC_UFS BIT(11) |
| 84 | #define SCU1_HWSTRAP1_DDR4 BIT(10) |
| 85 | #define SCU1_HWSTRAP1_LOW_SECURE BIT(8) |
| 86 | #define SCU1_HWSTRAP1_EN_EMCS BIT(7) |
| 87 | #define SCU1_HWSTRAP1_EN_GPIOPT BIT(6) |
| 88 | #define SCU1_HWSTRAP1_EN_SECBOOT BIT(5) |
| 89 | #define SCU1_HWSTRAP1_EN_RECOVERY_BOOT BIT(4) |
| 90 | #define SCU1_HWSTRAP1_LTPI0_EN BIT(3) |
| 91 | #define SCU1_HWSTRAP1_LTPI_IDX BIT(2) |
| 92 | #define SCU1_HWSTRAP1_LTPI1_EN BIT(1) |
| 93 | #define SCU1_HWSTRAP1_LTPI_MODE BIT(0) |
| 94 | #define SCU1_HWSTRAP2 0x030 |
| 95 | #define SCU1_HWSTRAP2_FMC_ABR_SINGLE_FLASH BIT(29) |
| 96 | #define SCU1_HWSTRAP2_FMC_ABR_CS_SWAP_DIS BIT(28) |
| 97 | #define SCU1_HWSTRAP2_SPI_TPM_PCR_EXT_EN BIT(27) |
| 98 | #define SCU1_HWSTRAP2_SPI_TPM_HASH_ALGO GENMASK(26, 25) |
| 99 | #define SCU1_HWSTRAP2_BOOT_SPI_FREQ GENMASK(24, 23) |
| 100 | #define SCU1_HWSTRAP2_RESERVED GENMASK(22, 19) |
| 101 | #define SCU1_HWSTRAP2_FWSPI_CRTM GENMASK(18, 17) |
| 102 | #define SCU1_HWSTRAP2_EN_FWSPIAUX BIT(16) |
| 103 | #define SCU1_HWSTRAP2_FWSPISIZE GENMASK(15, 13) |
| 104 | #define SCU1_HWSTRAP2_DIS_REC BIT(12) |
| 105 | #define SCU1_HWSTRAP2_EN_CPTRA_DBG BIT(11) |
| 106 | #define SCU1_HWSTRAP2_TPM_PCR_INDEX GENMASK(6, 2) |
| 107 | #define SCU1_HWSTRAP2_ROM_CLEAR_SRAM BIT(1) |
| 108 | #define SCU1_HWSTRAP2_ABR BIT(0) |
| 109 | #define SCU1_RSTLOG0 0x050 |
| 110 | #define SCU1_RSTLOG0_BMC_CPU BIT(12) |
| 111 | #define SCU1_RSTLOG0_ABR BIT(2) |
| 112 | #define SCU1_RSTLOG0_EXTRSTN BIT(1) |
| 113 | #define SCU1_RSTLOG0_SRST BIT(0) |
| 114 | #define SCU1_MISC1 0x0c0 |
| 115 | #define SCU1_MISC1_UARTDBG_ROUTE GENMASK(23, 22) |
| 116 | #define SCU1_MISC1_UART12_ROUTE GENMASK(21, 20) |
| 117 | #define SCU1_DBGCTL 0x0c8 |
| 118 | #define SCU1_DBGCTL_MASK GENMASK(7, 0) |
| 119 | #define SCU1_DBGCTL_UARTDBG BIT(6) |
| 120 | #define SCU1_RNG_DATA 0x0f4 |
| 121 | #define SCU1_RSTCTL1 0x200 |
| 122 | #define SCU1_RSTCTL1_I3C(x) (BIT(16) << (x)) |
| 123 | #define SCU1_RSTCTL1_CLR 0x204 |
| 124 | #define SCU1_RSTCTL1_CLR_I3C(x) (BIT(16) << (x)) |
| 125 | #define SCU1_RSTCTL2 0x220 |
| 126 | #define SCU1_RSTCTL2_LTPI1 BIT(22) |
| 127 | #define SCU1_RSTCTL2_LTPI0 BIT(20) |
| 128 | #define SCU1_RSTCTL2_I2C BIT(15) |
| 129 | #define SCU1_RSTCTL2_CPTRA BIT(9) |
| 130 | #define SCU1_RSTCTL2_CLR 0x224 |
| 131 | #define SCU1_RSTCTL2_CLR_I2C BIT(15) |
| 132 | #define SCU1_RSTCTL2_CLR_CPTRA BIT(9) |
| 133 | #define SCU1_CLKGATE1 0x240 |
| 134 | #define SCU1_CLKGATE1_I3C(x) (BIT(16) << (x)) |
| 135 | #define SCU1_CLKGATE1_I2C BIT(15) |
| 136 | #define SCU1_CLKGATE1_CLR 0x244 |
| 137 | #define SCU1_CLKGATE1_CLR_I3C(x) (BIT(16) << (x)) |
| 138 | #define SCU1_CLKGATE1_CLR_I2C BIT(15) |
| 139 | #define SCU1_CLKGATE2 0x260 |
| 140 | #define SCU1_CLKGATE2_LTPI1_TX BIT(19) |
| 141 | #define SCU1_CLKGATE2_LTPI_AHB BIT(10) |
| 142 | #define SCU1_CLKGATE2_LTPI0_TX BIT(9) |
| 143 | #define SCU1_CLKGATE2_CLR 0x264 |
| 144 | |
| 145 | #endif |