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Bo Shen42aafb32012-07-05 17:21:46 +00001/*
2 * Copyright (C) 2012 Atmel Corporation
3 *
4 * Configuation settings for the AT91SAM9X5EK board.
5 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Bo Shen42aafb32012-07-05 17:21:46 +00007 */
8
9#ifndef __CONFIG_H__
10#define __CONFIG_H__
11
12#include <asm/hardware.h>
13
Bo Shen337a2d82013-08-13 14:50:49 +080014#define CONFIG_SYS_TEXT_BASE 0x26f00000
15
Bo Shen42aafb32012-07-05 17:21:46 +000016/* ARM asynchronous clock */
17#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
18#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
Bo Shen42aafb32012-07-05 17:21:46 +000019
20#define CONFIG_AT91SAM9X5EK
Bo Shen42aafb32012-07-05 17:21:46 +000021
Bo Shen42aafb32012-07-05 17:21:46 +000022#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
23#define CONFIG_SETUP_MEMORY_TAGS
24#define CONFIG_INITRD_TAG
25#define CONFIG_SKIP_LOWLEVEL_INIT
26#define CONFIG_BOARD_EARLY_INIT_F
27#define CONFIG_DISPLAY_CPUINFO
28
29/* general purpose I/O */
30#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
31#define CONFIG_AT91_GPIO
32
33/* serial console */
34#define CONFIG_ATMEL_USART
35#define CONFIG_USART_BASE ATMEL_BASE_DBGU
36#define CONFIG_USART_ID ATMEL_ID_SYS
37
38/* LCD */
39#define CONFIG_LCD
40#define LCD_BPP LCD_COLOR16
41#define LCD_OUTPUT_BPP 24
42#define CONFIG_LCD_LOGO
Bo Shen42aafb32012-07-05 17:21:46 +000043#define CONFIG_LCD_INFO
44#define CONFIG_LCD_INFO_BELOW_LOGO
45#define CONFIG_SYS_WHITE_ON_BLACK
46#define CONFIG_ATMEL_HLCD
47#define CONFIG_ATMEL_LCD_RGB565
48#define CONFIG_SYS_CONSOLE_IS_IN_ENV
49
Bo Shen42aafb32012-07-05 17:21:46 +000050
51/*
52 * BOOTP options
53 */
54#define CONFIG_BOOTP_BOOTFILESIZE
55#define CONFIG_BOOTP_BOOTPATH
56#define CONFIG_BOOTP_GATEWAY
57#define CONFIG_BOOTP_HOSTNAME
58
Bo Shen963a2b12013-12-10 16:14:02 +080059/* no NOR flash */
60#define CONFIG_SYS_NO_FLASH
61
Bo Shen42aafb32012-07-05 17:21:46 +000062/*
63 * Command line configuration.
64 */
Bo Shen42aafb32012-07-05 17:21:46 +000065#define CONFIG_CMD_NAND
Richard Genoud1e34e832012-11-29 23:18:34 +000066
67/*
68 * define CONFIG_USB_EHCI to enable USB Hi-Speed (aka 2.0)
69 * NB: in this case, USB 1.1 devices won't be recognized.
70 */
71
Bo Shen42aafb32012-07-05 17:21:46 +000072/* SDRAM */
73#define CONFIG_NR_DRAM_BANKS 1
74#define CONFIG_SYS_SDRAM_BASE 0x20000000
75#define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */
76
77#define CONFIG_SYS_INIT_SP_ADDR \
78 (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
79
80/* DataFlash */
Bo Shen4a73e582012-08-19 20:32:24 +000081#ifdef CONFIG_CMD_SF
82#define CONFIG_ATMEL_SPI
Bo Shen4a73e582012-08-19 20:32:24 +000083#define CONFIG_SF_DEFAULT_SPEED 30000000
Bo Shen42aafb32012-07-05 17:21:46 +000084#endif
85
Bo Shen42aafb32012-07-05 17:21:46 +000086/* NAND flash */
87#ifdef CONFIG_CMD_NAND
88#define CONFIG_NAND_ATMEL
89#define CONFIG_SYS_MAX_NAND_DEVICE 1
90#define CONFIG_SYS_NAND_BASE 0x40000000
91#define CONFIG_SYS_NAND_DBW_8 1
92/* our ALE is AD21 */
93#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
94/* our CLE is AD22 */
95#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
96#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4
97#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5
98
Wu, Joshdd359a12012-08-23 00:05:38 +000099/* PMECC & PMERRLOC */
100#define CONFIG_ATMEL_NAND_HWECC 1
101#define CONFIG_ATMEL_NAND_HW_PMECC 1
102#define CONFIG_PMECC_CAP 2
103#define CONFIG_PMECC_SECTOR_SIZE 512
Wu, Joshdd359a12012-08-23 00:05:38 +0000104
Bo Shen591ef582013-06-26 10:48:53 +0800105#define CONFIG_CMD_NAND_TRIMFFS
106
Bo Shen42aafb32012-07-05 17:21:46 +0000107#define CONFIG_MTD_DEVICE
108#define CONFIG_CMD_MTDPARTS
109#define CONFIG_MTD_PARTITIONS
110#define CONFIG_RBTREE
111#define CONFIG_LZO
Bo Shen42aafb32012-07-05 17:21:46 +0000112#define CONFIG_CMD_UBIFS
113#endif
114
Wu, Joshe32c6612012-09-13 22:22:05 +0000115/* MMC */
116#ifdef CONFIG_CMD_MMC
117#define CONFIG_MMC
Wu, Joshe32c6612012-09-13 22:22:05 +0000118#define CONFIG_GENERIC_MMC
119#define CONFIG_GENERIC_ATMEL_MCI
Richard Genoudfa2dbe72012-11-29 23:18:33 +0000120#endif
121
122/* FAT */
123#ifdef CONFIG_CMD_FAT
Wu, Joshe32c6612012-09-13 22:22:05 +0000124#define CONFIG_DOS_PARTITION
125#endif
126
Bo Shen42aafb32012-07-05 17:21:46 +0000127/* Ethernet */
128#define CONFIG_MACB
129#define CONFIG_RMII
130#define CONFIG_NET_RETRY_COUNT 20
131#define CONFIG_MACB_SEARCH_PHY
132
Richard Genoud1e34e832012-11-29 23:18:34 +0000133/* USB */
134#ifdef CONFIG_CMD_USB
135#ifdef CONFIG_USB_EHCI
136#define CONFIG_USB_EHCI_ATMEL
137#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2
138#else
Bo Shen4a985df2013-10-21 16:14:00 +0800139#define CONFIG_USB_ATMEL
140#define CONFIG_USB_ATMEL_CLK_SEL_UPLL
Richard Genoud1e34e832012-11-29 23:18:34 +0000141#define CONFIG_USB_OHCI_NEW
142#define CONFIG_SYS_USB_OHCI_CPU_INIT
143#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI
144#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9x5"
145#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3
146#endif
Richard Genoud1e34e832012-11-29 23:18:34 +0000147#endif
148
Bo Shen42aafb32012-07-05 17:21:46 +0000149#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
150
151#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
152#define CONFIG_SYS_MEMTEST_END 0x26e00000
153
154#ifdef CONFIG_SYS_USE_NANDFLASH
155/* bootstrap + u-boot + env + linux in nandflash */
156#define CONFIG_ENV_IS_IN_NAND
157#define CONFIG_ENV_OFFSET 0xc0000
158#define CONFIG_ENV_OFFSET_REDUND 0x100000
159#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
160#define CONFIG_BOOTCOMMAND "nand read " \
161 "0x22000000 0x200000 0x300000; " \
162 "bootm 0x22000000"
Wu, Josh9d681892012-11-02 00:17:27 +0000163#elif defined(CONFIG_SYS_USE_SPIFLASH)
Bo Shen4a73e582012-08-19 20:32:24 +0000164/* bootstrap + u-boot + env + linux in spi flash */
165#define CONFIG_ENV_IS_IN_SPI_FLASH
166#define CONFIG_ENV_OFFSET 0x5000
167#define CONFIG_ENV_SIZE 0x3000
168#define CONFIG_ENV_SECT_SIZE 0x1000
169#define CONFIG_ENV_SPI_MAX_HZ 30000000
170#define CONFIG_BOOTCOMMAND "sf probe 0; " \
171 "sf read 0x22000000 0x100000 0x300000; " \
172 "bootm 0x22000000"
Bo Shen0a9f8ac2012-12-06 21:37:04 +0000173#elif defined(CONFIG_SYS_USE_DATAFLASH)
174/* bootstrap + u-boot + env + linux in data flash */
175#define CONFIG_ENV_IS_IN_SPI_FLASH
176#define CONFIG_ENV_OFFSET 0x4200
177#define CONFIG_ENV_SIZE 0x4200
178#define CONFIG_ENV_SECT_SIZE 0x210
179#define CONFIG_ENV_SPI_MAX_HZ 30000000
180#define CONFIG_BOOTCOMMAND "sf probe 0; " \
181 "sf read 0x22000000 0x84000 0x294000; " \
182 "bootm 0x22000000"
Wu, Josh9d681892012-11-02 00:17:27 +0000183#else /* CONFIG_SYS_USE_MMC */
184/* bootstrap + u-boot + env + linux in mmc */
Wu, Joshdf0ef742015-01-20 10:33:33 +0800185#define CONFIG_ENV_IS_IN_FAT
186#define CONFIG_FAT_WRITE
187#define FAT_ENV_INTERFACE "mmc"
188#define FAT_ENV_FILE "uboot.env"
189#define FAT_ENV_DEVICE_AND_PART "0"
190#define CONFIG_ENV_SIZE 0x4000
Bo Shen42aafb32012-07-05 17:21:46 +0000191#endif
192
Wu, Josh9d681892012-11-02 00:17:27 +0000193#ifdef CONFIG_SYS_USE_MMC
Bo Shen42aafb32012-07-05 17:21:46 +0000194#define CONFIG_BOOTARGS "mem=128M console=ttyS0,115200 " \
195 "mtdparts=atmel_nand:" \
196 "8M(bootstrap/uboot/kernel)ro,-(rootfs) " \
Wu, Josh9d681892012-11-02 00:17:27 +0000197 "root=/dev/mmcblk0p2 " \
198 "rw rootfstype=ext4 rootwait"
199#else
Bo Shena8fd0632013-02-20 00:16:25 +0000200#define CONFIG_BOOTARGS \
201 "console=ttyS0,115200 earlyprintk " \
202 "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \
203 "256k(env),256k(env_redundant),256k(spare)," \
204 "512k(dtb),6M(kernel)ro,-(rootfs) " \
205 "rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs rw"
Wu, Josh9d681892012-11-02 00:17:27 +0000206#endif
Bo Shen42aafb32012-07-05 17:21:46 +0000207
208#define CONFIG_BAUDRATE 115200
209
Bo Shen42aafb32012-07-05 17:21:46 +0000210#define CONFIG_SYS_CBSIZE 256
211#define CONFIG_SYS_MAXARGS 16
Bo Shen42aafb32012-07-05 17:21:46 +0000212#define CONFIG_SYS_LONGHELP
213#define CONFIG_CMDLINE_EDITING
214#define CONFIG_AUTO_COMPLETE
Bo Shen42aafb32012-07-05 17:21:46 +0000215
216/*
217 * Size of malloc() pool
218 */
219#define CONFIG_SYS_MALLOC_LEN (512 * 1024 + 0x1000)
220
Bo Shen9a3b1fe2015-03-27 14:23:35 +0800221/* SPL */
222#define CONFIG_SPL_FRAMEWORK
223#define CONFIG_SPL_TEXT_BASE 0x300000
224#define CONFIG_SPL_MAX_SIZE 0x6000
225#define CONFIG_SPL_STACK 0x308000
226
227#define CONFIG_SPL_BSS_START_ADDR 0x20000000
228#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
229#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
230#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
231
Bo Shen9a3b1fe2015-03-27 14:23:35 +0800232#define CONFIG_SPL_BOARD_INIT
233#define CONFIG_SYS_MONITOR_LEN (512 << 10)
234
235#define CONFIG_SYS_MASTER_CLOCK 132096000
236#define CONFIG_SYS_AT91_PLLA 0x20c73f03
237#define CONFIG_SYS_MCKR 0x1301
238#define CONFIG_SYS_MCKR_CSS 0x1302
239
Bo Shen9a3b1fe2015-03-27 14:23:35 +0800240#ifdef CONFIG_SYS_USE_MMC
241#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
Bo Shen9a3b1fe2015-03-27 14:23:35 +0800242#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400
243#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200
244#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
245#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
Bo Shen9a3b1fe2015-03-27 14:23:35 +0800246
247#elif CONFIG_SYS_USE_NANDFLASH
Bo Shen9a3b1fe2015-03-27 14:23:35 +0800248#define CONFIG_SPL_NAND_DRIVERS
249#define CONFIG_SPL_NAND_BASE
250#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
251#define CONFIG_SYS_NAND_5_ADDR_CYCLE
252#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
253#define CONFIG_SYS_NAND_PAGE_COUNT 64
254#define CONFIG_SYS_NAND_OOBSIZE 64
255#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
256#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
257#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
258
259#elif CONFIG_SYS_USE_SPIFLASH
Bo Shen9a3b1fe2015-03-27 14:23:35 +0800260#define CONFIG_SPL_SPI_LOAD
261#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8400
262
263#endif
264
Bo Shen42aafb32012-07-05 17:21:46 +0000265#endif