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git01.mediatek.com / filogic / uboot / 1b7028d44fc3eaabf279e70a13343457851586f9 / . / arch / sandbox / dts / sandbox.dts
blob: 4dd82f6a32fd009c6fd9783ec42507afddef4501 [file] [log] [blame]
Simon Glass66c164b2014-02-26 15:59:14 -0700[diff] [blame]1/dts-v1/;
2
Simon Glass07bb5e72019-05-18 11:59:48 -0600[diff] [blame]3#include <config.h>
4
Simon Glass66c164b2014-02-26 15:59:14 -0700[diff] [blame]5/ {
Simon Glassfd91fc92014-10-13 23:41:48 -0600[diff] [blame]6 #address-cells = <1>;
Simon Glassf905be82015-03-05 12:25:13 -0700[diff] [blame]7 #size-cells = <1>;
Simon Glass00c34d5b2017-06-15 21:37:53 -0600[diff] [blame]8 model = "sandbox";
Heinrich Schuchardtdeaf2972019-11-09 09:39:01 +0100[diff] [blame]9 compatible = "sandbox";
Simon Glassfd91fc92014-10-13 23:41:48 -0600[diff] [blame]10
Simon Glass70778bc2015-03-05 12:25:26 -0700[diff] [blame]11 aliases {
Simon Glass72138b92015-04-20 12:37:28 -0600[diff] [blame]12 i2c0 = &i2c_0;
Simon Glass70778bc2015-03-05 12:25:26 -0700[diff] [blame]13 pci0 = &pci;
Simon Glass72138b92015-04-20 12:37:28 -0600[diff] [blame]14 rtc0 = &rtc_0;
Mario Six95922152018-08-09 14:51:19 +0200[diff] [blame]15 axi0 = &axi;
Simon Glassed3698a2019-05-18 11:59:42 -0600[diff] [blame]16 spi0 = &spi;
Simon Glass70778bc2015-03-05 12:25:26 -0700[diff] [blame]17 };
18
Simon Glass07bb5e72019-05-18 11:59:48 -0600[diff] [blame]19 memory {
20 reg = <0 CONFIG_SYS_SDRAM_SIZE>;
21 };
22
Simon Glass699c9ca2018-10-01 12:22:08 -0600[diff] [blame]23 cros_ec: cros-ec {
Simon Glass73f220c2015-03-26 09:29:39 -0600[diff] [blame]24 reg = <0 0>;
Simon Glasse5501552018-11-06 15:21:27 -0700[diff] [blame]25 u-boot,dm-pre-reloc;
Simon Glass73f220c2015-03-26 09:29:39 -0600[diff] [blame]26 compatible = "google,cros-ec-sandbox";
Simon Glass1f6acb52014-02-27 13:25:59 -0700[diff] [blame]27 };
28
Yannick Fertré9712c822019-10-07 15:29:05 +0200[diff] [blame]29 dsi_host: dsi_host {
30 compatible = "sandbox,dsi-host";
31 status = "okay";
32 };
33
Joe Hershberger89590c82018-07-02 14:47:54 -0500[diff] [blame]34 ethrawbus {
35 compatible = "sandbox,eth-raw-bus";
36 skip-localhost = <0>;
37 };
38
Simon Glass45ab0082015-05-22 15:42:16 -0600[diff] [blame]39 eth@10002000 {
40 compatible = "sandbox,eth";
41 reg = <0x10002000 0x1000>;
42 fake-host-hwaddr = [00 00 66 44 22 00];
43 };
44
Simon Glass72138b92015-04-20 12:37:28 -0600[diff] [blame]45 i2c_0: i2c@0 {
Simon Glass4f46a592014-12-10 08:55:53 -0700[diff] [blame]46 #address-cells = <1>;
47 #size-cells = <0>;
Simon Glassf905be82015-03-05 12:25:13 -0700[diff] [blame]48 reg = <0 0>;
Simon Glass4f46a592014-12-10 08:55:53 -0700[diff] [blame]49 compatible = "sandbox,i2c";
50 clock-frequency = <400000>;
Masahiro Yamada0b53a752015-08-27 12:44:30 +0900[diff] [blame]51 pinctrl-names = "default";
52 pinctrl-0 = <&pinctrl_i2c0>;
Simon Glassfefc7ba2017-04-10 11:34:51 -0600[diff] [blame]53 };
54
Simon Glass70778bc2015-03-05 12:25:26 -0700[diff] [blame]55 pci: pci-controller {
56 compatible = "sandbox,pci";
57 device_type = "pci";
58 #address-cells = <3>;
59 #size-cells = <2>;
60 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000
61 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Simon Glass70778bc2015-03-05 12:25:26 -0700[diff] [blame]62 };
63
Simon Glassed3698a2019-05-18 11:59:42 -0600[diff] [blame]64 spi: spi@0 {
Simon Glasse5501552018-11-06 15:21:27 -0700[diff] [blame]65 u-boot,dm-pre-reloc;
Simon Glass45ab0082015-05-22 15:42:16 -0600[diff] [blame]66 #address-cells = <1>;
67 #size-cells = <0>;
68 reg = <0 0>;
69 compatible = "sandbox,spi";
70 cs-gpios = <0>, <&gpio_a 0>;
Joe Hershberger6ab76992015-03-22 17:09:13 -0500[diff] [blame]71 };
Simon Glass66c164b2014-02-26 15:59:14 -0700[diff] [blame]72};
Simon Glass73f220c2015-03-26 09:29:39 -0600[diff] [blame]73
Simon Glass28db4692019-05-18 11:59:41 -0600[diff] [blame]74#include "sandbox.dtsi"
Simon Glass73f220c2015-03-26 09:29:39 -0600[diff] [blame]75#include "cros-ec-keyboard.dtsi"
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200[diff] [blame]76#include "sandbox_pmic.dtsi"