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git01.mediatek.com / filogic / uboot / 1b7028d44fc3eaabf279e70a13343457851586f9 / . / arch / arm / mach-uniphier / clk / clk-pxs2.c
blob: 8cb4f87ae54b9491775588de3529cb1c63fd3c22 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Masahiro Yamada1fe65d32015-09-22 00:27:41 +0900[diff] [blame]2/*
3 * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada1fe65d32015-09-22 00:27:41 +0900[diff] [blame]4 */
5
Masahiro Yamada85ab6072016-07-22 20:20:11 +0900[diff] [blame]6#include <linux/bitops.h>
Masahiro Yamada1fe65d32015-09-22 00:27:41 +0900[diff] [blame]7#include <linux/io.h>
Masahiro Yamadaefdf3402016-01-09 01:51:13 +0900[diff] [blame]8
9#include "../init.h"
10#include "../sc-regs.h"
Masahiro Yamada1fe65d32015-09-22 00:27:41 +0900[diff] [blame]11
Masahiro Yamada98905692016-03-30 20:17:02 +0900[diff] [blame]12void uniphier_pxs2_clk_init(void)
Masahiro Yamada1fe65d32015-09-22 00:27:41 +0900[diff] [blame]13{
14 u32 tmp;
15
16 /* deassert reset */
Masahiro Yamadac84024c2019-07-10 20:07:41 +0900[diff] [blame]17 tmp = readl(sc_base + SC_RSTCTRL);
Masahiro Yamada260eda22017-10-14 02:21:17 +0900[diff] [blame]18#ifdef CONFIG_USB_DWC3_UNIPHIER
Masahiro Yamada1fe65d32015-09-22 00:27:41 +0900[diff] [blame]19 tmp |= SC_RSTCTRL_NRST_USB3B0 | SC_RSTCTRL_NRST_GIO;
20#endif
Masahiro Yamada1fe65d32015-09-22 00:27:41 +0900[diff] [blame]21#ifdef CONFIG_NAND_DENALI
22 tmp |= SC_RSTCTRL_NRST_NAND;
23#endif
Masahiro Yamadac84024c2019-07-10 20:07:41 +0900[diff] [blame]24 writel(tmp, sc_base + SC_RSTCTRL);
25 readl(sc_base + SC_RSTCTRL); /* dummy read */
Masahiro Yamada1fe65d32015-09-22 00:27:41 +0900[diff] [blame]26
Masahiro Yamada260eda22017-10-14 02:21:17 +0900[diff] [blame]27#ifdef CONFIG_USB_DWC3_UNIPHIER
Masahiro Yamadac84024c2019-07-10 20:07:41 +0900[diff] [blame]28 tmp = readl(sc_base + SC_RSTCTRL2);
Masahiro Yamada1fe65d32015-09-22 00:27:41 +0900[diff] [blame]29 tmp |= SC_RSTCTRL2_NRST_USB3B1;
Masahiro Yamadac84024c2019-07-10 20:07:41 +0900[diff] [blame]30 writel(tmp, sc_base + SC_RSTCTRL2);
31 readl(sc_base + SC_RSTCTRL2); /* dummy read */
Masahiro Yamada85ab6072016-07-22 20:20:11 +0900[diff] [blame]32
Masahiro Yamadac84024c2019-07-10 20:07:41 +0900[diff] [blame]33 tmp = readl(sc_base + SC_RSTCTRL6);
Masahiro Yamada85ab6072016-07-22 20:20:11 +0900[diff] [blame]34 tmp |= 0x37;
Masahiro Yamadac84024c2019-07-10 20:07:41 +0900[diff] [blame]35 writel(tmp, sc_base + SC_RSTCTRL6);
Masahiro Yamada1fe65d32015-09-22 00:27:41 +0900[diff] [blame]36#endif
37
Masahiro Yamada1c6a5e42016-03-30 20:17:42 +0900[diff] [blame]38 /* provide clocks */
Masahiro Yamadac84024c2019-07-10 20:07:41 +0900[diff] [blame]39 tmp = readl(sc_base + SC_CLKCTRL);
Masahiro Yamada260eda22017-10-14 02:21:17 +0900[diff] [blame]40#ifdef CONFIG_USB_DWC3_UNIPHIER
Masahiro Yamada85ab6072016-07-22 20:20:11 +0900[diff] [blame]41 tmp |= BIT(20) | BIT(19) | SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 |
Masahiro Yamada1fe65d32015-09-22 00:27:41 +0900[diff] [blame]42 SC_CLKCTRL_CEN_GIO;
43#endif
Masahiro Yamada1fe65d32015-09-22 00:27:41 +0900[diff] [blame]44#ifdef CONFIG_NAND_DENALI
45 tmp |= SC_CLKCTRL_CEN_NAND;
46#endif
Masahiro Yamadac84024c2019-07-10 20:07:41 +0900[diff] [blame]47 writel(tmp, sc_base + SC_CLKCTRL);
48 readl(sc_base + SC_CLKCTRL); /* dummy read */
Masahiro Yamada1fe65d32015-09-22 00:27:41 +0900[diff] [blame]49}