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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Michal Simeke60148d2014-01-14 14:21:52 +01002/*
Michal Simek98d0f1f2018-01-17 07:37:47 +01003 * (C) Copyright 2014 - 2017 Xilinx, Inc. Michal Simek
Michal Simeke60148d2014-01-14 14:21:52 +01004 */
5#include <common.h>
Simon Glass091f6a32015-10-17 19:41:22 -06006#include <debug_uart.h>
Simon Glassf11478f2019-12-28 10:45:07 -07007#include <hang.h>
Simon Glass2dc9c342020-05-10 11:40:01 -06008#include <image.h>
Simon Glass97589732020-05-10 11:40:02 -06009#include <init.h>
Simon Glass0f2af882020-05-10 11:40:05 -060010#include <log.h>
Michal Simeke60148d2014-01-14 14:21:52 +010011#include <spl.h>
12
13#include <asm/io.h>
Michal Simek162c6372014-08-11 14:03:15 +020014#include <asm/spl.h>
Simon Glass122216d2015-10-17 19:41:21 -060015#include <asm/arch/hardware.h>
Michal Simeke60148d2014-01-14 14:21:52 +010016#include <asm/arch/sys_proto.h>
Michal Simek85dc76a2017-11-08 16:14:47 +010017#include <asm/arch/ps7_init_gpl.h>
Michal Simeke60148d2014-01-14 14:21:52 +010018
Michal Simek7659fe42022-02-17 14:28:41 +010019#if defined(CONFIG_DEBUG_UART_BOARD_INIT)
20void board_debug_uart_init(void)
21{
22 ps7_init();
23}
24#endif
25
Michal Simeke60148d2014-01-14 14:21:52 +010026void board_init_f(ulong dummy)
27{
Michal Simek7659fe42022-02-17 14:28:41 +010028#if !defined(CONFIG_DEBUG_UART_BOARD_INIT)
Michal Simeke60148d2014-01-14 14:21:52 +010029 ps7_init();
Michal Simek7659fe42022-02-17 14:28:41 +010030#endif
Michal Simeke60148d2014-01-14 14:21:52 +010031
Michal Simeke60148d2014-01-14 14:21:52 +010032 arch_cpu_init();
Michal Simeke60148d2014-01-14 14:21:52 +010033}
34
Michal Simeka831f1f2014-04-25 12:15:40 +020035#ifdef CONFIG_SPL_BOARD_INIT
36void spl_board_init(void)
37{
Simon Glasse04843d2015-10-19 06:50:02 -060038 preloader_console_init();
Michal Simek1aab1142020-09-09 14:41:56 +020039#if defined(CONFIG_ARCH_EARLY_INIT_R) && defined(CONFIG_SPL_FPGA)
Luis Araneda7d9405a2018-07-19 03:10:18 -040040 arch_early_init_r();
41#endif
Michal Simeka831f1f2014-04-25 12:15:40 +020042 board_init();
43}
44#endif
45
Michal Simeke60148d2014-01-14 14:21:52 +010046u32 spl_boot_device(void)
47{
48 u32 mode;
49
50 switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
Simon Glassa5820472021-08-08 12:20:14 -060051#ifdef CONFIG_SPL_SPI
Michal Simeke60148d2014-01-14 14:21:52 +010052 case ZYNQ_BM_QSPI:
Michal Simeke60148d2014-01-14 14:21:52 +010053 mode = BOOT_DEVICE_SPI;
54 break;
55#endif
Michal Simek25830022015-01-13 16:04:10 +010056 case ZYNQ_BM_NAND:
57 mode = BOOT_DEVICE_NAND;
58 break;
59 case ZYNQ_BM_NOR:
60 mode = BOOT_DEVICE_NOR;
61 break;
Simon Glassb58bfe02021-08-08 12:20:09 -060062#ifdef CONFIG_SPL_MMC
Michal Simeke60148d2014-01-14 14:21:52 +010063 case ZYNQ_BM_SD:
Michal Simeke60148d2014-01-14 14:21:52 +010064 mode = BOOT_DEVICE_MMC1;
65 break;
66#endif
Michal Simek25830022015-01-13 16:04:10 +010067 case ZYNQ_BM_JTAG:
68 mode = BOOT_DEVICE_RAM;
69 break;
Michal Simeke60148d2014-01-14 14:21:52 +010070 default:
71 puts("Unsupported boot mode selected\n");
72 hang();
73 }
74
75 return mode;
76}
77
Michal Simeke60148d2014-01-14 14:21:52 +010078#ifdef CONFIG_SPL_OS_BOOT
79int spl_start_uboot(void)
80{
81 /* boot linux */
82 return 0;
83}
84#endif
Masahiro Yamadac2d10792014-05-12 12:18:30 +090085
Michal Simek42c8c412016-05-10 07:55:52 +020086void spl_board_prepare_for_boot(void)
87{
88 ps7_post_config();
89 debug("SPL bye\n");
90}