blob: 72944af18a40b96f1f50ff4dd6ad163fcafb15ac [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Jason Liudec11122011-11-25 00:18:02 +00002/*
3 * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
Jason Liudec11122011-11-25 00:18:02 +00004 */
5
6#ifndef __ASM_ARCH_MX6_IMX_REGS_H__
7#define __ASM_ARCH_MX6_IMX_REGS_H__
8
Benoît Thébaudeau1da8a7b2012-08-13 07:27:58 +00009#define ARCH_MXC
10
Jason Liudec11122011-11-25 00:18:02 +000011#define ROMCP_ARB_BASE_ADDR 0x00000000
12#define ROMCP_ARB_END_ADDR 0x000FFFFF
Fabio Estevamf7b9ac22013-04-10 09:32:57 +000013
14#ifdef CONFIG_MX6SL
15#define GPU_2D_ARB_BASE_ADDR 0x02200000
16#define GPU_2D_ARB_END_ADDR 0x02203FFF
17#define OPENVG_ARB_BASE_ADDR 0x02204000
18#define OPENVG_ARB_END_ADDR 0x02207FFF
Fabio Estevam1b691df2018-01-03 12:33:05 -020019#elif (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
Fabio Estevam712ab882014-06-24 17:40:58 -030020#define CAAM_ARB_BASE_ADDR 0x00100000
21#define CAAM_ARB_END_ADDR 0x00107FFF
22#define GPU_ARB_BASE_ADDR 0x01800000
23#define GPU_ARB_END_ADDR 0x01803FFF
24#define APBH_DMA_ARB_BASE_ADDR 0x01804000
25#define APBH_DMA_ARB_END_ADDR 0x0180BFFF
26#define M4_BOOTROM_BASE_ADDR 0x007F8000
27
Peng Fan06c46a02016-12-11 19:24:22 +080028#elif !defined(CONFIG_MX6SLL)
Jason Liudec11122011-11-25 00:18:02 +000029#define CAAM_ARB_BASE_ADDR 0x00100000
30#define CAAM_ARB_END_ADDR 0x00103FFF
31#define APBH_DMA_ARB_BASE_ADDR 0x00110000
32#define APBH_DMA_ARB_END_ADDR 0x00117FFF
33#define HDMI_ARB_BASE_ADDR 0x00120000
34#define HDMI_ARB_END_ADDR 0x00128FFF
35#define GPU_3D_ARB_BASE_ADDR 0x00130000
36#define GPU_3D_ARB_END_ADDR 0x00133FFF
37#define GPU_2D_ARB_BASE_ADDR 0x00134000
38#define GPU_2D_ARB_END_ADDR 0x00137FFF
39#define DTCP_ARB_BASE_ADDR 0x00138000
40#define DTCP_ARB_END_ADDR 0x0013BFFF
Fabio Estevamf7b9ac22013-04-10 09:32:57 +000041#endif /* CONFIG_MX6SL */
Stefan Roese412e0462013-04-09 21:06:09 +000042
43#define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR
44#define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000)
45#define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000)
46
Jason Liudec11122011-11-25 00:18:02 +000047/* GPV - PL301 configuration ports */
Fabio Estevam1b691df2018-01-03 12:33:05 -020048#if (defined(CONFIG_MX6SX) || \
49 defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
Peng Fan06c46a02016-12-11 19:24:22 +080050 defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL))
Fabio Estevamf7b9ac22013-04-10 09:32:57 +000051#define GPV2_BASE_ADDR 0x00D00000
Fabio Estevam712ab882014-06-24 17:40:58 -030052#define GPV3_BASE_ADDR 0x00E00000
53#define GPV4_BASE_ADDR 0x00F00000
54#define GPV5_BASE_ADDR 0x01000000
55#define GPV6_BASE_ADDR 0x01100000
56#define PCIE_ARB_BASE_ADDR 0x08000000
57#define PCIE_ARB_END_ADDR 0x08FFFFFF
58
59#else
Peng Fan06c46a02016-12-11 19:24:22 +080060#define GPV2_BASE_ADDR 0x00200000
Jason Liudec11122011-11-25 00:18:02 +000061#define GPV3_BASE_ADDR 0x00300000
62#define GPV4_BASE_ADDR 0x00800000
Fabio Estevam712ab882014-06-24 17:40:58 -030063#define PCIE_ARB_BASE_ADDR 0x01000000
64#define PCIE_ARB_END_ADDR 0x01FFFFFF
65#endif
66
Jason Liudec11122011-11-25 00:18:02 +000067#define IRAM_BASE_ADDR 0x00900000
68#define SCU_BASE_ADDR 0x00A00000
69#define IC_INTERFACES_BASE_ADDR 0x00A00100
70#define GLOBAL_TIMER_BASE_ADDR 0x00A00200
71#define PRIVATE_TIMERS_WD_BASE_ADDR 0x00A00600
72#define IC_DISTRIBUTOR_BASE_ADDR 0x00A01000
Fabio Estevam13409292014-01-29 17:39:49 -020073#define L2_PL310_BASE 0x00A02000
Jason Liudec11122011-11-25 00:18:02 +000074#define GPV0_BASE_ADDR 0x00B00000
75#define GPV1_BASE_ADDR 0x00C00000
Jason Liudec11122011-11-25 00:18:02 +000076
77#define AIPS1_ARB_BASE_ADDR 0x02000000
78#define AIPS1_ARB_END_ADDR 0x020FFFFF
79#define AIPS2_ARB_BASE_ADDR 0x02100000
80#define AIPS2_ARB_END_ADDR 0x021FFFFF
Peng Fan59e680d2015-07-20 19:28:23 +080081/* AIPS3 only on i.MX6SX */
Ye.Li00cce362015-01-14 17:18:12 +080082#define AIPS3_ARB_BASE_ADDR 0x02200000
83#define AIPS3_ARB_END_ADDR 0x022FFFFF
Peng Fan59e680d2015-07-20 19:28:23 +080084#ifdef CONFIG_MX6SX
Fabio Estevam712ab882014-06-24 17:40:58 -030085#define WEIM_ARB_BASE_ADDR 0x50000000
86#define WEIM_ARB_END_ADDR 0x57FFFFFF
Peng Fan828e4682014-12-31 11:01:38 +080087#define QSPI0_AMBA_BASE 0x60000000
88#define QSPI0_AMBA_END 0x6FFFFFFF
89#define QSPI1_AMBA_BASE 0x70000000
90#define QSPI1_AMBA_END 0x7FFFFFFF
Fabio Estevam1b691df2018-01-03 12:33:05 -020091#elif (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
Peng Fan59e680d2015-07-20 19:28:23 +080092#define WEIM_ARB_BASE_ADDR 0x50000000
93#define WEIM_ARB_END_ADDR 0x57FFFFFF
94#define QSPI0_AMBA_BASE 0x60000000
95#define QSPI0_AMBA_END 0x6FFFFFFF
Peng Fan06c46a02016-12-11 19:24:22 +080096#elif !defined(CONFIG_MX6SLL)
Jason Liudec11122011-11-25 00:18:02 +000097#define SATA_ARB_BASE_ADDR 0x02200000
98#define SATA_ARB_END_ADDR 0x02203FFF
99#define OPENVG_ARB_BASE_ADDR 0x02204000
100#define OPENVG_ARB_END_ADDR 0x02207FFF
101#define HSI_ARB_BASE_ADDR 0x02208000
102#define HSI_ARB_END_ADDR 0x0220BFFF
103#define IPU1_ARB_BASE_ADDR 0x02400000
104#define IPU1_ARB_END_ADDR 0x027FFFFF
105#define IPU2_ARB_BASE_ADDR 0x02800000
106#define IPU2_ARB_END_ADDR 0x02BFFFFF
107#define WEIM_ARB_BASE_ADDR 0x08000000
108#define WEIM_ARB_END_ADDR 0x0FFFFFFF
Fabio Estevam712ab882014-06-24 17:40:58 -0300109#endif
Jason Liudec11122011-11-25 00:18:02 +0000110
Peng Fan06c46a02016-12-11 19:24:22 +0800111#if (defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL) || \
Fabio Estevam1b691df2018-01-03 12:33:05 -0200112 defined(CONFIG_MX6SX) || \
113 defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
Fabio Estevamf7b9ac22013-04-10 09:32:57 +0000114#define MMDC0_ARB_BASE_ADDR 0x80000000
115#define MMDC0_ARB_END_ADDR 0xFFFFFFFF
116#define MMDC1_ARB_BASE_ADDR 0xC0000000
117#define MMDC1_ARB_END_ADDR 0xFFFFFFFF
118#else
Jason Liudec11122011-11-25 00:18:02 +0000119#define MMDC0_ARB_BASE_ADDR 0x10000000
120#define MMDC0_ARB_END_ADDR 0x7FFFFFFF
121#define MMDC1_ARB_BASE_ADDR 0x80000000
122#define MMDC1_ARB_END_ADDR 0xFFFFFFFF
Fabio Estevamf7b9ac22013-04-10 09:32:57 +0000123#endif
Jason Liudec11122011-11-25 00:18:02 +0000124
Fabio Estevam712ab882014-06-24 17:40:58 -0300125#ifndef CONFIG_MX6SX
Fabio Estevama0005af2012-05-31 07:23:55 +0000126#define IPU_SOC_BASE_ADDR IPU1_ARB_BASE_ADDR
127#define IPU_SOC_OFFSET 0x00200000
Fabio Estevam712ab882014-06-24 17:40:58 -0300128#endif
Fabio Estevama0005af2012-05-31 07:23:55 +0000129
Jason Liudec11122011-11-25 00:18:02 +0000130/* Defines for Blocks connected via AIPS (SkyBlue) */
131#define ATZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR
132#define ATZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR
Adrian Alonsoee7c4ca2015-09-02 13:54:15 -0500133#define ATZ3_BASE_ADDR AIPS3_ARB_BASE_ADDR
Jason Liudec11122011-11-25 00:18:02 +0000134#define AIPS1_BASE_ADDR AIPS1_ON_BASE_ADDR
135#define AIPS2_BASE_ADDR AIPS2_ON_BASE_ADDR
Adrian Alonsoee7c4ca2015-09-02 13:54:15 -0500136#define AIPS3_BASE_ADDR AIPS3_ON_BASE_ADDR
Jason Liudec11122011-11-25 00:18:02 +0000137
138#define SPDIF_BASE_ADDR (ATZ1_BASE_ADDR + 0x04000)
139#define ECSPI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x08000)
140#define ECSPI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x0C000)
141#define ECSPI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x10000)
142#define ECSPI4_BASE_ADDR (ATZ1_BASE_ADDR + 0x14000)
Peng Fan06c46a02016-12-11 19:24:22 +0800143
144#define MX6SL_UART5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
145#define MX6SLL_UART4_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
146#define MX6UL_UART7_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
147#define MX6SL_UART2_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
148#define MX6SLL_UART2_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
149#define MX6UL_UART8_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
150#define MX6SL_UART3_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000)
151#define MX6SLL_UART3_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000)
152#define MX6SL_UART4_BASE_ADDR (ATZ1_BASE_ADDR + 0x38000)
153
Fabio Estevam712ab882014-06-24 17:40:58 -0300154#ifndef CONFIG_MX6SX
Jason Liudec11122011-11-25 00:18:02 +0000155#define ECSPI5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
Fabio Estevam712ab882014-06-24 17:40:58 -0300156#endif
Peng Fan06c46a02016-12-11 19:24:22 +0800157#define UART1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x20000)
Jason Liudec11122011-11-25 00:18:02 +0000158#define UART1_BASE (ATZ1_BASE_ADDR + 0x20000)
159#define ESAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
Stefan Roeseb16a2e32016-02-10 11:41:25 +0100160#define UART8_BASE (ATZ1_BASE_ADDR + 0x24000)
Jason Liudec11122011-11-25 00:18:02 +0000161#define SSI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000)
162#define SSI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000)
163#define SSI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000)
164#define ASRC_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000)
Fabio Estevamf7b9ac22013-04-10 09:32:57 +0000165
Fabio Estevam712ab882014-06-24 17:40:58 -0300166#ifndef CONFIG_MX6SX
Jason Liudec11122011-11-25 00:18:02 +0000167#define SPBA_BASE_ADDR (ATZ1_BASE_ADDR + 0x3C000)
168#define VPU_BASE_ADDR (ATZ1_BASE_ADDR + 0x40000)
Fabio Estevam712ab882014-06-24 17:40:58 -0300169#endif
Jason Liudec11122011-11-25 00:18:02 +0000170#define AIPS1_ON_BASE_ADDR (ATZ1_BASE_ADDR + 0x7C000)
171
172#define AIPS1_OFF_BASE_ADDR (ATZ1_BASE_ADDR + 0x80000)
173#define PWM1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x0000)
174#define PWM2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4000)
175#define PWM3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x8000)
176#define PWM4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0xC000)
177#define CAN1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x10000)
178#define CAN2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x14000)
Peng Fan06c46a02016-12-11 19:24:22 +0800179/* QOSC on i.MX6SLL */
180#define QOSC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x14000)
Jason Liudec11122011-11-25 00:18:02 +0000181#define GPT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x18000)
182#define GPIO1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x1C000)
183#define GPIO2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x20000)
184#define GPIO3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x24000)
185#define GPIO4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x28000)
186#define GPIO5_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x2C000)
Peng Fan1d5229a2016-08-11 14:02:51 +0800187#define MX6UL_SNVS_LP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000)
Jason Liudec11122011-11-25 00:18:02 +0000188#define GPIO6_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000)
189#define GPIO7_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000)
190#define KPP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x38000)
191#define WDOG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x3C000)
192#define WDOG2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x40000)
Wolfgang Grandegger1859b702012-02-08 22:33:25 +0000193#define ANATOP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x48000)
194#define USB_PHY0_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x49000)
195#define USB_PHY1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4a000)
Jason Liudec11122011-11-25 00:18:02 +0000196#define CCM_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x44000)
Jason Liudec11122011-11-25 00:18:02 +0000197#define SNVS_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4C000)
198#define EPIT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x50000)
199#define EPIT2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x54000)
200#define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x58000)
201#define GPC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x5C000)
202#define IOMUXC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x60000)
Peng Fan06c46a02016-12-11 19:24:22 +0800203#define IOMUXC_GPR_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000)
204#ifdef CONFIG_MX6SLL
205#define CSI_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
206#define SDMA_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
207#define PXP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x70000)
208#define EPDC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x74000)
209#define DCP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x7C000)
210#elif defined(CONFIG_MX6SL)
Fabio Estevamf7b9ac22013-04-10 09:32:57 +0000211#define CSI_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000)
212#define SIPIX_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
213#define SDMA_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
Peng Fan06c46a02016-12-11 19:24:22 +0800214#elif defined(CONFIG_MX6SX)
Fabio Estevam712ab882014-06-24 17:40:58 -0300215#define CANFD1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
216#define SDMA_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
217#define CANFD2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x70000)
218#define SEMAPHORE1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x74000)
219#define SEMAPHORE2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x78000)
220#define RDC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x7C000)
Fabio Estevamf7b9ac22013-04-10 09:32:57 +0000221#else
Jason Liudec11122011-11-25 00:18:02 +0000222#define DCIC1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000)
223#define DCIC2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
224#define DMA_REQ_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
Fabio Estevamf7b9ac22013-04-10 09:32:57 +0000225#endif
Jason Liudec11122011-11-25 00:18:02 +0000226
Peng Fan06c46a02016-12-11 19:24:22 +0800227#define MX6SL_LCDIF_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x78000)
228#define MX6SLL_LCDIF_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x78000)
229
Jason Liudec11122011-11-25 00:18:02 +0000230#define AIPS2_ON_BASE_ADDR (ATZ2_BASE_ADDR + 0x7C000)
231#define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000)
Adrian Alonsoee7c4ca2015-09-02 13:54:15 -0500232#define AIPS3_ON_BASE_ADDR (ATZ3_BASE_ADDR + 0x7C000)
233#define AIPS3_OFF_BASE_ADDR (ATZ3_BASE_ADDR + 0x80000)
Anatolij Gustschinf30e3b22018-01-11 15:14:17 +0100234#if defined(CONFIG_MX6UL)
235#define CAAM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000)
236#else
Jason Liudec11122011-11-25 00:18:02 +0000237#define CAAM_BASE_ADDR (ATZ2_BASE_ADDR)
Anatolij Gustschinf30e3b22018-01-11 15:14:17 +0100238#endif
Jason Liudec11122011-11-25 00:18:02 +0000239#define ARM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000)
Raul Cardenasb5a36d82015-02-27 11:22:06 -0600240
Tom Rini376b88a2022-10-28 20:27:13 -0400241#define CFG_SYS_FSL_SEC_OFFSET 0
242#define CFG_SYS_FSL_SEC_ADDR (CAAM_BASE_ADDR + \
243 CFG_SYS_FSL_SEC_OFFSET)
244#define CFG_SYS_FSL_JR0_OFFSET 0x1000
245#define CFG_SYS_FSL_JR0_ADDR (CAAM_BASE_ADDR + \
246 CFG_SYS_FSL_JR0_OFFSET)
Raul Cardenasb5a36d82015-02-27 11:22:06 -0600247
Ye.Lif93453a2014-09-15 17:23:14 +0800248#define USB_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000)
249#define USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000)
Fabio Estevamf7b9ac22013-04-10 09:32:57 +0000250
Jason Liudec11122011-11-25 00:18:02 +0000251#define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000)
Fabio Estevamf7b9ac22013-04-10 09:32:57 +0000252#ifdef CONFIG_MX6SL
253#define MSHC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
254#else
Jason Liudec11122011-11-25 00:18:02 +0000255#define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
Fabio Estevamf7b9ac22013-04-10 09:32:57 +0000256#endif
257
Jason Liudec11122011-11-25 00:18:02 +0000258#define USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x10000)
259#define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000)
260#define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000)
261#define USDHC4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000)
262#define I2C1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x20000)
263#define I2C2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x24000)
264#define I2C3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x28000)
265#define ROMCP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x2C000)
266#define MMDC_P0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x30000)
Peng Fan06c46a02016-12-11 19:24:22 +0800267/* i.MX6SL/SLL */
Fabio Estevamf7b9ac22013-04-10 09:32:57 +0000268#define RNGB_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
Fabio Estevam1b691df2018-01-03 12:33:05 -0200269#if (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
Peng Fan59e680d2015-07-20 19:28:23 +0800270#define ENET2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000)
Fabio Estevamf7b9ac22013-04-10 09:32:57 +0000271#else
Peng Fan59e680d2015-07-20 19:28:23 +0800272/* i.MX6SX */
273#define ENET2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
Fabio Estevamf7b9ac22013-04-10 09:32:57 +0000274#endif
Peng Fan59e680d2015-07-20 19:28:23 +0800275/* i.MX6DQ/SDL */
276#define MMDC_P1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
Fabio Estevamf7b9ac22013-04-10 09:32:57 +0000277
Jason Liudec11122011-11-25 00:18:02 +0000278#define WEIM_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x38000)
279#define OCOTP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x3C000)
280#define CSU_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x40000)
Peng Fan06c46a02016-12-11 19:24:22 +0800281#ifdef CONFIG_MX6SLL
282#define IOMUXC_GPR_SNVS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000)
283#define IOMUXC_SNVS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000)
284#endif
Jason Liudec11122011-11-25 00:18:02 +0000285#define IP2APB_PERFMON1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000)
286#define IP2APB_PERFMON2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000)
Peng Fan7f323212015-10-29 15:54:45 +0800287#define MX6UL_LCDIF1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000)
Peng Fanfb4deaf2016-08-11 14:02:48 +0800288#define MX6ULL_LCDIF1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000)
Fabio Estevam712ab882014-06-24 17:40:58 -0300289#ifdef CONFIG_MX6SX
290#define DEBUG_MONITOR_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000)
291#else
Jason Liudec11122011-11-25 00:18:02 +0000292#define IP2APB_PERFMON3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000)
Fabio Estevam712ab882014-06-24 17:40:58 -0300293#endif
Jason Liudec11122011-11-25 00:18:02 +0000294#define IP2APB_TZASC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x50000)
Fabio Estevam1b691df2018-01-03 12:33:05 -0200295#if (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
Stefan Agnerbe8b7c52018-01-05 15:08:19 +0100296#define SCTR_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000)
Peng Fan59e680d2015-07-20 19:28:23 +0800297#define QSPI0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
Fabio Estevamabd67762016-04-18 09:56:15 -0300298#define UART6_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000)
Peng Fan59e680d2015-07-20 19:28:23 +0800299#elif defined(CONFIG_MX6SX)
Fabio Estevam712ab882014-06-24 17:40:58 -0300300#define SAI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000)
Jason Liudec11122011-11-25 00:18:02 +0000301#define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000)
Fabio Estevam712ab882014-06-24 17:40:58 -0300302#define SAI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000)
Peng Fan828e4682014-12-31 11:01:38 +0800303#define QSPI0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
304#define QSPI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
Fabio Estevam712ab882014-06-24 17:40:58 -0300305#else
Peng Fan59e680d2015-07-20 19:28:23 +0800306#define IP2APB_TZASC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000)
Jason Liudec11122011-11-25 00:18:02 +0000307#define MIPI_CSI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000)
308#define MIPI_DSI_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
309#define VDOA_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
Fabio Estevam712ab882014-06-24 17:40:58 -0300310#endif
Peng Fan59e680d2015-07-20 19:28:23 +0800311#define MX6UL_WDOG3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
Jason Liudec11122011-11-25 00:18:02 +0000312#define UART2_BASE (AIPS2_OFF_BASE_ADDR + 0x68000)
313#define UART3_BASE (AIPS2_OFF_BASE_ADDR + 0x6C000)
314#define UART4_BASE (AIPS2_OFF_BASE_ADDR + 0x70000)
315#define UART5_BASE (AIPS2_OFF_BASE_ADDR + 0x74000)
Heiko Schocher5c4b1e92015-05-18 10:56:24 +0200316#define I2C4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000)
Jason Liudec11122011-11-25 00:18:02 +0000317#define IP2APB_USBPHY1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000)
318#define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000)
Peng Fan06c46a02016-12-11 19:24:22 +0800319/* i.MX6SLL */
320#define MTR_MASTER_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000)
Jason Liudec11122011-11-25 00:18:02 +0000321
Fabio Estevam712ab882014-06-24 17:40:58 -0300322#ifdef CONFIG_MX6SX
323#define GIS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x04000)
324#define DCIC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x0C000)
325#define DCIC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x10000)
326#define CSI1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x14000)
327#define PXP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x18000)
328#define CSI2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x1C000)
Fabio Estevam712ab882014-06-24 17:40:58 -0300329#define VADC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x28000)
330#define VDEC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x2C000)
331#define SPBA_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x3C000)
332#define AIPS3_CONFIG_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x7C000)
333#define ADC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x80000)
334#define ADC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x84000)
Fabio Estevam712ab882014-06-24 17:40:58 -0300335#define ECSPI5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x8C000)
336#define HS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x90000)
337#define MU_MCU_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x94000)
338#define CANFD_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x98000)
339#define MU_DSP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x9C000)
340#define UART6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA0000)
341#define PWM5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA4000)
342#define PWM6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA8000)
343#define PWM7_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xAC000)
344#define PWM8_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xB0000)
Fabio Estevam1b691df2018-01-03 12:33:05 -0200345#elif (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
Peng Fanfb4deaf2016-08-11 14:02:48 +0800346#define AIPS3_CONFIG_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x7C000)
347#define DCP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x80000)
348#define RNGB_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x84000)
349#define UART8_IPS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000)
350#define EPDC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x8C000)
351#define IOMUXC_SNVS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x90000)
352#define SNVS_GPR_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x94000)
Fabio Estevam712ab882014-06-24 17:40:58 -0300353#endif
Fabio Estevama48538c2017-10-14 09:17:54 -0300354
355#define NOC_DDR_BASE_ADDR (GPV0_BASE_ADDR + 0xB0000)
356
Peng Fan7f323212015-10-29 15:54:45 +0800357/* Only for i.MX6SX */
358#define LCDIF2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x24000)
359#define MX6SX_LCDIF1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x20000)
Peng Fan59e680d2015-07-20 19:28:23 +0800360#define MX6SX_WDOG3_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000)
361
Fabio Estevam1b691df2018-01-03 12:33:05 -0200362#if !(defined(CONFIG_MX6SX) || \
363 defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
Peng Fan06c46a02016-12-11 19:24:22 +0800364 defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL))
Jason Liudec11122011-11-25 00:18:02 +0000365#define IRAM_SIZE 0x00040000
Fabio Estevam712ab882014-06-24 17:40:58 -0300366#else
367#define IRAM_SIZE 0x00020000
368#endif
Troy Kisky01112132012-02-07 14:08:46 +0000369#define FEC_QUIRK_ENET_MAC
Jason Liudec11122011-11-25 00:18:02 +0000370
Stefano Babic33731bc2017-06-29 10:16:06 +0200371#include <asm/mach-imx/regs-lcdif.h>
Jason Liudec11122011-11-25 00:18:02 +0000372#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
373#include <asm/types.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -0600374#include <linux/bitops.h>
Jason Liudec11122011-11-25 00:18:02 +0000375
Peng Fan7f323212015-10-29 15:54:45 +0800376/* only for i.MX6SX/UL */
Fabio Estevam27b0fc32017-11-23 09:18:53 -0200377#define WDOG3_BASE_ADDR (((is_mx6ul() || is_mx6ull()) ? \
Peng Fanf0d3fbf2015-11-30 16:04:51 +0800378 MX6UL_WDOG3_BASE_ADDR : MX6SX_WDOG3_BASE_ADDR))
Peng Fan06c46a02016-12-11 19:24:22 +0800379#define LCDIF1_BASE_ADDR ((is_cpu_type(MXC_CPU_MX6SLL)) ? \
380 MX6SLL_LCDIF_BASE_ADDR : \
381 (is_cpu_type(MXC_CPU_MX6SL)) ? \
382 MX6SL_LCDIF_BASE_ADDR : \
383 ((is_cpu_type(MXC_CPU_MX6UL)) ? \
Peng Fanfb4deaf2016-08-11 14:02:48 +0800384 MX6UL_LCDIF1_BASE_ADDR : \
385 ((is_mx6ull()) ? \
Peng Fan06c46a02016-12-11 19:24:22 +0800386 MX6ULL_LCDIF1_BASE_ADDR : MX6SX_LCDIF1_BASE_ADDR)))
Peng Fan7f323212015-10-29 15:54:45 +0800387
388
Fabio Estevam04fc1282011-12-20 05:46:31 +0000389extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
Jason Liudec11122011-11-25 00:18:02 +0000390
Gabriel Huau170ceaf2014-07-26 11:35:43 -0700391#define SRC_SCR_CORE_1_RESET_OFFSET 14
392#define SRC_SCR_CORE_1_RESET_MASK (1<<SRC_SCR_CORE_1_RESET_OFFSET)
393#define SRC_SCR_CORE_2_RESET_OFFSET 15
394#define SRC_SCR_CORE_2_RESET_MASK (1<<SRC_SCR_CORE_2_RESET_OFFSET)
395#define SRC_SCR_CORE_3_RESET_OFFSET 16
396#define SRC_SCR_CORE_3_RESET_MASK (1<<SRC_SCR_CORE_3_RESET_OFFSET)
397#define SRC_SCR_CORE_1_ENABLE_OFFSET 22
398#define SRC_SCR_CORE_1_ENABLE_MASK (1<<SRC_SCR_CORE_1_ENABLE_OFFSET)
399#define SRC_SCR_CORE_2_ENABLE_OFFSET 23
400#define SRC_SCR_CORE_2_ENABLE_MASK (1<<SRC_SCR_CORE_2_ENABLE_OFFSET)
401#define SRC_SCR_CORE_3_ENABLE_OFFSET 24
402#define SRC_SCR_CORE_3_ENABLE_MASK (1<<SRC_SCR_CORE_3_ENABLE_OFFSET)
403
Peng Fan42997432016-01-28 16:54:59 +0800404struct rdc_regs {
405 u32 vir; /* Version information */
406 u32 reserved1[8];
407 u32 stat; /* Status */
408 u32 intctrl; /* Interrupt and Control */
409 u32 intstat; /* Interrupt Status */
410 u32 reserved2[116];
411 u32 mda[32]; /* Master Domain Assignment */
412 u32 reserved3[96];
413 u32 pdap[104]; /* Peripheral Domain Access Permissions */
414 u32 reserved4[88];
415 struct {
416 u32 mrsa; /* Memory Region Start Address */
417 u32 mrea; /* Memory Region End Address */
418 u32 mrc; /* Memory Region Control */
419 u32 mrvs; /* Memory Region Violation Status */
420 } mem_region[55];
421};
422
423struct rdc_sema_regs {
424 u8 gate[64]; /* Gate */
425 u16 rstgt; /* Reset Gate */
426};
427
Fabio Estevamba613422014-11-14 11:27:22 -0200428/* WEIM registers */
429struct weim {
430 u32 cs0gcr1;
431 u32 cs0gcr2;
432 u32 cs0rcr1;
433 u32 cs0rcr2;
434 u32 cs0wcr1;
435 u32 cs0wcr2;
436
437 u32 cs1gcr1;
438 u32 cs1gcr2;
439 u32 cs1rcr1;
440 u32 cs1rcr2;
441 u32 cs1wcr1;
442 u32 cs1wcr2;
443
444 u32 cs2gcr1;
445 u32 cs2gcr2;
446 u32 cs2rcr1;
447 u32 cs2rcr2;
448 u32 cs2wcr1;
449 u32 cs2wcr2;
450
451 u32 cs3gcr1;
452 u32 cs3gcr2;
453 u32 cs3rcr1;
454 u32 cs3rcr2;
455 u32 cs3wcr1;
456 u32 cs3wcr2;
457
458 u32 unused[12];
459
460 u32 wcr;
461 u32 wiar;
462 u32 ear;
463};
464
Jason Liudec11122011-11-25 00:18:02 +0000465/* System Reset Controller (SRC) */
466struct src {
467 u32 scr;
468 u32 sbmr1;
469 u32 srsr;
470 u32 reserved1[2];
471 u32 sisr;
472 u32 simr;
473 u32 sbmr2;
474 u32 gpr1;
475 u32 gpr2;
476 u32 gpr3;
477 u32 gpr4;
478 u32 gpr5;
479 u32 gpr6;
480 u32 gpr7;
481 u32 gpr8;
482 u32 gpr9;
483 u32 gpr10;
484};
485
Jagan Tekic981a942017-02-24 15:45:15 +0530486#define src_base ((struct src *)SRC_BASE_ADDR)
487
Peng Fand7e46ca2018-01-10 13:20:32 +0800488#define SRC_M4_REG_OFFSET 0
489#define SRC_M4_ENABLE_OFFSET 22
490#define SRC_M4_ENABLE_MASK BIT(22)
491#define SRC_M4C_NON_SCLR_RST_OFFSET 4
492#define SRC_M4C_NON_SCLR_RST_MASK BIT(4)
Peng Fanfb3a3b72016-01-28 16:55:05 +0800493
Fabio Estevamf22d7592014-01-03 15:55:58 -0200494/* GPR1 bitfields */
Heiko Schocherff2b40d2015-09-25 12:31:48 +0200495#define IOMUXC_GPR1_APP_CLK_REQ_N BIT(30)
496#define IOMUXC_GPR1_PCIE_EXIT_L1 BIT(28)
497#define IOMUXC_GPR1_PCIE_RDY_L23 BIT(27)
498#define IOMUXC_GPR1_PCIE_ENTER_L1 BIT(26)
499#define IOMUXC_GPR1_MIPI_COLOR_SW BIT(25)
500#define IOMUXC_GPR1_DPI_OFF BIT(24)
501#define IOMUXC_GPR1_EXC_MON_SLVE BIT(22)
Fabio Estevamf22d7592014-01-03 15:55:58 -0200502#define IOMUXC_GPR1_ENET_CLK_SEL_OFFSET 21
503#define IOMUXC_GPR1_ENET_CLK_SEL_MASK (1 << IOMUXC_GPR1_ENET_CLK_SEL_OFFSET)
Heiko Schocherff2b40d2015-09-25 12:31:48 +0200504#define IOMUXC_GPR1_MIPI_IPU2_MUX_IOMUX BIT(20)
505#define IOMUXC_GPR1_MIPI_IPU1_MUX_IOMUX BIT(19)
506#define IOMUXC_GPR1_PCIE_TEST_PD BIT(18)
507#define IOMUXC_GPR1_IPU_VPU_MUX_IPU2 BIT(17)
508#define IOMUXC_GPR1_PCIE_REF_CLK_EN BIT(16)
509#define IOMUXC_GPR1_USB_EXP_MODE BIT(15)
510#define IOMUXC_GPR1_PCIE_INT BIT(14)
Heiko Schochera0230d82014-07-18 06:07:17 +0200511#define IOMUXC_GPR1_USB_OTG_ID_OFFSET 13
512#define IOMUXC_GPR1_USB_OTG_ID_SEL_MASK (1 << IOMUXC_GPR1_USB_OTG_ID_OFFSET)
Heiko Schocherff2b40d2015-09-25 12:31:48 +0200513#define IOMUXC_GPR1_GINT BIT(12)
514#define IOMUXC_GPR1_ADDRS3_MASK (0x3 << 10)
515#define IOMUXC_GPR1_ADDRS3_32MB (0x0 << 10)
516#define IOMUXC_GPR1_ADDRS3_64MB (0x1 << 10)
517#define IOMUXC_GPR1_ADDRS3_128MB (0x2 << 10)
518#define IOMUXC_GPR1_ACT_CS3 BIT(9)
519#define IOMUXC_GPR1_ADDRS2_MASK (0x3 << 7)
520#define IOMUXC_GPR1_ACT_CS2 BIT(6)
521#define IOMUXC_GPR1_ADDRS1_MASK (0x3 << 4)
522#define IOMUXC_GPR1_ACT_CS1 BIT(3)
523#define IOMUXC_GPR1_ADDRS0_OFFSET (1)
524#define IOMUXC_GPR1_ADDRS0_MASK (0x3 << 1)
525#define IOMUXC_GPR1_ACT_CS0 BIT(0)
Fabio Estevamf22d7592014-01-03 15:55:58 -0200526
Eric Nelsonadc8c382012-09-21 11:41:42 +0000527/* GPR3 bitfields */
528#define IOMUXC_GPR3_GPU_DBG_OFFSET 29
529#define IOMUXC_GPR3_GPU_DBG_MASK (3<<IOMUXC_GPR3_GPU_DBG_OFFSET)
530#define IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET 28
531#define IOMUXC_GPR3_BCH_WR_CACHE_CTL_MASK (1<<IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET)
532#define IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET 27
533#define IOMUXC_GPR3_BCH_RD_CACHE_CTL_MASK (1<<IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET)
534#define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET 26
535#define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_MASK (1<<IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET)
536#define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET 25
537#define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_MASK (1<<IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET)
538#define IOMUXC_GPR3_OCRAM_CTL_OFFSET 21
539#define IOMUXC_GPR3_OCRAM_CTL_MASK (0xf<<IOMUXC_GPR3_OCRAM_CTL_OFFSET)
540#define IOMUXC_GPR3_OCRAM_STATUS_OFFSET 17
541#define IOMUXC_GPR3_OCRAM_STATUS_MASK (0xf<<IOMUXC_GPR3_OCRAM_STATUS_OFFSET)
542#define IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET 16
543#define IOMUXC_GPR3_CORE3_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET)
544#define IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET 15
545#define IOMUXC_GPR3_CORE2_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET)
546#define IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET 14
547#define IOMUXC_GPR3_CORE1_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET)
548#define IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET 13
549#define IOMUXC_GPR3_CORE0_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET)
550#define IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET 12
551#define IOMUXC_GPR3_TZASC2_BOOT_LOCK_MASK (1<<IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET)
552#define IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET 11
553#define IOMUXC_GPR3_TZASC1_BOOT_LOCK_MASK (1<<IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET)
554#define IOMUXC_GPR3_IPU_DIAG_OFFSET 10
555#define IOMUXC_GPR3_IPU_DIAG_MASK (1<<IOMUXC_GPR3_IPU_DIAG_OFFSET)
556
557#define IOMUXC_GPR3_MUX_SRC_IPU1_DI0 0
558#define IOMUXC_GPR3_MUX_SRC_IPU1_DI1 1
559#define IOMUXC_GPR3_MUX_SRC_IPU2_DI0 2
560#define IOMUXC_GPR3_MUX_SRC_IPU2_DI1 3
561
562#define IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET 8
563#define IOMUXC_GPR3_LVDS1_MUX_CTL_MASK (3<<IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET)
564
565#define IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET 6
566#define IOMUXC_GPR3_LVDS0_MUX_CTL_MASK (3<<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET)
567
568#define IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET 4
569#define IOMUXC_GPR3_MIPI_MUX_CTL_MASK (3<<IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET)
570
571#define IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET 2
572#define IOMUXC_GPR3_HDMI_MUX_CTL_MASK (3<<IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET)
573
Heiko Schocherff2b40d2015-09-25 12:31:48 +0200574/* gpr12 bitfields */
575#define IOMUXC_GPR12_ARMP_IPG_CLK_EN BIT(27)
576#define IOMUXC_GPR12_ARMP_AHB_CLK_EN BIT(26)
577#define IOMUXC_GPR12_ARMP_ATB_CLK_EN BIT(25)
578#define IOMUXC_GPR12_ARMP_APB_CLK_EN BIT(24)
579#define IOMUXC_GPR12_DEVICE_TYPE (0xf << 12)
580#define IOMUXC_GPR12_PCIE_CTL_2 BIT(10)
581#define IOMUXC_GPR12_LOS_LEVEL (0x1f << 4)
Eric Nelsonadc8c382012-09-21 11:41:42 +0000582
Eric Nelson0c555872012-09-19 08:32:31 +0000583struct iomuxc {
Fabio Estevam1b691df2018-01-03 12:33:05 -0200584#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
Fabio Estevam72edac02014-07-09 17:59:55 -0300585 u8 reserved[0x4000];
586#endif
Eric Nelson0c555872012-09-19 08:32:31 +0000587 u32 gpr[14];
Eric Nelson0c555872012-09-19 08:32:31 +0000588};
589
Fabio Estevam1a5b0b42014-08-25 14:26:44 -0300590struct gpc {
591 u32 cntr;
592 u32 pgr;
593 u32 imr1;
594 u32 imr2;
595 u32 imr3;
596 u32 imr4;
597 u32 isr1;
598 u32 isr2;
599 u32 isr3;
600 u32 isr4;
601};
602
Eric Nelson0c555872012-09-19 08:32:31 +0000603#define IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET 20
604#define IOMUXC_GPR2_COUNTER_RESET_VAL_MASK (3<<IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET)
605#define IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET 16
606#define IOMUXC_GPR2_LVDS_CLK_SHIFT_MASK (7<<IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET)
607
608#define IOMUXC_GPR2_BGREF_RRMODE_OFFSET 15
609#define IOMUXC_GPR2_BGREF_RRMODE_MASK (1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
610#define IOMUXC_GPR2_BGREF_RRMODE_INTERNAL_RES (1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
611#define IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES (0<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
612#define IOMUXC_GPR2_VSYNC_ACTIVE_HIGH 0
613#define IOMUXC_GPR2_VSYNC_ACTIVE_LOW 1
614
615#define IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET 10
616#define IOMUXC_GPR2_DI1_VS_POLARITY_MASK (1<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
617#define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH (IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
618#define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW (IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
619
620#define IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET 9
621#define IOMUXC_GPR2_DI0_VS_POLARITY_MASK (1<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
622#define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH (IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
623#define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW (IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
624
625#define IOMUXC_GPR2_BITMAP_SPWG 0
626#define IOMUXC_GPR2_BITMAP_JEIDA 1
627
628#define IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET 8
629#define IOMUXC_GPR2_BIT_MAPPING_CH1_MASK (1<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
630#define IOMUXC_GPR2_BIT_MAPPING_CH1_JEIDA (IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
631#define IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG (IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
632
633#define IOMUXC_GPR2_DATA_WIDTH_18 0
634#define IOMUXC_GPR2_DATA_WIDTH_24 1
635
636#define IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET 7
637#define IOMUXC_GPR2_DATA_WIDTH_CH1_MASK (1<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
638#define IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT (IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
639#define IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT (IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
640
641#define IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET 6
642#define IOMUXC_GPR2_BIT_MAPPING_CH0_MASK (1<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
643#define IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA (IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
644#define IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG (IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
645
646#define IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET 5
647#define IOMUXC_GPR2_DATA_WIDTH_CH0_MASK (1<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
648#define IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT (IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
649#define IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT (IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
650
651#define IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET 4
652#define IOMUXC_GPR2_SPLIT_MODE_EN_MASK (1<<IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET)
653
654#define IOMUXC_GPR2_MODE_DISABLED 0
655#define IOMUXC_GPR2_MODE_ENABLED_DI0 1
Pierre Aubert7f5746b2013-06-19 11:16:13 +0200656#define IOMUXC_GPR2_MODE_ENABLED_DI1 3
Eric Nelson0c555872012-09-19 08:32:31 +0000657
658#define IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET 2
659#define IOMUXC_GPR2_LVDS_CH1_MODE_MASK (3<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
660#define IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED (IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
661#define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
662#define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI1 (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
663
664#define IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET 0
665#define IOMUXC_GPR2_LVDS_CH0_MODE_MASK (3<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
666#define IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED (IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
667#define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
668#define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI1 (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
669
Eric Nelson32565c52012-01-31 07:52:04 +0000670/*
671 * CSPI register definitions
672 */
Heiko Schocher472a68f2014-07-18 06:07:20 +0200673#define SPI_MAX_NUM 4
Peng Fan06c46a02016-12-11 19:24:22 +0800674#if defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL) || \
Fabio Estevam1b691df2018-01-03 12:33:05 -0200675 defined(CONFIG_MX6DL) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
Fabio Estevamf7b9ac22013-04-10 09:32:57 +0000676#define MXC_SPI_BASE_ADDRESSES \
677 ECSPI1_BASE_ADDR, \
678 ECSPI2_BASE_ADDR, \
679 ECSPI3_BASE_ADDR, \
680 ECSPI4_BASE_ADDR
681#else
Eric Nelson32565c52012-01-31 07:52:04 +0000682#define MXC_SPI_BASE_ADDRESSES \
683 ECSPI1_BASE_ADDR, \
684 ECSPI2_BASE_ADDR, \
685 ECSPI3_BASE_ADDR, \
686 ECSPI4_BASE_ADDR, \
687 ECSPI5_BASE_ADDR
Fabio Estevamf7b9ac22013-04-10 09:32:57 +0000688#endif
Eric Nelson32565c52012-01-31 07:52:04 +0000689
Benoît Thébaudeaufa7e3952013-04-23 10:17:38 +0000690struct ocotp_regs {
Jason Liudec11122011-11-25 00:18:02 +0000691 u32 ctrl;
692 u32 ctrl_set;
693 u32 ctrl_clr;
694 u32 ctrl_tog;
695 u32 timing;
696 u32 rsvd0[3];
697 u32 data;
698 u32 rsvd1[3];
699 u32 read_ctrl;
700 u32 rsvd2[3];
Benoît Thébaudeaufa7e3952013-04-23 10:17:38 +0000701 u32 read_fuse_data;
Jason Liudec11122011-11-25 00:18:02 +0000702 u32 rsvd3[3];
Benoît Thébaudeaufa7e3952013-04-23 10:17:38 +0000703 u32 sw_sticky;
Jason Liudec11122011-11-25 00:18:02 +0000704 u32 rsvd4[3];
705 u32 scs;
706 u32 scs_set;
707 u32 scs_clr;
708 u32 scs_tog;
709 u32 crc_addr;
710 u32 rsvd5[3];
711 u32 crc_value;
712 u32 rsvd6[3];
713 u32 version;
Jason Liubf651aa2011-12-19 02:38:13 +0000714 u32 rsvd7[0xdb];
Jason Liudec11122011-11-25 00:18:02 +0000715
Peng Fan52bae462015-08-26 15:40:47 +0800716 /* fuse banks */
Jason Liudec11122011-11-25 00:18:02 +0000717 struct fuse_bank {
718 u32 fuse_regs[0x20];
Peng Fan52bae462015-08-26 15:40:47 +0800719 } bank[0];
Jason Liudec11122011-11-25 00:18:02 +0000720};
721
Benoît Thébaudeaub29e3962013-04-23 10:17:39 +0000722struct fuse_bank0_regs {
723 u32 lock;
724 u32 rsvd0[3];
725 u32 uid_low;
726 u32 rsvd1[3];
727 u32 uid_high;
Stefano Babic83fd8582013-06-28 00:20:21 +0200728 u32 rsvd2[3];
Peng Fanc3490dbc2015-01-09 16:59:40 +0800729 u32 cfg2;
730 u32 rsvd3[3];
731 u32 cfg3;
732 u32 rsvd4[3];
733 u32 cfg4;
734 u32 rsvd5[3];
Stefano Babic83fd8582013-06-28 00:20:21 +0200735 u32 cfg5;
736 u32 rsvd6[3];
Peng Fanc3490dbc2015-01-09 16:59:40 +0800737 u32 cfg6;
738 u32 rsvd7[3];
Benoît Thébaudeaub29e3962013-04-23 10:17:39 +0000739};
740
Tim Harvey3eece962015-05-18 06:56:44 -0700741struct fuse_bank1_regs {
742 u32 mem0;
743 u32 rsvd0[3];
744 u32 mem1;
745 u32 rsvd1[3];
746 u32 mem2;
747 u32 rsvd2[3];
748 u32 mem3;
749 u32 rsvd3[3];
750 u32 mem4;
751 u32 rsvd4[3];
752 u32 ana0;
753 u32 rsvd5[3];
754 u32 ana1;
755 u32 rsvd6[3];
756 u32 ana2;
757 u32 rsvd7[3];
758};
759
Fabio Estevam712ab882014-06-24 17:40:58 -0300760struct fuse_bank4_regs {
761 u32 sjc_resp_low;
762 u32 rsvd0[3];
763 u32 sjc_resp_high;
764 u32 rsvd1[3];
Ye Lid5d8bf72016-02-01 10:41:31 +0800765 u32 mac_addr0;
Fabio Estevam712ab882014-06-24 17:40:58 -0300766 u32 rsvd2[3];
Ye Lid5d8bf72016-02-01 10:41:31 +0800767 u32 mac_addr1;
Fabio Estevam712ab882014-06-24 17:40:58 -0300768 u32 rsvd3[3];
Ye Lid5d8bf72016-02-01 10:41:31 +0800769 u32 mac_addr2; /*For i.MX6SX and i.MX6UL*/
Fabio Estevam712ab882014-06-24 17:40:58 -0300770 u32 rsvd4[7];
771 u32 gp1;
Peng Fan59e680d2015-07-20 19:28:23 +0800772 u32 rsvd5[3];
773 u32 gp2;
774 u32 rsvd6[3];
Fabio Estevam712ab882014-06-24 17:40:58 -0300775};
Jason Liudec11122011-11-25 00:18:02 +0000776
Jason Liubb25e072012-01-10 00:52:59 +0000777struct aipstz_regs {
778 u32 mprot0;
779 u32 mprot1;
780 u32 rsvd[0xe];
781 u32 opacr0;
782 u32 opacr1;
783 u32 opacr2;
784 u32 opacr3;
785 u32 opacr4;
786};
787
Fabio Estevam46e97332012-03-20 04:21:45 +0000788struct anatop_regs {
789 u32 pll_sys; /* 0x000 */
790 u32 pll_sys_set; /* 0x004 */
791 u32 pll_sys_clr; /* 0x008 */
792 u32 pll_sys_tog; /* 0x00c */
793 u32 usb1_pll_480_ctrl; /* 0x010 */
794 u32 usb1_pll_480_ctrl_set; /* 0x014 */
795 u32 usb1_pll_480_ctrl_clr; /* 0x018 */
796 u32 usb1_pll_480_ctrl_tog; /* 0x01c */
797 u32 usb2_pll_480_ctrl; /* 0x020 */
798 u32 usb2_pll_480_ctrl_set; /* 0x024 */
799 u32 usb2_pll_480_ctrl_clr; /* 0x028 */
800 u32 usb2_pll_480_ctrl_tog; /* 0x02c */
801 u32 pll_528; /* 0x030 */
802 u32 pll_528_set; /* 0x034 */
803 u32 pll_528_clr; /* 0x038 */
804 u32 pll_528_tog; /* 0x03c */
805 u32 pll_528_ss; /* 0x040 */
806 u32 rsvd0[3];
807 u32 pll_528_num; /* 0x050 */
808 u32 rsvd1[3];
809 u32 pll_528_denom; /* 0x060 */
810 u32 rsvd2[3];
811 u32 pll_audio; /* 0x070 */
812 u32 pll_audio_set; /* 0x074 */
813 u32 pll_audio_clr; /* 0x078 */
814 u32 pll_audio_tog; /* 0x07c */
815 u32 pll_audio_num; /* 0x080 */
816 u32 rsvd3[3];
817 u32 pll_audio_denom; /* 0x090 */
818 u32 rsvd4[3];
819 u32 pll_video; /* 0x0a0 */
820 u32 pll_video_set; /* 0x0a4 */
821 u32 pll_video_clr; /* 0x0a8 */
822 u32 pll_video_tog; /* 0x0ac */
823 u32 pll_video_num; /* 0x0b0 */
824 u32 rsvd5[3];
825 u32 pll_video_denom; /* 0x0c0 */
826 u32 rsvd6[3];
827 u32 pll_mlb; /* 0x0d0 */
828 u32 pll_mlb_set; /* 0x0d4 */
829 u32 pll_mlb_clr; /* 0x0d8 */
830 u32 pll_mlb_tog; /* 0x0dc */
831 u32 pll_enet; /* 0x0e0 */
832 u32 pll_enet_set; /* 0x0e4 */
833 u32 pll_enet_clr; /* 0x0e8 */
834 u32 pll_enet_tog; /* 0x0ec */
835 u32 pfd_480; /* 0x0f0 */
836 u32 pfd_480_set; /* 0x0f4 */
837 u32 pfd_480_clr; /* 0x0f8 */
838 u32 pfd_480_tog; /* 0x0fc */
839 u32 pfd_528; /* 0x100 */
840 u32 pfd_528_set; /* 0x104 */
841 u32 pfd_528_clr; /* 0x108 */
842 u32 pfd_528_tog; /* 0x10c */
843 u32 reg_1p1; /* 0x110 */
844 u32 reg_1p1_set; /* 0x114 */
845 u32 reg_1p1_clr; /* 0x118 */
846 u32 reg_1p1_tog; /* 0x11c */
847 u32 reg_3p0; /* 0x120 */
848 u32 reg_3p0_set; /* 0x124 */
849 u32 reg_3p0_clr; /* 0x128 */
850 u32 reg_3p0_tog; /* 0x12c */
851 u32 reg_2p5; /* 0x130 */
852 u32 reg_2p5_set; /* 0x134 */
853 u32 reg_2p5_clr; /* 0x138 */
854 u32 reg_2p5_tog; /* 0x13c */
855 u32 reg_core; /* 0x140 */
856 u32 reg_core_set; /* 0x144 */
857 u32 reg_core_clr; /* 0x148 */
858 u32 reg_core_tog; /* 0x14c */
859 u32 ana_misc0; /* 0x150 */
860 u32 ana_misc0_set; /* 0x154 */
861 u32 ana_misc0_clr; /* 0x158 */
862 u32 ana_misc0_tog; /* 0x15c */
863 u32 ana_misc1; /* 0x160 */
864 u32 ana_misc1_set; /* 0x164 */
865 u32 ana_misc1_clr; /* 0x168 */
866 u32 ana_misc1_tog; /* 0x16c */
867 u32 ana_misc2; /* 0x170 */
868 u32 ana_misc2_set; /* 0x174 */
869 u32 ana_misc2_clr; /* 0x178 */
870 u32 ana_misc2_tog; /* 0x17c */
871 u32 tempsense0; /* 0x180 */
872 u32 tempsense0_set; /* 0x184 */
873 u32 tempsense0_clr; /* 0x188 */
874 u32 tempsense0_tog; /* 0x18c */
875 u32 tempsense1; /* 0x190 */
876 u32 tempsense1_set; /* 0x194 */
877 u32 tempsense1_clr; /* 0x198 */
878 u32 tempsense1_tog; /* 0x19c */
879 u32 usb1_vbus_detect; /* 0x1a0 */
880 u32 usb1_vbus_detect_set; /* 0x1a4 */
881 u32 usb1_vbus_detect_clr; /* 0x1a8 */
882 u32 usb1_vbus_detect_tog; /* 0x1ac */
883 u32 usb1_chrg_detect; /* 0x1b0 */
884 u32 usb1_chrg_detect_set; /* 0x1b4 */
885 u32 usb1_chrg_detect_clr; /* 0x1b8 */
886 u32 usb1_chrg_detect_tog; /* 0x1bc */
887 u32 usb1_vbus_det_stat; /* 0x1c0 */
888 u32 usb1_vbus_det_stat_set; /* 0x1c4 */
889 u32 usb1_vbus_det_stat_clr; /* 0x1c8 */
890 u32 usb1_vbus_det_stat_tog; /* 0x1cc */
891 u32 usb1_chrg_det_stat; /* 0x1d0 */
892 u32 usb1_chrg_det_stat_set; /* 0x1d4 */
893 u32 usb1_chrg_det_stat_clr; /* 0x1d8 */
894 u32 usb1_chrg_det_stat_tog; /* 0x1dc */
895 u32 usb1_loopback; /* 0x1e0 */
896 u32 usb1_loopback_set; /* 0x1e4 */
897 u32 usb1_loopback_clr; /* 0x1e8 */
898 u32 usb1_loopback_tog; /* 0x1ec */
899 u32 usb1_misc; /* 0x1f0 */
900 u32 usb1_misc_set; /* 0x1f4 */
901 u32 usb1_misc_clr; /* 0x1f8 */
902 u32 usb1_misc_tog; /* 0x1fc */
903 u32 usb2_vbus_detect; /* 0x200 */
904 u32 usb2_vbus_detect_set; /* 0x204 */
905 u32 usb2_vbus_detect_clr; /* 0x208 */
906 u32 usb2_vbus_detect_tog; /* 0x20c */
907 u32 usb2_chrg_detect; /* 0x210 */
908 u32 usb2_chrg_detect_set; /* 0x214 */
909 u32 usb2_chrg_detect_clr; /* 0x218 */
910 u32 usb2_chrg_detect_tog; /* 0x21c */
911 u32 usb2_vbus_det_stat; /* 0x220 */
912 u32 usb2_vbus_det_stat_set; /* 0x224 */
913 u32 usb2_vbus_det_stat_clr; /* 0x228 */
914 u32 usb2_vbus_det_stat_tog; /* 0x22c */
915 u32 usb2_chrg_det_stat; /* 0x230 */
916 u32 usb2_chrg_det_stat_set; /* 0x234 */
917 u32 usb2_chrg_det_stat_clr; /* 0x238 */
918 u32 usb2_chrg_det_stat_tog; /* 0x23c */
919 u32 usb2_loopback; /* 0x240 */
920 u32 usb2_loopback_set; /* 0x244 */
921 u32 usb2_loopback_clr; /* 0x248 */
922 u32 usb2_loopback_tog; /* 0x24c */
923 u32 usb2_misc; /* 0x250 */
924 u32 usb2_misc_set; /* 0x254 */
925 u32 usb2_misc_clr; /* 0x258 */
926 u32 usb2_misc_tog; /* 0x25c */
927 u32 digprog; /* 0x260 */
Troy Kisky58394932012-10-23 10:57:46 +0000928 u32 reserved1[7];
929 u32 digprog_sololite; /* 0x280 */
Fabio Estevam46e97332012-03-20 04:21:45 +0000930};
931
Eric Nelson939dd082013-08-29 12:37:35 -0700932#define ANATOP_PFD_FRAC_SHIFT(n) ((n)*8)
933#define ANATOP_PFD_FRAC_MASK(n) (0x3f<<ANATOP_PFD_FRAC_SHIFT(n))
934#define ANATOP_PFD_STABLE_SHIFT(n) (6+((n)*8))
935#define ANATOP_PFD_STABLE_MASK(n) (1<<ANATOP_PFD_STABLE_SHIFT(n))
936#define ANATOP_PFD_CLKGATE_SHIFT(n) (7+((n)*8))
937#define ANATOP_PFD_CLKGATE_MASK(n) (1<<ANATOP_PFD_CLKGATE_SHIFT(n))
Eric Nelson8098ec12012-09-19 08:29:46 +0000938
Fabio Estevam48e65b02013-02-07 06:45:23 +0000939struct wdog_regs {
940 u16 wcr; /* Control */
941 u16 wsr; /* Service */
942 u16 wrsr; /* Reset Status */
943 u16 wicr; /* Interrupt Control */
944 u16 wmcr; /* Miscellaneous Control */
945};
946
Heiko Schocher72b20902014-07-18 06:07:18 +0200947#define PWMCR_PRESCALER(x) (((x - 1) & 0xFFF) << 4)
948#define PWMCR_DOZEEN (1 << 24)
949#define PWMCR_WAITEN (1 << 23)
950#define PWMCR_DBGEN (1 << 22)
951#define PWMCR_CLKSRC_IPG_HIGH (2 << 16)
952#define PWMCR_CLKSRC_IPG (1 << 16)
953#define PWMCR_EN (1 << 0)
954
955struct pwm_regs {
956 u32 cr;
957 u32 sr;
958 u32 ir;
959 u32 sar;
960 u32 pr;
961 u32 cnr;
962};
Stefan Agner11389e22018-05-30 19:01:45 +0200963
964/*
965 * If ROM fail back to USB recover mode, USBPH0_PWD will be clear to use USB
966 * If boot from the other mode, USB0_PWD will keep reset value
967 */
968#define is_boot_from_usb(void) (!(readl(USB_PHY0_BASE_ADDR) & (1<<20)))
969
Simon Glass559f1a82020-05-10 11:40:12 -0600970#endif /* __ASSEMBLY__ */
Jason Liudec11122011-11-25 00:18:02 +0000971#endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */