Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 1859b70691f6753c9c48285ceaed19fcce87e188 / . / arch / arm / include / asm / arch-mx6 / imx-regs.h
blob: 6a200bb8655ac636ba18e26ad169433a39a0f0fe [file] [log] [blame]
Jason Liudec11122011-11-25 00:18:02 +0000[diff] [blame]1/*
2 * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
17 */
18
19#ifndef __ASM_ARCH_MX6_IMX_REGS_H__
20#define __ASM_ARCH_MX6_IMX_REGS_H__
21
22#define ROMCP_ARB_BASE_ADDR 0x00000000
23#define ROMCP_ARB_END_ADDR 0x000FFFFF
24#define CAAM_ARB_BASE_ADDR 0x00100000
25#define CAAM_ARB_END_ADDR 0x00103FFF
26#define APBH_DMA_ARB_BASE_ADDR 0x00110000
27#define APBH_DMA_ARB_END_ADDR 0x00117FFF
28#define HDMI_ARB_BASE_ADDR 0x00120000
29#define HDMI_ARB_END_ADDR 0x00128FFF
30#define GPU_3D_ARB_BASE_ADDR 0x00130000
31#define GPU_3D_ARB_END_ADDR 0x00133FFF
32#define GPU_2D_ARB_BASE_ADDR 0x00134000
33#define GPU_2D_ARB_END_ADDR 0x00137FFF
34#define DTCP_ARB_BASE_ADDR 0x00138000
35#define DTCP_ARB_END_ADDR 0x0013BFFF
36
37/* GPV - PL301 configuration ports */
38#define GPV2_BASE_ADDR 0x00200000
39#define GPV3_BASE_ADDR 0x00300000
40#define GPV4_BASE_ADDR 0x00800000
41#define IRAM_BASE_ADDR 0x00900000
42#define SCU_BASE_ADDR 0x00A00000
43#define IC_INTERFACES_BASE_ADDR 0x00A00100
44#define GLOBAL_TIMER_BASE_ADDR 0x00A00200
45#define PRIVATE_TIMERS_WD_BASE_ADDR 0x00A00600
46#define IC_DISTRIBUTOR_BASE_ADDR 0x00A01000
47#define GPV0_BASE_ADDR 0x00B00000
48#define GPV1_BASE_ADDR 0x00C00000
49#define PCIE_ARB_BASE_ADDR 0x01000000
50#define PCIE_ARB_END_ADDR 0x01FFFFFF
51
52#define AIPS1_ARB_BASE_ADDR 0x02000000
53#define AIPS1_ARB_END_ADDR 0x020FFFFF
54#define AIPS2_ARB_BASE_ADDR 0x02100000
55#define AIPS2_ARB_END_ADDR 0x021FFFFF
56#define SATA_ARB_BASE_ADDR 0x02200000
57#define SATA_ARB_END_ADDR 0x02203FFF
58#define OPENVG_ARB_BASE_ADDR 0x02204000
59#define OPENVG_ARB_END_ADDR 0x02207FFF
60#define HSI_ARB_BASE_ADDR 0x02208000
61#define HSI_ARB_END_ADDR 0x0220BFFF
62#define IPU1_ARB_BASE_ADDR 0x02400000
63#define IPU1_ARB_END_ADDR 0x027FFFFF
64#define IPU2_ARB_BASE_ADDR 0x02800000
65#define IPU2_ARB_END_ADDR 0x02BFFFFF
66#define WEIM_ARB_BASE_ADDR 0x08000000
67#define WEIM_ARB_END_ADDR 0x0FFFFFFF
68
69#define MMDC0_ARB_BASE_ADDR 0x10000000
70#define MMDC0_ARB_END_ADDR 0x7FFFFFFF
71#define MMDC1_ARB_BASE_ADDR 0x80000000
72#define MMDC1_ARB_END_ADDR 0xFFFFFFFF
73
74/* Defines for Blocks connected via AIPS (SkyBlue) */
75#define ATZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR
76#define ATZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR
77#define AIPS1_BASE_ADDR AIPS1_ON_BASE_ADDR
78#define AIPS2_BASE_ADDR AIPS2_ON_BASE_ADDR
79
80#define SPDIF_BASE_ADDR (ATZ1_BASE_ADDR + 0x04000)
81#define ECSPI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x08000)
82#define ECSPI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x0C000)
83#define ECSPI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x10000)
84#define ECSPI4_BASE_ADDR (ATZ1_BASE_ADDR + 0x14000)
85#define ECSPI5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
86#define UART1_BASE (ATZ1_BASE_ADDR + 0x20000)
87#define ESAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
88#define SSI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000)
89#define SSI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000)
90#define SSI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000)
91#define ASRC_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000)
92#define SPBA_BASE_ADDR (ATZ1_BASE_ADDR + 0x3C000)
93#define VPU_BASE_ADDR (ATZ1_BASE_ADDR + 0x40000)
94#define AIPS1_ON_BASE_ADDR (ATZ1_BASE_ADDR + 0x7C000)
95
96#define AIPS1_OFF_BASE_ADDR (ATZ1_BASE_ADDR + 0x80000)
97#define PWM1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x0000)
98#define PWM2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4000)
99#define PWM3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x8000)
100#define PWM4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0xC000)
101#define CAN1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x10000)
102#define CAN2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x14000)
103#define GPT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x18000)
104#define GPIO1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x1C000)
105#define GPIO2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x20000)
106#define GPIO3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x24000)
107#define GPIO4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x28000)
108#define GPIO5_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x2C000)
109#define GPIO6_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000)
110#define GPIO7_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000)
111#define KPP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x38000)
112#define WDOG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x3C000)
113#define WDOG2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x40000)
Wolfgang Grandegger1859b702012-02-08 22:33:25 +0000[diff] [blame^]114#define ANATOP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x48000)
115#define USB_PHY0_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x49000)
116#define USB_PHY1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4a000)
Jason Liudec11122011-11-25 00:18:02 +0000[diff] [blame]117#define CCM_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x44000)
118#define ANATOP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x48000)
119#define SNVS_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4C000)
120#define EPIT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x50000)
121#define EPIT2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x54000)
122#define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x58000)
123#define GPC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x5C000)
124#define IOMUXC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x60000)
125#define DCIC1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000)
126#define DCIC2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
127#define DMA_REQ_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
128
129#define AIPS2_ON_BASE_ADDR (ATZ2_BASE_ADDR + 0x7C000)
130#define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000)
131#define CAAM_BASE_ADDR (ATZ2_BASE_ADDR)
132#define ARM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000)
133#define USBOH3_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000)
134#define USBOH3_USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000)
135#define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000)
136#define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
137#define USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x10000)
138#define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000)
139#define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000)
140#define USDHC4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000)
141#define I2C1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x20000)
142#define I2C2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x24000)
143#define I2C3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x28000)
144#define ROMCP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x2C000)
145#define MMDC_P0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x30000)
146#define MMDC_P1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
147#define WEIM_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x38000)
148#define OCOTP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x3C000)
149#define CSU_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x40000)
150#define IP2APB_PERFMON1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000)
151#define IP2APB_PERFMON2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000)
152#define IP2APB_PERFMON3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000)
153#define IP2APB_TZASC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x50000)
154#define IP2APB_TZASC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000)
155#define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000)
156#define MIPI_CSI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000)
157#define MIPI_DSI_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
158#define VDOA_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
159#define UART2_BASE (AIPS2_OFF_BASE_ADDR + 0x68000)
160#define UART3_BASE (AIPS2_OFF_BASE_ADDR + 0x6C000)
161#define UART4_BASE (AIPS2_OFF_BASE_ADDR + 0x70000)
162#define UART5_BASE (AIPS2_OFF_BASE_ADDR + 0x74000)
163#define IP2APB_USBPHY1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000)
164#define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000)
165
166#define CHIP_REV_1_0 0x10
167#define IRAM_SIZE 0x00040000
168#define IMX_IIM_BASE OCOTP_BASE_ADDR
Troy Kisky01112132012-02-07 14:08:46 +0000[diff] [blame]169#define FEC_QUIRK_ENET_MAC
Jason Liudec11122011-11-25 00:18:02 +0000[diff] [blame]170
Eric Nelson066263d2012-01-31 07:52:01 +0000[diff] [blame]171#define GPIO_NUMBER(port, index) ((((port)-1)*32)+((index)&31))
172#define GPIO_TO_PORT(number) (((number)/32)+1)
173#define GPIO_TO_INDEX(number) ((number)&31)
174
Jason Liudec11122011-11-25 00:18:02 +0000[diff] [blame]175#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
176#include <asm/types.h>
177
Fabio Estevam04fc1282011-12-20 05:46:31 +0000[diff] [blame]178extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
Jason Liudec11122011-11-25 00:18:02 +0000[diff] [blame]179
180/* System Reset Controller (SRC) */
181struct src {
182 u32 scr;
183 u32 sbmr1;
184 u32 srsr;
185 u32 reserved1[2];
186 u32 sisr;
187 u32 simr;
188 u32 sbmr2;
189 u32 gpr1;
190 u32 gpr2;
191 u32 gpr3;
192 u32 gpr4;
193 u32 gpr5;
194 u32 gpr6;
195 u32 gpr7;
196 u32 gpr8;
197 u32 gpr9;
198 u32 gpr10;
199};
200
Eric Nelson32565c52012-01-31 07:52:04 +0000[diff] [blame]201/* ECSPI registers */
202struct cspi_regs {
203 u32 rxdata;
204 u32 txdata;
205 u32 ctrl;
206 u32 cfg;
207 u32 intr;
208 u32 dma;
209 u32 stat;
210 u32 period;
211};
212
213/*
214 * CSPI register definitions
215 */
216#define MXC_ECSPI
217#define MXC_CSPICTRL_EN (1 << 0)
218#define MXC_CSPICTRL_MODE (1 << 1)
219#define MXC_CSPICTRL_XCH (1 << 2)
220#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
221#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
222#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
223#define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8)
224#define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18)
225#define MXC_CSPICTRL_MAXBITS 0xfff
226#define MXC_CSPICTRL_TC (1 << 7)
227#define MXC_CSPICTRL_RXOVF (1 << 6)
228#define MXC_CSPIPERIOD_32KHZ (1 << 15)
229#define MAX_SPI_BYTES 32
230
231/* Bit position inside CTRL register to be associated with SS */
232#define MXC_CSPICTRL_CHAN 18
233
234/* Bit position inside CON register to be associated with SS */
235#define MXC_CSPICON_POL 4
236#define MXC_CSPICON_PHA 0
237#define MXC_CSPICON_SSPOL 12
238#define MXC_SPI_BASE_ADDRESSES \
239 ECSPI1_BASE_ADDR, \
240 ECSPI2_BASE_ADDR, \
241 ECSPI3_BASE_ADDR, \
242 ECSPI4_BASE_ADDR, \
243 ECSPI5_BASE_ADDR
244
Jason Liudec11122011-11-25 00:18:02 +0000[diff] [blame]245struct iim_regs {
246 u32 ctrl;
247 u32 ctrl_set;
248 u32 ctrl_clr;
249 u32 ctrl_tog;
250 u32 timing;
251 u32 rsvd0[3];
252 u32 data;
253 u32 rsvd1[3];
254 u32 read_ctrl;
255 u32 rsvd2[3];
256 u32 fuse_data;
257 u32 rsvd3[3];
258 u32 sticky;
259 u32 rsvd4[3];
260 u32 scs;
261 u32 scs_set;
262 u32 scs_clr;
263 u32 scs_tog;
264 u32 crc_addr;
265 u32 rsvd5[3];
266 u32 crc_value;
267 u32 rsvd6[3];
268 u32 version;
Jason Liubf651aa2011-12-19 02:38:13 +0000[diff] [blame]269 u32 rsvd7[0xdb];
Jason Liudec11122011-11-25 00:18:02 +0000[diff] [blame]270
271 struct fuse_bank {
272 u32 fuse_regs[0x20];
273 } bank[15];
274};
275
276struct fuse_bank4_regs {
277 u32 sjc_resp_low;
278 u32 rsvd0[3];
279 u32 sjc_resp_high;
280 u32 rsvd1[3];
281 u32 mac_addr_low;
282 u32 rsvd2[3];
283 u32 mac_addr_high;
284 u32 rsvd3[0x13];
285};
286
Jason Liubb25e072012-01-10 00:52:59 +0000[diff] [blame]287struct aipstz_regs {
288 u32 mprot0;
289 u32 mprot1;
290 u32 rsvd[0xe];
291 u32 opacr0;
292 u32 opacr1;
293 u32 opacr2;
294 u32 opacr3;
295 u32 opacr4;
296};
297
Jason Liudec11122011-11-25 00:18:02 +0000[diff] [blame]298#endif /* __ASSEMBLER__*/
299#endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */