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git01.mediatek.com / filogic / uboot / 1a55f04dbf38935c27f5bf217ca8ffd5439f40e2 / . / arch / arm / mach-tegra / tegra210 / clock.c
blob: 330753f2ad1a30b70f177adb5ad97ef50241738d [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]2/*
Tom Warren3bb2f5d2020-03-27 10:24:31 -0700[diff] [blame]3 * (C) Copyright 2013-2020
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]4 * NVIDIA Corporation <www.nvidia.com>
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]5 */
6
7/* Tegra210 Clock control functions */
8
9#include <common.h>
Stephen Warren553b61e2015-10-05 16:58:52 -0600[diff] [blame]10#include <errno.h>
Simon Glass97589732020-05-10 11:40:02 -0600[diff] [blame]11#include <init.h>
Simon Glass0f2af882020-05-10 11:40:05 -0600[diff] [blame]12#include <log.h>
Simon Glass274e0b02020-05-10 11:39:56 -0600[diff] [blame]13#include <asm/cache.h>
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]14#include <asm/io.h>
15#include <asm/arch/clock.h>
16#include <asm/arch/sysctr.h>
17#include <asm/arch/tegra.h>
18#include <asm/arch-tegra/clk_rst.h>
19#include <asm/arch-tegra/timer.h>
20#include <div64.h>
21#include <fdtdec.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -0600[diff] [blame]22#include <linux/bitops.h>
Simon Glassdbd79542020-05-10 11:40:11 -0600[diff] [blame]23#include <linux/delay.h>
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]24
25/*
26 * Clock types that we can use as a source. The Tegra210 has muxes for the
27 * peripheral clocks, and in most cases there are four options for the clock
28 * source. This gives us a clock 'type' and exploits what commonality exists
29 * in the device.
30 *
31 * Letters are obvious, except for T which means CLK_M, and S which means the
32 * clock derived from 32KHz. Beware that CLK_M (also called OSC in the
33 * datasheet) and PLL_M are different things. The former is the basic
34 * clock supplied to the SOC from an external oscillator. The latter is the
35 * memory clock PLL.
36 *
37 * See definitions in clock_id in the header file.
38 */
39enum clock_type_id {
40 CLOCK_TYPE_AXPT, /* PLL_A, PLL_X, PLL_P, CLK_M */
41 CLOCK_TYPE_MCPA, /* and so on */
42 CLOCK_TYPE_MCPT,
43 CLOCK_TYPE_PCM,
44 CLOCK_TYPE_PCMT,
45 CLOCK_TYPE_PDCT,
46 CLOCK_TYPE_ACPT,
47 CLOCK_TYPE_ASPTE,
Thierry Reding317a47c2019-04-15 11:32:15 +0200[diff] [blame]48 CLOCK_TYPE_PDD2T,
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]49 CLOCK_TYPE_PCST,
Simon Glassb6ba3fb2015-08-10 07:14:36 -0600[diff] [blame]50 CLOCK_TYPE_DP,
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]51
52 CLOCK_TYPE_PC2CC3M,
53 CLOCK_TYPE_PC2CC3S_T,
54 CLOCK_TYPE_PC2CC3M_T,
55 CLOCK_TYPE_PC2CC3M_T16, /* PC2CC3M_T, but w/16-bit divisor (I2C) */
56 CLOCK_TYPE_MC2CC3P_A,
57 CLOCK_TYPE_M,
58 CLOCK_TYPE_MCPTM2C2C3,
59 CLOCK_TYPE_PC2CC3T_S,
60 CLOCK_TYPE_AC2CC3P_TS2,
61 CLOCK_TYPE_PC01C00_C42C41TC40,
62
63 CLOCK_TYPE_COUNT,
64 CLOCK_TYPE_NONE = -1, /* invalid clock type */
65};
66
67enum {
68 CLOCK_MAX_MUX = 8 /* number of source options for each clock */
69};
70
71/*
72 * Clock source mux for each clock type. This just converts our enum into
73 * a list of mux sources for use by the code.
74 *
75 * Note:
76 * The extra column in each clock source array is used to store the mask
77 * bits in its register for the source.
78 */
79#define CLK(x) CLOCK_ID_ ## x
80static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = {
81 { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC),
82 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
83 MASK_BITS_31_30},
84 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO),
85 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
86 MASK_BITS_31_30},
87 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
88 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
89 MASK_BITS_31_30},
90 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE),
91 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
92 MASK_BITS_31_30},
93 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
94 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
95 MASK_BITS_31_30},
96 { CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC),
97 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
98 MASK_BITS_31_30},
99 { CLK(AUDIO), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
100 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
101 MASK_BITS_31_30},
102 { CLK(AUDIO), CLK(SFROM32KHZ), CLK(PERIPH), CLK(OSC),
103 CLK(EPCI), CLK(NONE), CLK(NONE), CLK(NONE),
104 MASK_BITS_31_29},
Thierry Reding317a47c2019-04-15 11:32:15 +0200[diff] [blame]105 { CLK(PERIPH), CLK(NONE), CLK(DISPLAY), CLK(NONE),
106 CLK(NONE), CLK(DISPLAY2), CLK(OSC), CLK(NONE),
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]107 MASK_BITS_31_29},
108 { CLK(PERIPH), CLK(CGENERAL), CLK(SFROM32KHZ), CLK(OSC),
109 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
110 MASK_BITS_31_28},
Simon Glassb6ba3fb2015-08-10 07:14:36 -0600[diff] [blame]111 /* CLOCK_TYPE_DP */
112 { CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
113 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
114 MASK_BITS_31_28},
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]115
116 /* Additional clock types on Tegra114+ */
117 /* CLOCK_TYPE_PC2CC3M */
118 { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
119 CLK(MEMORY), CLK(NONE), CLK(NONE), CLK(NONE),
120 MASK_BITS_31_29},
121 /* CLOCK_TYPE_PC2CC3S_T */
122 { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
123 CLK(SFROM32KHZ), CLK(NONE), CLK(OSC), CLK(NONE),
124 MASK_BITS_31_29},
125 /* CLOCK_TYPE_PC2CC3M_T */
126 { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
127 CLK(MEMORY), CLK(NONE), CLK(OSC), CLK(NONE),
128 MASK_BITS_31_29},
129 /* CLOCK_TYPE_PC2CC3M_T, w/16-bit divisor (I2C) */
130 { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
131 CLK(MEMORY), CLK(NONE), CLK(OSC), CLK(NONE),
132 MASK_BITS_31_29},
133 /* CLOCK_TYPE_MC2CC3P_A */
134 { CLK(MEMORY), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
135 CLK(PERIPH), CLK(NONE), CLK(AUDIO), CLK(NONE),
136 MASK_BITS_31_29},
137 /* CLOCK_TYPE_M */
138 { CLK(MEMORY), CLK(NONE), CLK(NONE), CLK(NONE),
139 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
140 MASK_BITS_31_30},
141 /* CLOCK_TYPE_MCPTM2C2C3 */
142 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
143 CLK(MEMORY2), CLK(CGENERAL2), CLK(CGENERAL3), CLK(NONE),
144 MASK_BITS_31_29},
145 /* CLOCK_TYPE_PC2CC3T_S */
146 { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
147 CLK(OSC), CLK(NONE), CLK(SFROM32KHZ), CLK(NONE),
148 MASK_BITS_31_29},
149 /* CLOCK_TYPE_AC2CC3P_TS2 */
150 { CLK(AUDIO), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
151 CLK(PERIPH), CLK(NONE), CLK(OSC), CLK(SRC2),
152 MASK_BITS_31_29},
153 /* CLOCK_TYPE_PC01C00_C42C41TC40 */
154 { CLK(PERIPH), CLK(CGENERAL_1), CLK(CGENERAL_0), CLK(NONE),
155 CLK(CGENERAL4_2), CLK(CGENERAL4_1), CLK(OSC), CLK(CGENERAL4_0),
156 MASK_BITS_31_29},
157};
158
159/*
160 * Clock type for each peripheral clock source. We put the name in each
161 * record just so it is easy to match things up
162 */
163#define TYPE(name, type) type
164static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
165 /* 0x00 */
166 TYPE(PERIPHC_I2S2, CLOCK_TYPE_AXPT),
167 TYPE(PERIPHC_I2S3, CLOCK_TYPE_AXPT),
168 TYPE(PERIPHC_SPDIF_OUT, CLOCK_TYPE_AXPT),
169 TYPE(PERIPHC_SPDIF_IN, CLOCK_TYPE_PC2CC3M),
170 TYPE(PERIPHC_PWM, CLOCK_TYPE_PC2CC3S_T),
171 TYPE(PERIPHC_05h, CLOCK_TYPE_NONE),
172 TYPE(PERIPHC_SBC2, CLOCK_TYPE_PC2CC3M_T),
173 TYPE(PERIPHC_SBC3, CLOCK_TYPE_PC2CC3M_T),
174
175 /* 0x08 */
176 TYPE(PERIPHC_08h, CLOCK_TYPE_NONE),
177 TYPE(PERIPHC_I2C1, CLOCK_TYPE_PC2CC3M_T16),
178 TYPE(PERIPHC_I2C5, CLOCK_TYPE_PC2CC3M_T16),
179 TYPE(PERIPHC_0bh, CLOCK_TYPE_NONE),
180 TYPE(PERIPHC_0ch, CLOCK_TYPE_NONE),
181 TYPE(PERIPHC_SBC1, CLOCK_TYPE_PC2CC3M_T),
Thierry Reding317a47c2019-04-15 11:32:15 +0200[diff] [blame]182 TYPE(PERIPHC_DISP1, CLOCK_TYPE_PDD2T),
183 TYPE(PERIPHC_DISP2, CLOCK_TYPE_PDD2T),
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]184
185 /* 0x10 */
186 TYPE(PERIPHC_10h, CLOCK_TYPE_NONE),
187 TYPE(PERIPHC_11h, CLOCK_TYPE_NONE),
188 TYPE(PERIPHC_VI, CLOCK_TYPE_MC2CC3P_A),
189 TYPE(PERIPHC_13h, CLOCK_TYPE_NONE),
190 TYPE(PERIPHC_SDMMC1, CLOCK_TYPE_PC2CC3M_T),
191 TYPE(PERIPHC_SDMMC2, CLOCK_TYPE_PC2CC3M_T),
192 TYPE(PERIPHC_16h, CLOCK_TYPE_NONE),
193 TYPE(PERIPHC_17h, CLOCK_TYPE_NONE),
194
195 /* 0x18 */
196 TYPE(PERIPHC_18h, CLOCK_TYPE_NONE),
197 TYPE(PERIPHC_SDMMC4, CLOCK_TYPE_PC2CC3M_T),
198 TYPE(PERIPHC_VFIR, CLOCK_TYPE_PC2CC3M_T),
199 TYPE(PERIPHC_1Bh, CLOCK_TYPE_NONE),
200 TYPE(PERIPHC_1Ch, CLOCK_TYPE_NONE),
201 TYPE(PERIPHC_HSI, CLOCK_TYPE_PC2CC3M_T),
202 TYPE(PERIPHC_UART1, CLOCK_TYPE_PC2CC3M_T),
203 TYPE(PERIPHC_UART2, CLOCK_TYPE_PC2CC3M_T),
204
205 /* 0x20 */
206 TYPE(PERIPHC_HOST1X, CLOCK_TYPE_MC2CC3P_A),
207 TYPE(PERIPHC_21h, CLOCK_TYPE_NONE),
208 TYPE(PERIPHC_22h, CLOCK_TYPE_NONE),
209 TYPE(PERIPHC_23h, CLOCK_TYPE_NONE),
210 TYPE(PERIPHC_24h, CLOCK_TYPE_NONE),
211 TYPE(PERIPHC_25h, CLOCK_TYPE_NONE),
212 TYPE(PERIPHC_I2C2, CLOCK_TYPE_PC2CC3M_T16),
213 TYPE(PERIPHC_EMC, CLOCK_TYPE_MCPTM2C2C3),
214
215 /* 0x28 */
216 TYPE(PERIPHC_UART3, CLOCK_TYPE_PC2CC3M_T),
217 TYPE(PERIPHC_29h, CLOCK_TYPE_NONE),
218 TYPE(PERIPHC_VI_SENSOR, CLOCK_TYPE_MC2CC3P_A),
219 TYPE(PERIPHC_2bh, CLOCK_TYPE_NONE),
220 TYPE(PERIPHC_2ch, CLOCK_TYPE_NONE),
221 TYPE(PERIPHC_SBC4, CLOCK_TYPE_PC2CC3M_T),
222 TYPE(PERIPHC_I2C3, CLOCK_TYPE_PC2CC3M_T16),
223 TYPE(PERIPHC_SDMMC3, CLOCK_TYPE_PC2CC3M_T),
224
225 /* 0x30 */
226 TYPE(PERIPHC_UART4, CLOCK_TYPE_PC2CC3M_T),
227 TYPE(PERIPHC_UART5, CLOCK_TYPE_PC2CC3M_T),
228 TYPE(PERIPHC_VDE, CLOCK_TYPE_PC2CC3M_T),
229 TYPE(PERIPHC_OWR, CLOCK_TYPE_PC2CC3M_T),
230 TYPE(PERIPHC_NOR, CLOCK_TYPE_PC2CC3M_T),
231 TYPE(PERIPHC_CSITE, CLOCK_TYPE_PC2CC3M_T),
232 TYPE(PERIPHC_I2S1, CLOCK_TYPE_AXPT),
233 TYPE(PERIPHC_DTV, CLOCK_TYPE_NONE),
234
235 /* 0x38 */
236 TYPE(PERIPHC_38h, CLOCK_TYPE_NONE),
237 TYPE(PERIPHC_39h, CLOCK_TYPE_NONE),
238 TYPE(PERIPHC_3ah, CLOCK_TYPE_NONE),
239 TYPE(PERIPHC_3bh, CLOCK_TYPE_NONE),
240 TYPE(PERIPHC_MSENC, CLOCK_TYPE_MC2CC3P_A),
241 TYPE(PERIPHC_TSEC, CLOCK_TYPE_PC2CC3M_T),
242 TYPE(PERIPHC_3eh, CLOCK_TYPE_NONE),
243 TYPE(PERIPHC_OSC, CLOCK_TYPE_NONE),
244
245 /* 0x40 */
246 TYPE(PERIPHC_40h, CLOCK_TYPE_NONE), /* start with 0x3b0 */
247 TYPE(PERIPHC_MSELECT, CLOCK_TYPE_PC2CC3M_T),
248 TYPE(PERIPHC_TSENSOR, CLOCK_TYPE_PC2CC3T_S),
249 TYPE(PERIPHC_I2S4, CLOCK_TYPE_AXPT),
250 TYPE(PERIPHC_I2S5, CLOCK_TYPE_AXPT),
251 TYPE(PERIPHC_I2C4, CLOCK_TYPE_PC2CC3M_T16),
252 TYPE(PERIPHC_SBC5, CLOCK_TYPE_PC2CC3M_T),
253 TYPE(PERIPHC_SBC6, CLOCK_TYPE_PC2CC3M_T),
254
255 /* 0x48 */
256 TYPE(PERIPHC_AUDIO, CLOCK_TYPE_AC2CC3P_TS2),
257 TYPE(PERIPHC_49h, CLOCK_TYPE_NONE),
258 TYPE(PERIPHC_4ah, CLOCK_TYPE_NONE),
259 TYPE(PERIPHC_4bh, CLOCK_TYPE_NONE),
260 TYPE(PERIPHC_4ch, CLOCK_TYPE_NONE),
261 TYPE(PERIPHC_HDA2CODEC2X, CLOCK_TYPE_PC2CC3M_T),
262 TYPE(PERIPHC_ACTMON, CLOCK_TYPE_PC2CC3S_T),
263 TYPE(PERIPHC_EXTPERIPH1, CLOCK_TYPE_ASPTE),
264
265 /* 0x50 */
266 TYPE(PERIPHC_EXTPERIPH2, CLOCK_TYPE_ASPTE),
267 TYPE(PERIPHC_EXTPERIPH3, CLOCK_TYPE_ASPTE),
268 TYPE(PERIPHC_52h, CLOCK_TYPE_NONE),
269 TYPE(PERIPHC_I2CSLOW, CLOCK_TYPE_PC2CC3S_T),
270 TYPE(PERIPHC_SYS, CLOCK_TYPE_NONE),
271 TYPE(PERIPHC_55h, CLOCK_TYPE_NONE),
272 TYPE(PERIPHC_56h, CLOCK_TYPE_NONE),
273 TYPE(PERIPHC_57h, CLOCK_TYPE_NONE),
274
275 /* 0x58 */
276 TYPE(PERIPHC_58h, CLOCK_TYPE_NONE),
277 TYPE(PERIPHC_59h, CLOCK_TYPE_NONE),
278 TYPE(PERIPHC_5ah, CLOCK_TYPE_NONE),
279 TYPE(PERIPHC_5bh, CLOCK_TYPE_NONE),
280 TYPE(PERIPHC_SATAOOB, CLOCK_TYPE_PCMT),
281 TYPE(PERIPHC_SATA, CLOCK_TYPE_PCMT),
282 TYPE(PERIPHC_HDA, CLOCK_TYPE_PC2CC3M_T),
283 TYPE(PERIPHC_5fh, CLOCK_TYPE_NONE),
284
285 /* 0x60 */
286 TYPE(PERIPHC_XUSB_CORE_HOST, CLOCK_TYPE_NONE),
287 TYPE(PERIPHC_XUSB_FALCON, CLOCK_TYPE_NONE),
288 TYPE(PERIPHC_XUSB_FS, CLOCK_TYPE_NONE),
289 TYPE(PERIPHC_XUSB_CORE_DEV, CLOCK_TYPE_NONE),
290 TYPE(PERIPHC_XUSB_SS, CLOCK_TYPE_NONE),
291 TYPE(PERIPHC_CILAB, CLOCK_TYPE_NONE),
292 TYPE(PERIPHC_CILCD, CLOCK_TYPE_NONE),
293 TYPE(PERIPHC_CILE, CLOCK_TYPE_NONE),
294
295 /* 0x68 */
296 TYPE(PERIPHC_DSIA_LP, CLOCK_TYPE_NONE),
297 TYPE(PERIPHC_DSIB_LP, CLOCK_TYPE_NONE),
298 TYPE(PERIPHC_ENTROPY, CLOCK_TYPE_NONE),
299 TYPE(PERIPHC_DVFS_REF, CLOCK_TYPE_NONE),
300 TYPE(PERIPHC_DVFS_SOC, CLOCK_TYPE_NONE),
301 TYPE(PERIPHC_TRACECLKIN, CLOCK_TYPE_NONE),
302 TYPE(PERIPHC_6eh, CLOCK_TYPE_NONE),
303 TYPE(PERIPHC_6fh, CLOCK_TYPE_NONE),
304
305 /* 0x70 */
306 TYPE(PERIPHC_EMC_LATENCY, CLOCK_TYPE_NONE),
307 TYPE(PERIPHC_SOC_THERM, CLOCK_TYPE_NONE),
308 TYPE(PERIPHC_72h, CLOCK_TYPE_NONE),
309 TYPE(PERIPHC_73h, CLOCK_TYPE_NONE),
310 TYPE(PERIPHC_74h, CLOCK_TYPE_NONE),
311 TYPE(PERIPHC_75h, CLOCK_TYPE_NONE),
312 TYPE(PERIPHC_VI_SENSOR2, CLOCK_TYPE_NONE),
313 TYPE(PERIPHC_I2C6, CLOCK_TYPE_PC2CC3M_T16),
314
315 /* 0x78 */
316 TYPE(PERIPHC_78h, CLOCK_TYPE_NONE),
317 TYPE(PERIPHC_EMC_DLL, CLOCK_TYPE_MCPTM2C2C3),
318 TYPE(PERIPHC_7ah, CLOCK_TYPE_NONE),
319 TYPE(PERIPHC_CLK72MHZ, CLOCK_TYPE_NONE),
320 TYPE(PERIPHC_7ch, CLOCK_TYPE_NONE),
321 TYPE(PERIPHC_7dh, CLOCK_TYPE_NONE),
322 TYPE(PERIPHC_VIC, CLOCK_TYPE_NONE),
323 TYPE(PERIPHC_7Fh, CLOCK_TYPE_NONE),
324
325 /* 0x80 */
326 TYPE(PERIPHC_SDMMC_LEGACY_TM, CLOCK_TYPE_NONE),
327 TYPE(PERIPHC_NVDEC, CLOCK_TYPE_NONE),
328 TYPE(PERIPHC_NVJPG, CLOCK_TYPE_NONE),
329 TYPE(PERIPHC_NVENC, CLOCK_TYPE_NONE),
330 TYPE(PERIPHC_84h, CLOCK_TYPE_NONE),
331 TYPE(PERIPHC_85h, CLOCK_TYPE_NONE),
332 TYPE(PERIPHC_86h, CLOCK_TYPE_NONE),
333 TYPE(PERIPHC_87h, CLOCK_TYPE_NONE),
334
335 /* 0x88 */
336 TYPE(PERIPHC_88h, CLOCK_TYPE_NONE),
337 TYPE(PERIPHC_89h, CLOCK_TYPE_NONE),
338 TYPE(PERIPHC_DMIC3, CLOCK_TYPE_NONE),
339 TYPE(PERIPHC_APE, CLOCK_TYPE_NONE),
340 TYPE(PERIPHC_QSPI, CLOCK_TYPE_PC01C00_C42C41TC40),
Tom Warren3bb2f5d2020-03-27 10:24:31 -0700[diff] [blame]341 TYPE(PERIPHC_VI_I2C, CLOCK_TYPE_PC2CC3M_T16),
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]342 TYPE(PERIPHC_USB2_HSIC_TRK, CLOCK_TYPE_NONE),
343 TYPE(PERIPHC_PEX_SATA_USB_RX_BYP, CLOCK_TYPE_NONE),
344
345 /* 0x90 */
346 TYPE(PERIPHC_MAUD, CLOCK_TYPE_NONE),
347 TYPE(PERIPHC_TSECB, CLOCK_TYPE_NONE),
348};
349
350/*
351 * This array translates a periph_id to a periphc_internal_id
352 *
353 * Not present/matched up:
354 * uint vi_sensor; _VI_SENSOR_0, 0x1A8
355 * SPDIF - which is both 0x08 and 0x0c
356 *
357 */
358#define NONE(name) (-1)
359#define OFFSET(name, value) PERIPHC_ ## name
360#define INTERNAL_ID(id) (id & 0x000000ff)
361static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
362 /* Low word: 31:0 */
363 NONE(CPU),
364 NONE(COP),
365 NONE(TRIGSYS),
366 NONE(ISPB),
367 NONE(RESERVED4),
368 NONE(TMR),
369 PERIPHC_UART1,
370 PERIPHC_UART2, /* and vfir 0x68 */
371
372 /* 8 */
373 NONE(GPIO),
374 PERIPHC_SDMMC2,
375 PERIPHC_SPDIF_IN,
376 PERIPHC_I2S2,
377 PERIPHC_I2C1,
378 NONE(RESERVED13),
379 PERIPHC_SDMMC1,
380 PERIPHC_SDMMC4,
381
382 /* 16 */
383 NONE(TCW),
384 PERIPHC_PWM,
385 PERIPHC_I2S3,
386 NONE(RESERVED19),
387 PERIPHC_VI,
388 NONE(RESERVED21),
389 NONE(USBD),
390 NONE(ISP),
391
392 /* 24 */
393 NONE(RESERVED24),
394 NONE(RESERVED25),
395 PERIPHC_DISP2,
396 PERIPHC_DISP1,
397 PERIPHC_HOST1X,
398 NONE(VCP),
399 PERIPHC_I2S1,
400 NONE(CACHE2),
401
402 /* Middle word: 63:32 */
403 NONE(MEM),
404 NONE(AHBDMA),
405 NONE(APBDMA),
406 NONE(RESERVED35),
407 NONE(RESERVED36),
408 NONE(STAT_MON),
409 NONE(RESERVED38),
410 NONE(FUSE),
411
412 /* 40 */
413 NONE(KFUSE),
414 PERIPHC_SBC1, /* SBCx = SPIx */
415 PERIPHC_NOR,
416 NONE(RESERVED43),
417 PERIPHC_SBC2,
418 NONE(XIO),
419 PERIPHC_SBC3,
420 PERIPHC_I2C5,
421
422 /* 48 */
423 NONE(DSI),
424 NONE(RESERVED49),
425 PERIPHC_HSI,
426 NONE(RESERVED51),
427 NONE(CSI),
428 NONE(RESERVED53),
429 PERIPHC_I2C2,
430 PERIPHC_UART3,
431
432 /* 56 */
433 NONE(MIPI_CAL),
434 PERIPHC_EMC,
435 NONE(USB2),
436 NONE(USB3),
437 NONE(RESERVED60),
438 PERIPHC_VDE,
439 NONE(BSEA),
440 NONE(BSEV),
441
442 /* Upper word 95:64 */
443 NONE(RESERVED64),
444 PERIPHC_UART4,
445 PERIPHC_UART5,
446 PERIPHC_I2C3,
447 PERIPHC_SBC4,
448 PERIPHC_SDMMC3,
449 NONE(PCIE),
450 PERIPHC_OWR,
451
452 /* 72 */
453 NONE(AFI),
454 PERIPHC_CSITE,
455 NONE(PCIEXCLK),
456 NONE(AVPUCQ),
457 NONE(LA),
458 NONE(TRACECLKIN),
459 NONE(SOC_THERM),
460 NONE(DTV),
461
462 /* 80 */
463 NONE(RESERVED80),
464 PERIPHC_I2CSLOW,
465 NONE(DSIB),
466 PERIPHC_TSEC,
467 NONE(RESERVED84),
468 NONE(RESERVED85),
469 NONE(RESERVED86),
470 NONE(EMUCIF),
471
472 /* 88 */
473 NONE(RESERVED88),
474 NONE(XUSB_HOST),
475 NONE(RESERVED90),
476 PERIPHC_MSENC,
477 NONE(RESERVED92),
478 NONE(RESERVED93),
479 NONE(RESERVED94),
480 NONE(XUSB_DEV),
481
482 /* V word: 31:0 */
483 NONE(CPUG),
484 NONE(CPULP),
485 NONE(V_RESERVED2),
486 PERIPHC_MSELECT,
487 NONE(V_RESERVED4),
488 PERIPHC_I2S4,
489 PERIPHC_I2S5,
490 PERIPHC_I2C4,
491
492 /* 104 */
493 PERIPHC_SBC5,
494 PERIPHC_SBC6,
495 PERIPHC_AUDIO,
496 NONE(APBIF),
497 NONE(V_RESERVED12),
498 NONE(V_RESERVED13),
499 NONE(V_RESERVED14),
500 PERIPHC_HDA2CODEC2X,
501
502 /* 112 */
503 NONE(ATOMICS),
504 NONE(V_RESERVED17),
505 NONE(V_RESERVED18),
506 NONE(V_RESERVED19),
507 NONE(V_RESERVED20),
508 NONE(V_RESERVED21),
509 NONE(V_RESERVED22),
510 PERIPHC_ACTMON,
511
512 /* 120 */
513 NONE(EXTPERIPH1),
514 NONE(EXTPERIPH2),
515 NONE(EXTPERIPH3),
516 NONE(OOB),
517 PERIPHC_SATA,
518 PERIPHC_HDA,
519 NONE(TZRAM),
520 NONE(SE),
521
522 /* W word: 31:0 */
523 NONE(HDA2HDMICODEC),
524 NONE(SATACOLD),
525 NONE(W_RESERVED2),
526 NONE(W_RESERVED3),
527 NONE(W_RESERVED4),
528 NONE(W_RESERVED5),
529 NONE(W_RESERVED6),
530 NONE(W_RESERVED7),
531
532 /* 136 */
533 NONE(CEC),
534 NONE(W_RESERVED9),
535 NONE(W_RESERVED10),
536 NONE(W_RESERVED11),
537 NONE(W_RESERVED12),
538 NONE(W_RESERVED13),
539 NONE(XUSB_PADCTL),
540 NONE(W_RESERVED15),
541
542 /* 144 */
543 NONE(W_RESERVED16),
544 NONE(W_RESERVED17),
545 NONE(W_RESERVED18),
546 NONE(W_RESERVED19),
547 NONE(W_RESERVED20),
548 NONE(ENTROPY),
549 NONE(DDS),
550 NONE(W_RESERVED23),
551
552 /* 152 */
553 NONE(W_RESERVED24),
554 NONE(W_RESERVED25),
555 NONE(W_RESERVED26),
556 NONE(DVFS),
557 NONE(XUSB_SS),
558 NONE(W_RESERVED29),
559 NONE(W_RESERVED30),
560 NONE(W_RESERVED31),
561
562 /* X word: 31:0 */
563 NONE(SPARE),
564 NONE(X_RESERVED1),
565 NONE(X_RESERVED2),
566 NONE(X_RESERVED3),
567 NONE(CAM_MCLK),
568 NONE(CAM_MCLK2),
569 PERIPHC_I2C6,
570 NONE(X_RESERVED7),
571
572 /* 168 */
573 NONE(X_RESERVED8),
574 NONE(X_RESERVED9),
575 NONE(X_RESERVED10),
576 NONE(VIM2_CLK),
577 NONE(X_RESERVED12),
578 NONE(X_RESERVED13),
579 NONE(EMC_DLL),
580 NONE(X_RESERVED15),
581
582 /* 176 */
583 NONE(X_RESERVED16),
584 NONE(CLK72MHZ),
585 NONE(VIC),
586 NONE(X_RESERVED19),
587 NONE(X_RESERVED20),
588 NONE(DPAUX),
589 NONE(SOR0),
590 NONE(X_RESERVED23),
591
592 /* 184 */
593 NONE(GPU),
594 NONE(X_RESERVED25),
595 NONE(X_RESERVED26),
596 NONE(X_RESERVED27),
597 NONE(X_RESERVED28),
598 NONE(X_RESERVED29),
599 NONE(X_RESERVED30),
600 NONE(X_RESERVED31),
601
602 /* Y: 192 (192 - 223) */
603 NONE(Y_RESERVED0),
604 PERIPHC_SDMMC_LEGACY_TM,
605 PERIPHC_NVDEC,
606 PERIPHC_NVJPG,
607 NONE(Y_RESERVED4),
608 PERIPHC_DMIC3, /* 197 */
609 PERIPHC_APE, /* 198 */
610 NONE(Y_RESERVED7),
611
612 /* 200 */
613 NONE(Y_RESERVED8),
614 NONE(Y_RESERVED9),
615 NONE(Y_RESERVED10),
616 NONE(Y_RESERVED11),
617 NONE(Y_RESERVED12),
618 NONE(Y_RESERVED13),
619 NONE(Y_RESERVED14),
620 NONE(Y_RESERVED15),
621
622 /* 208 */
623 PERIPHC_VI_I2C, /* 208 */
624 NONE(Y_RESERVED17),
625 NONE(Y_RESERVED18),
626 PERIPHC_QSPI, /* 211 */
627 NONE(Y_RESERVED20),
628 NONE(Y_RESERVED21),
629 NONE(Y_RESERVED22),
630 NONE(Y_RESERVED23),
631
632 /* 216 */
633 NONE(Y_RESERVED24),
634 NONE(Y_RESERVED25),
635 NONE(Y_RESERVED26),
636 PERIPHC_NVENC, /* 219 */
637 NONE(Y_RESERVED28),
638 NONE(Y_RESERVED29),
639 NONE(Y_RESERVED30),
640 NONE(Y_RESERVED31),
641};
642
643/*
Tom Warrena8480ef2015-06-25 09:50:44 -0700[diff] [blame]644 * PLL divider shift/mask tables for all PLL IDs.
645 */
646struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = {
647 /*
648 * NOTE: If kcp_mask/kvco_mask == 0, they're not used in that PLL (PLLC, etc.)
649 * If lock_ena or lock_det are >31, they're not used in that PLL (PLLC, etc.)
650 */
651 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 10, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x1F,
652 .lock_ena = 32, .lock_det = 27, .kcp_shift = 0, .kcp_mask = 0, .kvco_shift = 0, .kvco_mask = 0 }, /* PLLC */
653 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x1F,
654 .lock_ena = 4, .lock_det = 27, .kcp_shift = 1, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLM */
655 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 10, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x1F,
656 .lock_ena = 18, .lock_det = 27, .kcp_shift = 0, .kcp_mask = 3, .kvco_shift = 2, .kvco_mask = 1 }, /* PLLP */
657 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x1F,
658 .lock_ena = 28, .lock_det = 27, .kcp_shift = 25, .kcp_mask = 3, .kvco_shift = 24, .kvco_mask = 1 }, /* PLLA */
659 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 16, .p_mask = 0x1F,
660 .lock_ena = 29, .lock_det = 27, .kcp_shift = 25, .kcp_mask = 3, .kvco_shift = 24, .kvco_mask = 1 }, /* PLLU */
661 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 11, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x07,
662 .lock_ena = 18, .lock_det = 27, .kcp_shift = 23, .kcp_mask = 3, .kvco_shift = 22, .kvco_mask = 1 }, /* PLLD */
663 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x1F,
664 .lock_ena = 18, .lock_det = 27, .kcp_shift = 1, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLX */
665 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 0, .p_mask = 0,
666 .lock_ena = 9, .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLE */
667 { .m_shift = 0, .m_mask = 0, .n_shift = 0, .n_mask = 0, .p_shift = 0, .p_mask = 0,
668 .lock_ena = 0, .lock_det = 0, .kcp_shift = 0, .kcp_mask = 0, .kvco_shift = 0, .kvco_mask = 0 }, /* PLLS (gone)*/
Simon Glassb6ba3fb2015-08-10 07:14:36 -0600[diff] [blame]669 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 19, .p_mask = 0x1F,
670 .lock_ena = 30, .lock_det = 27, .kcp_shift = 25, .kcp_mask = 3, .kvco_shift = 24, .kvco_mask = 1 }, /* PLLDP */
Tom Warrena8480ef2015-06-25 09:50:44 -0700[diff] [blame]671};
672
673/*
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]674 * Get the oscillator frequency, from the corresponding hardware configuration
Svyatoslav Ryhel7f4ab332023-02-01 10:53:01 +0200[diff] [blame]675 * field. Note that T30+ supports 3 new higher freqs.
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]676 */
677enum clock_osc_freq clock_get_osc_freq(void)
678{
679 struct clk_rst_ctlr *clkrst =
680 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
681 u32 reg;
682
683 reg = readl(&clkrst->crc_osc_ctrl);
Svyatoslav Ryhel7f4ab332023-02-01 10:53:01 +0200[diff] [blame]684 return (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]685}
686
687/* Returns a pointer to the clock source register for a peripheral */
688u32 *get_periph_source_reg(enum periph_id periph_id)
689{
690 struct clk_rst_ctlr *clkrst =
691 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
692 enum periphc_internal_id internal_id;
693
694 /* Coresight is a special case */
695 if (periph_id == PERIPH_ID_CSI)
696 return &clkrst->crc_clk_src[PERIPH_ID_CSI+1];
697
698 assert(periph_id >= PERIPH_ID_FIRST && periph_id < PERIPH_ID_COUNT);
699 internal_id = INTERNAL_ID(periph_id_to_internal_id[periph_id]);
700 assert(internal_id != -1);
701
702 if (internal_id < PERIPHC_VW_FIRST)
703 /* L, H, U */
704 return &clkrst->crc_clk_src[internal_id];
705
706 if (internal_id < PERIPHC_X_FIRST) {
707 /* VW */
708 internal_id -= PERIPHC_VW_FIRST;
709 return &clkrst->crc_clk_src_vw[internal_id];
710 }
711
712 if (internal_id < PERIPHC_Y_FIRST) {
713 /* X */
714 internal_id -= PERIPHC_X_FIRST;
715 return &clkrst->crc_clk_src_x[internal_id];
716 }
717
718 /* Y */
719 internal_id -= PERIPHC_Y_FIRST;
720 return &clkrst->crc_clk_src_y[internal_id];
721}
722
Stephen Warren532543c2016-09-13 10:45:56 -0600[diff] [blame]723int get_periph_clock_info(enum periph_id periph_id, int *mux_bits,
724 int *divider_bits, int *type)
725{
726 enum periphc_internal_id internal_id;
727
728 if (!clock_periph_id_isvalid(periph_id))
729 return -1;
730
Tom Warren3bb2f5d2020-03-27 10:24:31 -0700[diff] [blame]731 internal_id = INTERNAL_ID(periph_id_to_internal_id[periph_id]);
Stephen Warren532543c2016-09-13 10:45:56 -0600[diff] [blame]732 if (!periphc_internal_id_isvalid(internal_id))
733 return -1;
734
735 *type = clock_periph_type[internal_id];
736 if (!clock_type_id_isvalid(*type))
737 return -1;
738
739 *mux_bits = clock_source[*type][CLOCK_MAX_MUX];
740
741 if (*type == CLOCK_TYPE_PC2CC3M_T16)
742 *divider_bits = 16;
743 else
744 *divider_bits = 8;
745
746 return 0;
747}
748
749enum clock_id get_periph_clock_id(enum periph_id periph_id, int source)
750{
751 enum periphc_internal_id internal_id;
752 int type;
753
754 if (!clock_periph_id_isvalid(periph_id))
755 return CLOCK_ID_NONE;
756
Tom Warren3bb2f5d2020-03-27 10:24:31 -0700[diff] [blame]757 internal_id = INTERNAL_ID(periph_id_to_internal_id[periph_id]);
Stephen Warren532543c2016-09-13 10:45:56 -0600[diff] [blame]758 if (!periphc_internal_id_isvalid(internal_id))
759 return CLOCK_ID_NONE;
760
761 type = clock_periph_type[internal_id];
762 if (!clock_type_id_isvalid(type))
763 return CLOCK_ID_NONE;
764
765 return clock_source[type][source];
766}
767
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]768/**
769 * Given a peripheral ID and the required source clock, this returns which
770 * value should be programmed into the source mux for that peripheral.
771 *
772 * There is special code here to handle the one source type with 5 sources.
773 *
774 * @param periph_id peripheral to start
775 * @param source PLL id of required parent clock
776 * @param mux_bits Set to number of bits in mux register: 2 or 4
777 * @param divider_bits Set to number of divider bits (8 or 16)
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +0100[diff] [blame]778 * Return: mux value (0-4, or -1 if not found)
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]779 */
780int get_periph_clock_source(enum periph_id periph_id,
781 enum clock_id parent, int *mux_bits, int *divider_bits)
782{
783 enum clock_type_id type;
Stephen Warren532543c2016-09-13 10:45:56 -0600[diff] [blame]784 int mux, err;
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]785
Stephen Warren532543c2016-09-13 10:45:56 -0600[diff] [blame]786 err = get_periph_clock_info(periph_id, mux_bits, divider_bits, &type);
787 assert(!err);
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]788
789 for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
790 if (clock_source[type][mux] == parent)
791 return mux;
792
793 /* if we get here, either us or the caller has made a mistake */
794 printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id,
795 parent);
796 return -1;
797}
798
799void clock_set_enable(enum periph_id periph_id, int enable)
800{
801 struct clk_rst_ctlr *clkrst =
802 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
803 u32 *clk;
804 u32 reg;
805
806 /* Enable/disable the clock to this peripheral */
807 assert(clock_periph_id_isvalid(periph_id));
808 if ((int)periph_id < (int)PERIPH_ID_VW_FIRST)
809 clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];
810 else if ((int)periph_id < (int)PERIPH_ID_X_FIRST)
811 clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)];
812 else if ((int)periph_id < (int)PERIPH_ID_Y_FIRST)
813 clk = &clkrst->crc_clk_out_enb_x;
814 else
815 clk = &clkrst->crc_clk_out_enb_y;
816
817 reg = readl(clk);
818 if (enable)
819 reg |= PERIPH_MASK(periph_id);
820 else
821 reg &= ~PERIPH_MASK(periph_id);
822 writel(reg, clk);
823}
824
825void reset_set_enable(enum periph_id periph_id, int enable)
826{
827 struct clk_rst_ctlr *clkrst =
828 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
829 u32 *reset;
830 u32 reg;
831
832 /* Enable/disable reset to the peripheral */
833 assert(clock_periph_id_isvalid(periph_id));
834 if (periph_id < PERIPH_ID_VW_FIRST)
835 reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];
836 else if ((int)periph_id < (int)PERIPH_ID_X_FIRST)
837 reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)];
838 else if ((int)periph_id < (int)PERIPH_ID_Y_FIRST)
839 reset = &clkrst->crc_rst_devices_x;
840 else
841 reset = &clkrst->crc_rst_devices_y;
842
843 reg = readl(reset);
844 if (enable)
845 reg |= PERIPH_MASK(periph_id);
846 else
847 reg &= ~PERIPH_MASK(periph_id);
848 writel(reg, reset);
849}
850
851#ifdef CONFIG_OF_CONTROL
852/*
853 * Convert a device tree clock ID to our peripheral ID. They are mostly
854 * the same but we are very cautious so we check that a valid clock ID is
855 * provided.
856 *
857 * @param clk_id Clock ID according to tegra210 device tree binding
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +0100[diff] [blame]858 * Return: peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]859 */
860enum periph_id clk_id_to_periph_id(int clk_id)
861{
862 if (clk_id > PERIPH_ID_COUNT)
863 return PERIPH_ID_NONE;
864
865 switch (clk_id) {
866 case PERIPH_ID_RESERVED4:
867 case PERIPH_ID_RESERVED25:
868 case PERIPH_ID_RESERVED35:
869 case PERIPH_ID_RESERVED36:
870 case PERIPH_ID_RESERVED38:
871 case PERIPH_ID_RESERVED43:
872 case PERIPH_ID_RESERVED49:
873 case PERIPH_ID_RESERVED53:
874 case PERIPH_ID_RESERVED64:
875 case PERIPH_ID_RESERVED84:
876 case PERIPH_ID_RESERVED85:
877 case PERIPH_ID_RESERVED86:
878 case PERIPH_ID_RESERVED88:
879 case PERIPH_ID_RESERVED90:
880 case PERIPH_ID_RESERVED92:
881 case PERIPH_ID_RESERVED93:
882 case PERIPH_ID_RESERVED94:
883 case PERIPH_ID_V_RESERVED2:
884 case PERIPH_ID_V_RESERVED4:
885 case PERIPH_ID_V_RESERVED17:
886 case PERIPH_ID_V_RESERVED18:
887 case PERIPH_ID_V_RESERVED19:
888 case PERIPH_ID_V_RESERVED20:
889 case PERIPH_ID_V_RESERVED21:
890 case PERIPH_ID_V_RESERVED22:
891 case PERIPH_ID_W_RESERVED2:
892 case PERIPH_ID_W_RESERVED3:
893 case PERIPH_ID_W_RESERVED4:
894 case PERIPH_ID_W_RESERVED5:
895 case PERIPH_ID_W_RESERVED6:
896 case PERIPH_ID_W_RESERVED7:
897 case PERIPH_ID_W_RESERVED9:
898 case PERIPH_ID_W_RESERVED10:
899 case PERIPH_ID_W_RESERVED11:
900 case PERIPH_ID_W_RESERVED12:
901 case PERIPH_ID_W_RESERVED13:
902 case PERIPH_ID_W_RESERVED15:
903 case PERIPH_ID_W_RESERVED16:
904 case PERIPH_ID_W_RESERVED17:
905 case PERIPH_ID_W_RESERVED18:
906 case PERIPH_ID_W_RESERVED19:
907 case PERIPH_ID_W_RESERVED20:
908 case PERIPH_ID_W_RESERVED23:
909 case PERIPH_ID_W_RESERVED29:
910 case PERIPH_ID_W_RESERVED30:
911 case PERIPH_ID_W_RESERVED31:
912 return PERIPH_ID_NONE;
913 default:
914 return clk_id;
915 }
916}
917#endif /* CONFIG_OF_CONTROL */
918
919/*
920 * T210 redefines PLLP_OUT2 as PLLP_VCO/DIVP, so do different OUT1-4 setup here.
921 * PLLP_BASE/MISC/etc. is already set up for 408MHz in the BootROM.
922 */
923void tegra210_setup_pllp(void)
924{
925 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
926 u32 reg;
927
928 /* Set PLLP_OUT1, 3 & 4 freqs to 9.6, 102 & 204MHz */
929
930 /* OUT1 */
931 /* Assert RSTN before enable */
932 reg = PLLP_OUT1_RSTN_EN;
933 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]);
934 /* Set divisor and reenable */
935 reg = (IN_408_OUT_9_6_DIVISOR << PLLP_OUT1_RATIO)
936 | PLLP_OUT1_OVR | PLLP_OUT1_CLKEN | PLLP_OUT1_RSTN_DIS;
937 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]);
938
939 /* OUT3, 4 */
940 /* Assert RSTN before enable */
941 reg = PLLP_OUT4_RSTN_EN | PLLP_OUT3_RSTN_EN;
942 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]);
943 /* Set divisor and reenable */
944 reg = (IN_408_OUT_204_DIVISOR << PLLP_OUT4_RATIO)
945 | PLLP_OUT4_OVR | PLLP_OUT4_CLKEN | PLLP_OUT4_RSTN_DIS
946 | (IN_408_OUT_102_DIVISOR << PLLP_OUT3_RATIO)
947 | PLLP_OUT3_OVR | PLLP_OUT3_CLKEN | PLLP_OUT3_RSTN_DIS;
948 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]);
949
950 /*
951 * NOTE: If you want to change PLLP_OUT2 away from 204MHz,
952 * you can change PLLP_BASE DIVP here. Currently defaults
953 * to 1, which is 2^1, or 2, so PLLP_OUT2 is 204MHz.
954 * See Table 13 in section 5.1.4 in T210 TRM for more info.
955 */
956}
957
958void clock_early_init(void)
959{
960 struct clk_rst_ctlr *clkrst =
961 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
Tom Warrena8480ef2015-06-25 09:50:44 -0700[diff] [blame]962 struct clk_pll_info *pllinfo = &tegra_pll_info_table[CLOCK_ID_DISPLAY];
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]963 u32 data;
964
965 tegra210_setup_pllp();
966
967 /*
968 * PLLC output frequency set to 600Mhz
969 * PLLD output frequency set to 925Mhz
970 */
971 switch (clock_get_osc_freq()) {
972 case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
Svyatoslav Ryhel7f4ab332023-02-01 10:53:01 +0200[diff] [blame]973 case CLOCK_OSC_FREQ_48_0: /* OSC is 48Mhz */
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]974 clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8);
975 clock_set_rate(CLOCK_ID_DISPLAY, 925, 12, 0, 12);
976 break;
977
978 case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
979 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
980 clock_set_rate(CLOCK_ID_DISPLAY, 925, 26, 0, 12);
981 break;
982
983 case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
Svyatoslav Ryhel7f4ab332023-02-01 10:53:01 +0200[diff] [blame]984 case CLOCK_OSC_FREQ_16_8: /* OSC is 16.8Mhz */
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]985 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
986 clock_set_rate(CLOCK_ID_DISPLAY, 925, 13, 0, 12);
987 break;
988 case CLOCK_OSC_FREQ_19_2:
989 clock_set_rate(CLOCK_ID_CGENERAL, 125, 4, 0, 0);
990 clock_set_rate(CLOCK_ID_DISPLAY, 96, 2, 0, 12);
991 break;
Tom Warren27bce712015-06-22 13:03:44 -0700[diff] [blame]992 case CLOCK_OSC_FREQ_38_4:
993 clock_set_rate(CLOCK_ID_CGENERAL, 125, 8, 0, 0);
994 clock_set_rate(CLOCK_ID_DISPLAY, 96, 4, 0, 0);
995 break;
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]996 default:
997 /*
998 * These are not supported. It is too early to print a
999 * message and the UART likely won't work anyway due to the
1000 * oscillator being wrong.
1001 */
1002 break;
1003 }
1004
1005 /* PLLC_MISC1: Turn IDDQ off. NOTE: T210 PLLC_MISC_1 maps to pll_misc */
1006 clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc,
1007 (1 << PLLC_IDDQ));
1008 udelay(2);
1009
1010 /*
1011 * PLLC_MISC: Take PLLC out of reset. NOTE: T210 PLLC_MISC maps
1012 * to pll_out[1]
1013 */
1014 clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1],
1015 (1 << PLLC_RESET));
1016 udelay(2);
1017
1018 /* PLLD_MISC: Set CLKENABLE and LOCK_DETECT bits */
Tom Warrena8480ef2015-06-25 09:50:44 -0700[diff] [blame]1019 data = (1 << PLLD_ENABLE_CLK) | (1 << pllinfo->lock_ena);
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1020 writel(data, &clkrst->crc_pll[CLOCK_ID_DISPLAY].pll_misc);
1021 udelay(2);
1022}
1023
Thierry Redingfa6e24d2015-08-20 11:42:19 +0200[diff] [blame]1024unsigned int clk_m_get_rate(unsigned parent_rate)
1025{
1026 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
1027 u32 value, div;
1028
1029 value = readl(&clkrst->crc_spare_reg0);
1030 div = ((value >> 2) & 0x3) + 1;
1031
1032 return parent_rate / div;
1033}
1034
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1035void arch_timer_init(void)
1036{
1037 struct sysctr_ctlr *sysctr = (struct sysctr_ctlr *)NV_PA_TSC_BASE;
1038 u32 freq, val;
1039
Thierry Reding4c3aaa72015-08-20 11:42:20 +0200[diff] [blame]1040 freq = clock_get_rate(CLOCK_ID_CLK_M);
1041 debug("%s: clk_m freq is %dHz [0x%08X]\n", __func__, freq, freq);
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1042
Thierry Reding4c3aaa72015-08-20 11:42:20 +0200[diff] [blame]1043 if (current_el() == 3)
1044 asm("msr cntfrq_el0, %0\n" : : "r" (freq));
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1045
1046 /* Only Tegra114+ has the System Counter regs */
1047 debug("%s: setting CNTFID0 to 0x%08X\n", __func__, freq);
1048 writel(freq, &sysctr->cntfid0);
1049
1050 val = readl(&sysctr->cntcr);
1051 val |= TSC_CNTCR_ENABLE | TSC_CNTCR_HDBG;
1052 writel(val, &sysctr->cntcr);
1053 debug("%s: TSC CNTCR = 0x%08X\n", __func__, val);
1054}
1055
Stephen Warren553b61e2015-10-05 16:58:52 -0600[diff] [blame]1056#define PLLREFE_MISC 0x4c8
1057#define PLLREFE_MISC_LOCK BIT(27)
1058#define PLLREFE_MISC_IDDQ BIT(24)
1059
1060#define PLLREFE_BASE 0x4c4
1061#define PLLREFE_BASE_BYPASS BIT(31)
1062#define PLLREFE_BASE_ENABLE BIT(30)
1063#define PLLREFE_BASE_REF_DIS BIT(29)
1064#define PLLREFE_BASE_KCP(kcp) (((kcp) & 0x3) << 27)
1065#define PLLREFE_BASE_KVCO BIT(26)
1066#define PLLREFE_BASE_DIVP(p) (((p) & 0x1f) << 16)
1067#define PLLREFE_BASE_DIVN(n) (((n) & 0xff) << 8)
1068#define PLLREFE_BASE_DIVM(m) (((m) & 0xff) << 0)
1069
1070static int tegra_pllref_enable(void)
1071{
1072 u32 value;
1073 unsigned long start;
1074
1075 /*
1076 * This sequence comes from Tegra X1 TRM section "Cold Boot, with no
1077 * Recovery Mode or Boot from USB", sub-section "PLLREFE".
1078 */
1079
1080 value = readl(NV_PA_CLK_RST_BASE + PLLREFE_MISC);
1081 value &= ~PLLREFE_MISC_IDDQ;
1082 writel(value, NV_PA_CLK_RST_BASE + PLLREFE_MISC);
1083
1084 udelay(5);
1085
1086 value = PLLREFE_BASE_ENABLE |
1087 PLLREFE_BASE_KCP(0) |
1088 PLLREFE_BASE_DIVP(0) |
1089 PLLREFE_BASE_DIVN(0x41) |
1090 PLLREFE_BASE_DIVM(4);
1091 writel(value, NV_PA_CLK_RST_BASE + PLLREFE_BASE);
1092
1093 debug("waiting for pllrefe lock\n");
1094 start = get_timer(0);
1095 while (get_timer(start) < 250) {
1096 value = readl(NV_PA_CLK_RST_BASE + PLLREFE_MISC);
1097 if (value & PLLREFE_MISC_LOCK)
1098 break;
1099 }
1100 if (!(value & PLLREFE_MISC_LOCK)) {
1101 debug(" timeout\n");
1102 return -ETIMEDOUT;
1103 }
1104 debug(" done\n");
1105
1106 return 0;
1107}
1108
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1109#define PLLE_SS_CNTL 0x68
1110#define PLLE_SS_CNTL_SSCINCINTR(x) (((x) & 0x3f) << 24)
1111#define PLLE_SS_CNTL_SSCINC(x) (((x) & 0xff) << 16)
1112#define PLLE_SS_CNTL_SSCINVERT (1 << 15)
1113#define PLLE_SS_CNTL_SSCCENTER (1 << 14)
1114#define PLLE_SS_CNTL_SSCBYP (1 << 12)
1115#define PLLE_SS_CNTL_INTERP_RESET (1 << 11)
1116#define PLLE_SS_CNTL_BYPASS_SS (1 << 10)
1117#define PLLE_SS_CNTL_SSCMAX(x) (((x) & 0x1ff) << 0)
1118
1119#define PLLE_BASE 0x0e8
Stephen Warren553b61e2015-10-05 16:58:52 -0600[diff] [blame]1120#define PLLE_BASE_ENABLE (1 << 31)
1121#define PLLE_BASE_PLDIV_CML(x) (((x) & 0x1f) << 24)
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1122#define PLLE_BASE_NDIV(x) (((x) & 0xff) << 8)
1123#define PLLE_BASE_MDIV(x) (((x) & 0xff) << 0)
1124
1125#define PLLE_MISC 0x0ec
1126#define PLLE_MISC_IDDQ_SWCTL (1 << 14)
Stephen Warren553b61e2015-10-05 16:58:52 -0600[diff] [blame]1127#define PLLE_MISC_IDDQ_OVERRIDE_VALUE (1 << 13)
1128#define PLLE_MISC_LOCK (1 << 11)
Stephen Warrenb6409f22016-03-22 09:45:36 -0600[diff] [blame]1129#define PLLE_PTS (1 << 8)
Stephen Warren553b61e2015-10-05 16:58:52 -0600[diff] [blame]1130#define PLLE_MISC_KCP(x) (((x) & 0x3) << 6)
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1131#define PLLE_MISC_VREG_CTRL(x) (((x) & 0x3) << 2)
Stephen Warren553b61e2015-10-05 16:58:52 -0600[diff] [blame]1132#define PLLE_MISC_KVCO (1 << 0)
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1133
1134#define PLLE_AUX 0x48c
Stephen Warren553b61e2015-10-05 16:58:52 -0600[diff] [blame]1135#define PLLE_AUX_SS_SEQ_INCLUDE (1 << 31)
1136#define PLLE_AUX_REF_SEL_PLLREFE (1 << 28)
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1137#define PLLE_AUX_SEQ_ENABLE (1 << 24)
Stephen Warren553b61e2015-10-05 16:58:52 -0600[diff] [blame]1138#define PLLE_AUX_SS_SWCTL (1 << 6)
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1139#define PLLE_AUX_ENABLE_SWCTL (1 << 4)
Stephen Warren553b61e2015-10-05 16:58:52 -0600[diff] [blame]1140#define PLLE_AUX_USE_LOCKDET (1 << 3)
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1141
1142int tegra_plle_enable(void)
1143{
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1144 u32 value;
Stephen Warren553b61e2015-10-05 16:58:52 -0600[diff] [blame]1145 unsigned long start;
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1146
Stephen Warren553b61e2015-10-05 16:58:52 -0600[diff] [blame]1147 /* PLLREF feeds PLLE */
1148 tegra_pllref_enable();
1149
1150 /*
1151 * This sequence comes from Tegra X1 TRM section "Cold Boot, with no
1152 * Recovery Mode or Boot from USB", sub-section "PLLEs".
1153 */
1154
1155 /* 1. Select XTAL as the source */
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1156
1157 value = readl(NV_PA_CLK_RST_BASE + PLLE_AUX);
Stephen Warren553b61e2015-10-05 16:58:52 -0600[diff] [blame]1158 value &= ~PLLE_AUX_REF_SEL_PLLREFE;
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1159 writel(value, NV_PA_CLK_RST_BASE + PLLE_AUX);
1160
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1161 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
Stephen Warren553b61e2015-10-05 16:58:52 -0600[diff] [blame]1162 value &= ~PLLE_MISC_IDDQ_OVERRIDE_VALUE;
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1163 writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC);
1164
Stephen Warren553b61e2015-10-05 16:58:52 -0600[diff] [blame]1165 /* 2. Wait 5 us */
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1166 udelay(5);
1167
Stephen Warren553b61e2015-10-05 16:58:52 -0600[diff] [blame]1168 /*
1169 * 3. Program the following registers to generate a low jitter 100MHz
1170 * clock.
1171 */
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1172
1173 value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
Stephen Warren553b61e2015-10-05 16:58:52 -0600[diff] [blame]1174 value &= ~PLLE_BASE_PLDIV_CML(0x1f);
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1175 value &= ~PLLE_BASE_NDIV(0xff);
1176 value &= ~PLLE_BASE_MDIV(0xff);
Stephen Warren553b61e2015-10-05 16:58:52 -0600[diff] [blame]1177 value |= PLLE_BASE_PLDIV_CML(0xe);
1178 value |= PLLE_BASE_NDIV(0x7d);
1179 value |= PLLE_BASE_MDIV(2);
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1180 writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
1181
Stephen Warren553b61e2015-10-05 16:58:52 -0600[diff] [blame]1182 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
Stephen Warrenb6409f22016-03-22 09:45:36 -0600[diff] [blame]1183 value |= PLLE_PTS;
Stephen Warren553b61e2015-10-05 16:58:52 -0600[diff] [blame]1184 value &= ~PLLE_MISC_KCP(3);
1185 value &= ~PLLE_MISC_VREG_CTRL(3);
1186 value &= ~PLLE_MISC_KVCO;
1187 writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC);
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1188
1189 value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
1190 value |= PLLE_BASE_ENABLE;
1191 writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
1192
Stephen Warren553b61e2015-10-05 16:58:52 -0600[diff] [blame]1193 /* 4. Wait for LOCK */
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1194
Stephen Warren553b61e2015-10-05 16:58:52 -0600[diff] [blame]1195 debug("waiting for plle lock\n");
1196 start = get_timer(0);
1197 while (get_timer(start) < 250) {
1198 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
1199 if (value & PLLE_MISC_LOCK)
1200 break;
1201 }
1202 if (!(value & PLLE_MISC_LOCK)) {
1203 debug(" timeout\n");
1204 return -ETIMEDOUT;
1205 }
1206 debug(" done\n");
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1207
Stephen Warren553b61e2015-10-05 16:58:52 -0600[diff] [blame]1208 /* 5. Enable SSA */
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1209
1210 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
Stephen Warren553b61e2015-10-05 16:58:52 -0600[diff] [blame]1211 value &= ~PLLE_SS_CNTL_SSCINC(0xff);
1212 value |= PLLE_SS_CNTL_SSCINC(1);
1213 value &= ~PLLE_SS_CNTL_SSCINCINTR(0x3f);
1214 value |= PLLE_SS_CNTL_SSCINCINTR(0x23);
1215 value &= ~PLLE_SS_CNTL_SSCMAX(0x1fff);
1216 value |= PLLE_SS_CNTL_SSCMAX(0x21);
1217 value &= ~PLLE_SS_CNTL_SSCINVERT;
1218 value &= ~PLLE_SS_CNTL_SSCCENTER;
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1219 value &= ~PLLE_SS_CNTL_BYPASS_SS;
Stephen Warren553b61e2015-10-05 16:58:52 -0600[diff] [blame]1220 value &= ~PLLE_SS_CNTL_SSCBYP;
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1221 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
1222
Stephen Warren553b61e2015-10-05 16:58:52 -0600[diff] [blame]1223 /* 6. Wait 300 ns */
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1224
Stephen Warren553b61e2015-10-05 16:58:52 -0600[diff] [blame]1225 udelay(1);
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1226 value &= ~PLLE_SS_CNTL_INTERP_RESET;
1227 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
1228
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1229 return 0;
1230}
Stephen Warren1453d102016-09-13 10:45:55 -0600[diff] [blame]1231
1232struct periph_clk_init periph_clk_init_table[] = {
1233 { PERIPH_ID_SBC1, CLOCK_ID_PERIPH },
1234 { PERIPH_ID_SBC2, CLOCK_ID_PERIPH },
1235 { PERIPH_ID_SBC3, CLOCK_ID_PERIPH },
1236 { PERIPH_ID_SBC4, CLOCK_ID_PERIPH },
1237 { PERIPH_ID_SBC5, CLOCK_ID_PERIPH },
1238 { PERIPH_ID_SBC6, CLOCK_ID_PERIPH },
1239 { PERIPH_ID_HOST1X, CLOCK_ID_PERIPH },
Stephen Warren1453d102016-09-13 10:45:55 -0600[diff] [blame]1240 { PERIPH_ID_SDMMC1, CLOCK_ID_PERIPH },
1241 { PERIPH_ID_SDMMC2, CLOCK_ID_PERIPH },
1242 { PERIPH_ID_SDMMC3, CLOCK_ID_PERIPH },
1243 { PERIPH_ID_SDMMC4, CLOCK_ID_PERIPH },
1244 { PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ },
1245 { PERIPH_ID_I2C1, CLOCK_ID_PERIPH },
1246 { PERIPH_ID_I2C2, CLOCK_ID_PERIPH },
1247 { PERIPH_ID_I2C3, CLOCK_ID_PERIPH },
1248 { PERIPH_ID_I2C4, CLOCK_ID_PERIPH },
1249 { PERIPH_ID_I2C5, CLOCK_ID_PERIPH },
1250 { PERIPH_ID_I2C6, CLOCK_ID_PERIPH },
1251 { -1, },
1252};