Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
Peter Howard | 9ed4f70 | 2015-03-23 09:19:56 +1100 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ |
| 4 | * |
| 5 | * Based on davinci_dvevm.h. Original Copyrights follow: |
| 6 | * |
| 7 | * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> |
Peter Howard | 9ed4f70 | 2015-03-23 09:19:56 +1100 | [diff] [blame] | 8 | */ |
| 9 | |
| 10 | #ifndef __CONFIG_H |
| 11 | #define __CONFIG_H |
| 12 | |
| 13 | /* |
| 14 | * Board |
| 15 | */ |
Peter Howard | 9ed4f70 | 2015-03-23 09:19:56 +1100 | [diff] [blame] | 16 | |
| 17 | /* |
| 18 | * SoC Configuration |
| 19 | */ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 20 | #define CFG_SYS_OSCIN_FREQ 24000000 |
| 21 | #define CFG_SYS_TIMERBASE DAVINCI_TIMER0_BASE |
| 22 | #define CFG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) |
Peter Howard | 9ed4f70 | 2015-03-23 09:19:56 +1100 | [diff] [blame] | 23 | |
| 24 | /* |
| 25 | * Memory Info |
| 26 | */ |
Peter Howard | 9ed4f70 | 2015-03-23 09:19:56 +1100 | [diff] [blame] | 27 | #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ |
| 28 | #define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */ |
Tom Rini | db9c39e | 2022-12-04 10:04:51 -0500 | [diff] [blame] | 29 | #define CFG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ |
Peter Howard | 9ed4f70 | 2015-03-23 09:19:56 +1100 | [diff] [blame] | 30 | |
| 31 | /* memtest start addr */ |
Peter Howard | 9ed4f70 | 2015-03-23 09:19:56 +1100 | [diff] [blame] | 32 | |
| 33 | /* memtest will be run on 16MB */ |
Peter Howard | 9ed4f70 | 2015-03-23 09:19:56 +1100 | [diff] [blame] | 34 | |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 35 | #define CFG_SYS_DA850_SYSCFG_SUSPSRC ( \ |
Peter Howard | 9ed4f70 | 2015-03-23 09:19:56 +1100 | [diff] [blame] | 36 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \ |
| 37 | DAVINCI_SYSCFG_SUSPSRC_SPI1 | \ |
| 38 | DAVINCI_SYSCFG_SUSPSRC_UART2 | \ |
| 39 | DAVINCI_SYSCFG_SUSPSRC_EMAC | \ |
| 40 | DAVINCI_SYSCFG_SUSPSRC_I2C) |
| 41 | |
| 42 | /* |
| 43 | * PLL configuration |
| 44 | */ |
Peter Howard | 9ed4f70 | 2015-03-23 09:19:56 +1100 | [diff] [blame] | 45 | |
David Lechner | 5425f2d | 2018-03-14 20:36:30 -0500 | [diff] [blame] | 46 | /* Requires CONFIG_SYS_DA850_PLL0_POSTDIV=0, set in Kconfig */ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 47 | #define CFG_SYS_DA850_PLL0_PLLM 18 |
| 48 | #define CFG_SYS_DA850_PLL1_PLLM 21 |
Peter Howard | 9ed4f70 | 2015-03-23 09:19:56 +1100 | [diff] [blame] | 49 | |
| 50 | /* |
Fabien Parent | 7b3cece | 2016-11-29 14:23:39 +0100 | [diff] [blame] | 51 | * DDR2 memory configuration |
| 52 | */ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 53 | #define CFG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \ |
Fabien Parent | 7b3cece | 2016-11-29 14:23:39 +0100 | [diff] [blame] | 54 | DV_DDR_PHY_EXT_STRBEN | \ |
| 55 | (0x5 << DV_DDR_PHY_RD_LATENCY_SHIFT)) |
| 56 | |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 57 | #define CFG_SYS_DA850_DDR2_SDBCR ( \ |
Fabien Parent | 7b3cece | 2016-11-29 14:23:39 +0100 | [diff] [blame] | 58 | (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \ |
| 59 | (1 << DV_DDR_SDCR_DDREN_SHIFT) | \ |
| 60 | (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \ |
| 61 | (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \ |
| 62 | (4 << DV_DDR_SDCR_CL_SHIFT) | \ |
| 63 | (3 << DV_DDR_SDCR_IBANK_SHIFT) | \ |
| 64 | (2 << DV_DDR_SDCR_PAGESIZE_SHIFT)) |
| 65 | |
| 66 | /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 67 | #define CFG_SYS_DA850_DDR2_SDBCR2 0 |
Fabien Parent | 7b3cece | 2016-11-29 14:23:39 +0100 | [diff] [blame] | 68 | |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 69 | #define CFG_SYS_DA850_DDR2_SDTIMR ( \ |
Fabien Parent | 7b3cece | 2016-11-29 14:23:39 +0100 | [diff] [blame] | 70 | (19 << DV_DDR_SDTMR1_RFC_SHIFT) | \ |
| 71 | (1 << DV_DDR_SDTMR1_RP_SHIFT) | \ |
| 72 | (1 << DV_DDR_SDTMR1_RCD_SHIFT) | \ |
| 73 | (2 << DV_DDR_SDTMR1_WR_SHIFT) | \ |
| 74 | (6 << DV_DDR_SDTMR1_RAS_SHIFT) | \ |
| 75 | (8 << DV_DDR_SDTMR1_RC_SHIFT) | \ |
| 76 | (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \ |
| 77 | (1 << DV_DDR_SDTMR1_WTR_SHIFT)) |
| 78 | |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 79 | #define CFG_SYS_DA850_DDR2_SDTIMR2 ( \ |
Fabien Parent | 7b3cece | 2016-11-29 14:23:39 +0100 | [diff] [blame] | 80 | (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \ |
| 81 | (2 << DV_DDR_SDTMR2_XP_SHIFT) | \ |
| 82 | (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \ |
Sekhar Nori | d53dbf3 | 2017-06-02 18:07:12 +0530 | [diff] [blame] | 83 | (20 << DV_DDR_SDTMR2_XSNR_SHIFT) | \ |
Fabien Parent | 7b3cece | 2016-11-29 14:23:39 +0100 | [diff] [blame] | 84 | (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \ |
| 85 | (1 << DV_DDR_SDTMR2_RTP_SHIFT) | \ |
| 86 | (2 << DV_DDR_SDTMR2_CKE_SHIFT)) |
| 87 | |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 88 | #define CFG_SYS_DA850_DDR2_SDRCR 0x00000492 |
| 89 | #define CFG_SYS_DA850_DDR2_PBBPR 0x30 |
Fabien Parent | 7b3cece | 2016-11-29 14:23:39 +0100 | [diff] [blame] | 90 | |
| 91 | /* |
Peter Howard | 9ed4f70 | 2015-03-23 09:19:56 +1100 | [diff] [blame] | 92 | * Serial Driver info |
| 93 | */ |
Tom Rini | df6a215 | 2022-11-16 13:10:28 -0500 | [diff] [blame] | 94 | #define CFG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) |
Peter Howard | 9ed4f70 | 2015-03-23 09:19:56 +1100 | [diff] [blame] | 95 | |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 96 | #define CFG_SYS_SPI_BASE DAVINCI_SPI1_BASE |
| 97 | #define CFG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID) |
Peter Howard | 9ed4f70 | 2015-03-23 09:19:56 +1100 | [diff] [blame] | 98 | |
Peter Howard | 9ed4f70 | 2015-03-23 09:19:56 +1100 | [diff] [blame] | 99 | /* |
| 100 | * I2C Configuration |
| 101 | */ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 102 | #define CFG_SYS_I2C_EXPANDER_ADDR 0x20 |
Peter Howard | 9ed4f70 | 2015-03-23 09:19:56 +1100 | [diff] [blame] | 103 | |
| 104 | /* |
| 105 | * Flash & Environment |
| 106 | */ |
Miquel Raynal | d093536 | 2019-10-03 19:50:03 +0200 | [diff] [blame] | 107 | #ifdef CONFIG_MTD_RAW_NAND |
Tom Rini | b421349 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 108 | #define CFG_SYS_NAND_CS 3 |
| 109 | #define CFG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE |
| 110 | #define CFG_SYS_NAND_MASK_CLE 0x10 |
| 111 | #define CFG_SYS_NAND_MASK_ALE 0x8 |
Tom Rini | b421349 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 112 | #define CFG_SYS_NAND_U_BOOT_SIZE SZ_512K |
| 113 | #define CFG_SYS_NAND_U_BOOT_DST 0xc1080000 |
| 114 | #define CFG_SYS_NAND_U_BOOT_START CFG_SYS_NAND_U_BOOT_DST |
| 115 | #define CFG_SYS_NAND_ECCPOS { \ |
Fabien Parent | 7f04072 | 2016-12-05 19:15:21 +0100 | [diff] [blame] | 116 | 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \ |
| 117 | 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \ |
| 118 | 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ |
| 119 | 54, 55, 56, 57, 58, 59, 60, 61, 62, 63 } |
Tom Rini | b421349 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 120 | #define CFG_SYS_NAND_ECCSIZE 512 |
| 121 | #define CFG_SYS_NAND_ECCBYTES 10 |
Peter Howard | 9ed4f70 | 2015-03-23 09:19:56 +1100 | [diff] [blame] | 122 | #endif |
| 123 | |
Peter Howard | 9ed4f70 | 2015-03-23 09:19:56 +1100 | [diff] [blame] | 124 | /* |
Peter Howard | 9ed4f70 | 2015-03-23 09:19:56 +1100 | [diff] [blame] | 125 | * U-Boot general configuration |
| 126 | */ |
Peter Howard | 9ed4f70 | 2015-03-23 09:19:56 +1100 | [diff] [blame] | 127 | |
| 128 | /* |
| 129 | * Linux Information |
| 130 | */ |
| 131 | #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) |
Sekhar Nori | b261dce | 2017-04-06 14:52:55 +0530 | [diff] [blame] | 132 | |
| 133 | #define DEFAULT_LINUX_BOOT_ENV \ |
| 134 | "loadaddr=0xc0700000\0" \ |
Fabien Parent | 6b70b13 | 2016-11-29 17:15:03 +0100 | [diff] [blame] | 135 | "fdtaddr=0xc0600000\0" \ |
Sekhar Nori | b261dce | 2017-04-06 14:52:55 +0530 | [diff] [blame] | 136 | "scriptaddr=0xc0600000\0" |
| 137 | |
Sekhar Nori | 5bf9390 | 2017-04-06 14:52:57 +0530 | [diff] [blame] | 138 | #include <environment/ti/mmc.h> |
| 139 | |
Tom Rini | c9edebe | 2022-12-04 10:03:50 -0500 | [diff] [blame] | 140 | #define CFG_EXTRA_ENV_SETTINGS \ |
Sekhar Nori | b261dce | 2017-04-06 14:52:55 +0530 | [diff] [blame] | 141 | DEFAULT_LINUX_BOOT_ENV \ |
Sekhar Nori | 5bf9390 | 2017-04-06 14:52:57 +0530 | [diff] [blame] | 142 | DEFAULT_MMC_TI_ARGS \ |
| 143 | "bootpart=0:2\0" \ |
| 144 | "bootdir=/boot\0" \ |
| 145 | "bootfile=zImage\0" \ |
Fabien Parent | 6b70b13 | 2016-11-29 17:15:03 +0100 | [diff] [blame] | 146 | "fdtfile=da850-lcdk.dtb\0" \ |
Sekhar Nori | 5bf9390 | 2017-04-06 14:52:57 +0530 | [diff] [blame] | 147 | "boot_fdt=yes\0" \ |
| 148 | "boot_fit=0\0" \ |
| 149 | "console=ttyS2,115200n8\0" |
Peter Howard | 9ed4f70 | 2015-03-23 09:19:56 +1100 | [diff] [blame] | 150 | |
Peter Howard | 9ed4f70 | 2015-03-23 09:19:56 +1100 | [diff] [blame] | 151 | /* SD/MMC */ |
Peter Howard | 9ed4f70 | 2015-03-23 09:19:56 +1100 | [diff] [blame] | 152 | |
Peter Howard | 9ed4f70 | 2015-03-23 09:19:56 +1100 | [diff] [blame] | 153 | /* defines for SPL */ |
Peter Howard | 9ed4f70 | 2015-03-23 09:19:56 +1100 | [diff] [blame] | 154 | |
| 155 | /* additions for new relocation code, must added to all boards */ |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 156 | #define CFG_SYS_SDRAM_BASE 0xc0000000 |
Simon Glass | ce3574f | 2017-05-17 08:23:09 -0600 | [diff] [blame] | 157 | |
| 158 | #include <asm/arch/hardware.h> |
| 159 | |
Peter Howard | 9ed4f70 | 2015-03-23 09:19:56 +1100 | [diff] [blame] | 160 | #endif /* __CONFIG_H */ |