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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0 */
Peter Howard9ed4f702015-03-23 09:19:56 +11002/*
3 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
4 *
5 * Based on davinci_dvevm.h. Original Copyrights follow:
6 *
7 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
Peter Howard9ed4f702015-03-23 09:19:56 +11008 */
9
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13/*
14 * Board
15 */
Peter Howard9ed4f702015-03-23 09:19:56 +110016
17/*
18 * SoC Configuration
19 */
Tom Rini6a5dccc2022-11-16 13:10:41 -050020#define CFG_SYS_OSCIN_FREQ 24000000
21#define CFG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
22#define CFG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
Peter Howard9ed4f702015-03-23 09:19:56 +110023
24/*
25 * Memory Info
26 */
Peter Howard9ed4f702015-03-23 09:19:56 +110027#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
28#define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */
Tom Rinidb9c39e2022-12-04 10:04:51 -050029#define CFG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
Peter Howard9ed4f702015-03-23 09:19:56 +110030
31/* memtest start addr */
Peter Howard9ed4f702015-03-23 09:19:56 +110032
33/* memtest will be run on 16MB */
Peter Howard9ed4f702015-03-23 09:19:56 +110034
Tom Rini6a5dccc2022-11-16 13:10:41 -050035#define CFG_SYS_DA850_SYSCFG_SUSPSRC ( \
Peter Howard9ed4f702015-03-23 09:19:56 +110036 DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \
37 DAVINCI_SYSCFG_SUSPSRC_SPI1 | \
38 DAVINCI_SYSCFG_SUSPSRC_UART2 | \
39 DAVINCI_SYSCFG_SUSPSRC_EMAC | \
40 DAVINCI_SYSCFG_SUSPSRC_I2C)
41
42/*
43 * PLL configuration
44 */
Peter Howard9ed4f702015-03-23 09:19:56 +110045
David Lechner5425f2d2018-03-14 20:36:30 -050046/* Requires CONFIG_SYS_DA850_PLL0_POSTDIV=0, set in Kconfig */
Tom Rini6a5dccc2022-11-16 13:10:41 -050047#define CFG_SYS_DA850_PLL0_PLLM 18
48#define CFG_SYS_DA850_PLL1_PLLM 21
Peter Howard9ed4f702015-03-23 09:19:56 +110049
50/*
Fabien Parent7b3cece2016-11-29 14:23:39 +010051 * DDR2 memory configuration
52 */
Tom Rini6a5dccc2022-11-16 13:10:41 -050053#define CFG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
Fabien Parent7b3cece2016-11-29 14:23:39 +010054 DV_DDR_PHY_EXT_STRBEN | \
55 (0x5 << DV_DDR_PHY_RD_LATENCY_SHIFT))
56
Tom Rini6a5dccc2022-11-16 13:10:41 -050057#define CFG_SYS_DA850_DDR2_SDBCR ( \
Fabien Parent7b3cece2016-11-29 14:23:39 +010058 (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \
59 (1 << DV_DDR_SDCR_DDREN_SHIFT) | \
60 (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \
61 (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \
62 (4 << DV_DDR_SDCR_CL_SHIFT) | \
63 (3 << DV_DDR_SDCR_IBANK_SHIFT) | \
64 (2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
65
66/* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
Tom Rini6a5dccc2022-11-16 13:10:41 -050067#define CFG_SYS_DA850_DDR2_SDBCR2 0
Fabien Parent7b3cece2016-11-29 14:23:39 +010068
Tom Rini6a5dccc2022-11-16 13:10:41 -050069#define CFG_SYS_DA850_DDR2_SDTIMR ( \
Fabien Parent7b3cece2016-11-29 14:23:39 +010070 (19 << DV_DDR_SDTMR1_RFC_SHIFT) | \
71 (1 << DV_DDR_SDTMR1_RP_SHIFT) | \
72 (1 << DV_DDR_SDTMR1_RCD_SHIFT) | \
73 (2 << DV_DDR_SDTMR1_WR_SHIFT) | \
74 (6 << DV_DDR_SDTMR1_RAS_SHIFT) | \
75 (8 << DV_DDR_SDTMR1_RC_SHIFT) | \
76 (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \
77 (1 << DV_DDR_SDTMR1_WTR_SHIFT))
78
Tom Rini6a5dccc2022-11-16 13:10:41 -050079#define CFG_SYS_DA850_DDR2_SDTIMR2 ( \
Fabien Parent7b3cece2016-11-29 14:23:39 +010080 (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \
81 (2 << DV_DDR_SDTMR2_XP_SHIFT) | \
82 (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \
Sekhar Norid53dbf32017-06-02 18:07:12 +053083 (20 << DV_DDR_SDTMR2_XSNR_SHIFT) | \
Fabien Parent7b3cece2016-11-29 14:23:39 +010084 (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \
85 (1 << DV_DDR_SDTMR2_RTP_SHIFT) | \
86 (2 << DV_DDR_SDTMR2_CKE_SHIFT))
87
Tom Rini6a5dccc2022-11-16 13:10:41 -050088#define CFG_SYS_DA850_DDR2_SDRCR 0x00000492
89#define CFG_SYS_DA850_DDR2_PBBPR 0x30
Fabien Parent7b3cece2016-11-29 14:23:39 +010090
91/*
Peter Howard9ed4f702015-03-23 09:19:56 +110092 * Serial Driver info
93 */
Tom Rinidf6a2152022-11-16 13:10:28 -050094#define CFG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
Peter Howard9ed4f702015-03-23 09:19:56 +110095
Tom Rini6a5dccc2022-11-16 13:10:41 -050096#define CFG_SYS_SPI_BASE DAVINCI_SPI1_BASE
97#define CFG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
Peter Howard9ed4f702015-03-23 09:19:56 +110098
Peter Howard9ed4f702015-03-23 09:19:56 +110099/*
100 * I2C Configuration
101 */
Tom Rini6a5dccc2022-11-16 13:10:41 -0500102#define CFG_SYS_I2C_EXPANDER_ADDR 0x20
Peter Howard9ed4f702015-03-23 09:19:56 +1100103
104/*
105 * Flash & Environment
106 */
Miquel Raynald0935362019-10-03 19:50:03 +0200107#ifdef CONFIG_MTD_RAW_NAND
Tom Rinib4213492022-11-12 17:36:51 -0500108#define CFG_SYS_NAND_CS 3
109#define CFG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
110#define CFG_SYS_NAND_MASK_CLE 0x10
111#define CFG_SYS_NAND_MASK_ALE 0x8
Tom Rinib4213492022-11-12 17:36:51 -0500112#define CFG_SYS_NAND_U_BOOT_SIZE SZ_512K
113#define CFG_SYS_NAND_U_BOOT_DST 0xc1080000
114#define CFG_SYS_NAND_U_BOOT_START CFG_SYS_NAND_U_BOOT_DST
115#define CFG_SYS_NAND_ECCPOS { \
Fabien Parent7f040722016-12-05 19:15:21 +0100116 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
117 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
118 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
119 54, 55, 56, 57, 58, 59, 60, 61, 62, 63 }
Tom Rinib4213492022-11-12 17:36:51 -0500120#define CFG_SYS_NAND_ECCSIZE 512
121#define CFG_SYS_NAND_ECCBYTES 10
Peter Howard9ed4f702015-03-23 09:19:56 +1100122#endif
123
Peter Howard9ed4f702015-03-23 09:19:56 +1100124/*
Peter Howard9ed4f702015-03-23 09:19:56 +1100125 * U-Boot general configuration
126 */
Peter Howard9ed4f702015-03-23 09:19:56 +1100127
128/*
129 * Linux Information
130 */
131#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
Sekhar Norib261dce2017-04-06 14:52:55 +0530132
133#define DEFAULT_LINUX_BOOT_ENV \
134 "loadaddr=0xc0700000\0" \
Fabien Parent6b70b132016-11-29 17:15:03 +0100135 "fdtaddr=0xc0600000\0" \
Sekhar Norib261dce2017-04-06 14:52:55 +0530136 "scriptaddr=0xc0600000\0"
137
Sekhar Nori5bf93902017-04-06 14:52:57 +0530138#include <environment/ti/mmc.h>
139
Tom Rinic9edebe2022-12-04 10:03:50 -0500140#define CFG_EXTRA_ENV_SETTINGS \
Sekhar Norib261dce2017-04-06 14:52:55 +0530141 DEFAULT_LINUX_BOOT_ENV \
Sekhar Nori5bf93902017-04-06 14:52:57 +0530142 DEFAULT_MMC_TI_ARGS \
143 "bootpart=0:2\0" \
144 "bootdir=/boot\0" \
145 "bootfile=zImage\0" \
Fabien Parent6b70b132016-11-29 17:15:03 +0100146 "fdtfile=da850-lcdk.dtb\0" \
Sekhar Nori5bf93902017-04-06 14:52:57 +0530147 "boot_fdt=yes\0" \
148 "boot_fit=0\0" \
149 "console=ttyS2,115200n8\0"
Peter Howard9ed4f702015-03-23 09:19:56 +1100150
Peter Howard9ed4f702015-03-23 09:19:56 +1100151/* SD/MMC */
Peter Howard9ed4f702015-03-23 09:19:56 +1100152
Peter Howard9ed4f702015-03-23 09:19:56 +1100153/* defines for SPL */
Peter Howard9ed4f702015-03-23 09:19:56 +1100154
155/* additions for new relocation code, must added to all boards */
Tom Rinibb4dd962022-11-16 13:10:37 -0500156#define CFG_SYS_SDRAM_BASE 0xc0000000
Simon Glassce3574f2017-05-17 08:23:09 -0600157
158#include <asm/arch/hardware.h>
159
Peter Howard9ed4f702015-03-23 09:19:56 +1100160#endif /* __CONFIG_H */