| commit | d53dbf3f5563cf57542d225fa0d674fdf8dfdb86 | [log] [tgz] |
|---|---|---|
| author | Sekhar Nori <nsekhar@ti.com> | Fri Jun 02 18:07:12 2017 +0530 |
| committer | Tom Rini <trini@konsulko.com> | Fri Jun 09 11:24:01 2017 -0400 |
| tree | 1d8b00fb66eb811ec767484f7e11ee7bb242b6f8 | |
| parent | b9a9afdbf360f2128901a58b331c3560350e9d77 [diff] [blame] |
davinci: omapl138_lcdk: fix tXSNR DDR2 timing value As per the datasheet[1] available for DDR2 part on board the OMAP-L138 LCDK, the tXSNR (exit self refresh to a non-read command) is 137.5 ns. This corresponds to a value of 20 to be written to T_XSNR register field of OMAP-L138's DDR configuration. The DDR2 is at 150 MHz. Fix this. The correct value also appears on the initialization scripts (called CCS GEL files) available on TI's wiki pages[2] [1] http://www.samsung.com/global/business/semiconductor/file/product/ds_k4t1gxx4qf_rev12-0.pdf [2] http://processors.wiki.ti.com/index.php/L138/C6748_Development_Kit_(LCDK)#CCS_XML_.26_GEL_Files Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h index 0a8096c..5f11895 100644 --- a/include/configs/omapl138_lcdk.h +++ b/include/configs/omapl138_lcdk.h
@@ -110,7 +110,7 @@ (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \ (2 << DV_DDR_SDTMR2_XP_SHIFT) | \ (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \ - (10 << DV_DDR_SDTMR2_XSNR_SHIFT) | \ + (20 << DV_DDR_SDTMR2_XSNR_SHIFT) | \ (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \ (1 << DV_DDR_SDTMR2_RTP_SHIFT) | \ (2 << DV_DDR_SDTMR2_CKE_SHIFT))