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Haavard Skinnemoen2f5bfb72008-05-16 11:10:33 +02001/*
2 * SPI flash internal definitions
3 *
4 * Copyright (C) 2008 Atmel Corporation
Jagannadha Sutradharudu Teki25dc86a2013-10-02 19:38:49 +05305 * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.
6 *
Jagannadha Sutradharudu Tekid1452702013-10-10 22:32:55 +05307 * SPDX-License-Identifier: GPL-2.0+
Haavard Skinnemoen2f5bfb72008-05-16 11:10:33 +02008 */
9
Jagannadha Sutradharudu Teki84fb8632013-10-10 22:14:09 +053010#ifndef _SF_INTERNAL_H_
11#define _SF_INTERNAL_H_
Haavard Skinnemoen2f5bfb72008-05-16 11:10:33 +020012
Jagannadha Sutradharudu Teki25dc86a2013-10-02 19:38:49 +053013#define SPI_FLASH_16MB_BOUN 0x1000000
Haavard Skinnemoen2f5bfb72008-05-16 11:10:33 +020014
Jagannadha Sutradharudu Teki25dc86a2013-10-02 19:38:49 +053015/* SECT flags */
Jagannadha Sutradharudu Tekif3b2dd82013-10-07 19:34:56 +053016#define SECT_4K (1 << 1)
Jagannadha Sutradharudu Teki25dc86a2013-10-02 19:38:49 +053017#define SECT_32K (1 << 2)
18#define E_FSR (1 << 3)
Haavard Skinnemoen2f5bfb72008-05-16 11:10:33 +020019
Jagannadha Sutradharudu Teki25dc86a2013-10-02 19:38:49 +053020/* Erase commands */
21#define CMD_ERASE_4K 0x20
22#define CMD_ERASE_32K 0x52
23#define CMD_ERASE_CHIP 0xc7
24#define CMD_ERASE_64K 0xd8
25
26/* Write commands */
Mike Frysinger1302bec2012-01-28 16:26:03 -080027#define CMD_WRITE_STATUS 0x01
Mike Frysinger301e9b42011-04-25 06:58:29 +000028#define CMD_PAGE_PROGRAM 0x02
Mike Frysinger79112112011-04-25 06:59:53 +000029#define CMD_WRITE_DISABLE 0x04
Mike Frysinger37e13bc2011-01-10 02:20:12 -050030#define CMD_READ_STATUS 0x05
Mike Frysingerb375ad92013-12-03 16:43:27 -070031#define CMD_READ_STATUS1 0x35
Mike Frysinger53421bb2011-01-10 02:20:13 -050032#define CMD_WRITE_ENABLE 0x06
Jagannadha Sutradharudu Tekif3b2dd82013-10-07 19:34:56 +053033#define CMD_READ_CONFIG 0x35
34#define CMD_FLAG_STATUS 0x70
Mike Frysinger37e13bc2011-01-10 02:20:12 -050035
Jagannadha Sutradharudu Teki25dc86a2013-10-02 19:38:49 +053036/* Read commands */
37#define CMD_READ_ARRAY_SLOW 0x03
38#define CMD_READ_ARRAY_FAST 0x0b
39#define CMD_READ_ID 0x9f
Jagannadha Sutradharudu Teki29d70c92013-06-19 15:37:09 +053040
Jagannadha Sutradharudu Tekice08a712013-06-19 15:31:23 +053041/* Bank addr access commands */
Jagannadha Sutradharudu Teki25dc86a2013-10-02 19:38:49 +053042#ifdef CONFIG_SPI_FLASH_BAR
Jagannadha Sutradharudu Tekic6d173d2013-06-19 15:33:58 +053043# define CMD_BANKADDR_BRWR 0x17
44# define CMD_BANKADDR_BRRD 0x16
45# define CMD_EXTNADDR_WREAR 0xC5
46# define CMD_EXTNADDR_RDEAR 0xC8
47#endif
Jagannadha Sutradharudu Tekice08a712013-06-19 15:31:23 +053048
Mike Frysinger37e13bc2011-01-10 02:20:12 -050049/* Common status */
50#define STATUS_WIP 0x01
Jagannadha Sutradharudu Teki750f3ac2013-06-21 15:56:30 +053051#define STATUS_PEC 0x80
Mike Frysinger37e13bc2011-01-10 02:20:12 -050052
Jagannadha Sutradharudu Teki25dc86a2013-10-02 19:38:49 +053053/* Flash timeout values */
54#define SPI_FLASH_PROG_TIMEOUT (2 * CONFIG_SYS_HZ)
55#define SPI_FLASH_PAGE_ERASE_TIMEOUT (5 * CONFIG_SYS_HZ)
56#define SPI_FLASH_SECTOR_ERASE_TIMEOUT (10 * CONFIG_SYS_HZ)
57
58/* SST specific */
59#ifdef CONFIG_SPI_FLASH_SST
60# define SST_WP 0x01 /* Supports AAI word program */
Jagannadha Sutradharudu Tekif3b2dd82013-10-07 19:34:56 +053061# define CMD_SST_BP 0x02 /* Byte Program */
Jagannadha Sutradharudu Teki25dc86a2013-10-02 19:38:49 +053062# define CMD_SST_AAI_WP 0xAD /* Auto Address Incr Word Program */
63
64int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len,
65 const void *buf);
66#endif
67
Haavard Skinnemoen2f5bfb72008-05-16 11:10:33 +020068/* Send a single-byte command to the device and read the response */
69int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len);
70
71/*
72 * Send a multi-byte command to the device and read the response. Used
73 * for flash array reads, etc.
74 */
75int spi_flash_cmd_read(struct spi_slave *spi, const u8 *cmd,
76 size_t cmd_len, void *data, size_t data_len);
77
78/*
79 * Send a multi-byte command to the device followed by (optional)
80 * data. Used for programming the flash array, etc.
81 */
82int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len,
83 const void *data, size_t data_len);
84
Mike Frysinger301e9b42011-04-25 06:58:29 +000085
Jagannadha Sutradharudu Teki25dc86a2013-10-02 19:38:49 +053086/* Flash erase(sectors) operation, support all possible erase commands */
87int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len);
Jagannadha Sutradharudu Teki08032422013-10-02 19:34:53 +053088
Jagannadha Sutradharudu Teki25dc86a2013-10-02 19:38:49 +053089/* Program the status register */
90int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr);
91
92/* Set quad enbale bit */
93int spi_flash_set_qeb(struct spi_flash *flash);
94
95/* Enable writing on the SPI flash */
Mike Frysinger8ec7f4c2011-04-23 23:05:55 +000096static inline int spi_flash_cmd_write_enable(struct spi_flash *flash)
97{
98 return spi_flash_cmd(flash->spi, CMD_WRITE_ENABLE, NULL, 0);
99}
100
Jagannadha Sutradharudu Teki25dc86a2013-10-02 19:38:49 +0530101/* Disable writing on the SPI flash */
Mike Frysinger79112112011-04-25 06:59:53 +0000102static inline int spi_flash_cmd_write_disable(struct spi_flash *flash)
103{
104 return spi_flash_cmd(flash->spi, CMD_WRITE_DISABLE, NULL, 0);
105}
106
107/*
Jagannadha Sutradharudu Teki25dc86a2013-10-02 19:38:49 +0530108 * Send the read status command to the device and wait for the wip
109 * (write-in-progress) bit to clear itself.
Haavard Skinnemoen2f5bfb72008-05-16 11:10:33 +0200110 */
Jagannadha Sutradharudu Teki25dc86a2013-10-02 19:38:49 +0530111int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout);
112
Jagannadha Sutradharudu Tekidc78b852013-06-21 19:19:00 +0530113/*
114 * Used for spi_flash write operation
115 * - SPI claim
116 * - spi_flash_cmd_write_enable
117 * - spi_flash_cmd_write
118 * - spi_flash_cmd_wait_ready
119 * - SPI release
120 */
121int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd,
122 size_t cmd_len, const void *buf, size_t buf_len);
Mike Frysinger37e13bc2011-01-10 02:20:12 -0500123
124/*
Jagannadha Sutradharudu Teki25dc86a2013-10-02 19:38:49 +0530125 * Flash write operation, support all possible write commands.
126 * Write the requested data out breaking it up into multiple write
127 * commands as needed per the write size.
Mike Frysinger37e13bc2011-01-10 02:20:12 -0500128 */
Jagannadha Sutradharudu Teki25dc86a2013-10-02 19:38:49 +0530129int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
130 size_t len, const void *buf);
131
132/*
133 * Same as spi_flash_cmd_read() except it also claims/releases the SPI
134 * bus. Used as common part of the ->read() operation.
135 */
136int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd,
137 size_t cmd_len, void *data, size_t data_len);
138
139/* Flash read operation, support all possible read commands */
140int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
141 size_t len, void *data);
Mike Frysinger37e13bc2011-01-10 02:20:12 -0500142
Jagannadha Sutradharudu Teki84fb8632013-10-10 22:14:09 +0530143#endif /* _SF_INTERNAL_H_ */