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Haavard Skinnemoen2f5bfb72008-05-16 11:10:33 +02001/*
2 * SPI flash internal definitions
3 *
4 * Copyright (C) 2008 Atmel Corporation
Jagannadha Sutradharudu Teki25dc86a2013-10-02 19:38:49 +05305 * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.
6 *
7 * Licensed under the GPL-2 or later.
Haavard Skinnemoen2f5bfb72008-05-16 11:10:33 +02008 */
9
Jagannadha Sutradharudu Teki84fb8632013-10-10 22:14:09 +053010#ifndef _SF_INTERNAL_H_
11#define _SF_INTERNAL_H_
Haavard Skinnemoen2f5bfb72008-05-16 11:10:33 +020012
Jagannadha Sutradharudu Teki25dc86a2013-10-02 19:38:49 +053013#define SPI_FLASH_16MB_BOUN 0x1000000
Haavard Skinnemoen2f5bfb72008-05-16 11:10:33 +020014
Jagannadha Sutradharudu Teki25dc86a2013-10-02 19:38:49 +053015/* SECT flags */
Jagannadha Sutradharudu Tekif3b2dd82013-10-07 19:34:56 +053016#define SECT_4K (1 << 1)
Jagannadha Sutradharudu Teki25dc86a2013-10-02 19:38:49 +053017#define SECT_32K (1 << 2)
18#define E_FSR (1 << 3)
Haavard Skinnemoen2f5bfb72008-05-16 11:10:33 +020019
Jagannadha Sutradharudu Teki25dc86a2013-10-02 19:38:49 +053020/* Erase commands */
21#define CMD_ERASE_4K 0x20
22#define CMD_ERASE_32K 0x52
23#define CMD_ERASE_CHIP 0xc7
24#define CMD_ERASE_64K 0xd8
25
26/* Write commands */
Mike Frysinger1302bec2012-01-28 16:26:03 -080027#define CMD_WRITE_STATUS 0x01
Mike Frysinger301e9b42011-04-25 06:58:29 +000028#define CMD_PAGE_PROGRAM 0x02
Mike Frysinger79112112011-04-25 06:59:53 +000029#define CMD_WRITE_DISABLE 0x04
Mike Frysinger37e13bc2011-01-10 02:20:12 -050030#define CMD_READ_STATUS 0x05
Mike Frysinger53421bb2011-01-10 02:20:13 -050031#define CMD_WRITE_ENABLE 0x06
Jagannadha Sutradharudu Tekif3b2dd82013-10-07 19:34:56 +053032#define CMD_READ_CONFIG 0x35
33#define CMD_FLAG_STATUS 0x70
Mike Frysinger37e13bc2011-01-10 02:20:12 -050034
Jagannadha Sutradharudu Teki25dc86a2013-10-02 19:38:49 +053035/* Read commands */
36#define CMD_READ_ARRAY_SLOW 0x03
37#define CMD_READ_ARRAY_FAST 0x0b
38#define CMD_READ_ID 0x9f
Jagannadha Sutradharudu Teki29d70c92013-06-19 15:37:09 +053039
Jagannadha Sutradharudu Tekice08a712013-06-19 15:31:23 +053040/* Bank addr access commands */
Jagannadha Sutradharudu Teki25dc86a2013-10-02 19:38:49 +053041#ifdef CONFIG_SPI_FLASH_BAR
Jagannadha Sutradharudu Tekic6d173d2013-06-19 15:33:58 +053042# define CMD_BANKADDR_BRWR 0x17
43# define CMD_BANKADDR_BRRD 0x16
44# define CMD_EXTNADDR_WREAR 0xC5
45# define CMD_EXTNADDR_RDEAR 0xC8
46#endif
Jagannadha Sutradharudu Tekice08a712013-06-19 15:31:23 +053047
Mike Frysinger37e13bc2011-01-10 02:20:12 -050048/* Common status */
49#define STATUS_WIP 0x01
Jagannadha Sutradharudu Teki750f3ac2013-06-21 15:56:30 +053050#define STATUS_PEC 0x80
Mike Frysinger37e13bc2011-01-10 02:20:12 -050051
Jagannadha Sutradharudu Teki25dc86a2013-10-02 19:38:49 +053052/* Flash timeout values */
53#define SPI_FLASH_PROG_TIMEOUT (2 * CONFIG_SYS_HZ)
54#define SPI_FLASH_PAGE_ERASE_TIMEOUT (5 * CONFIG_SYS_HZ)
55#define SPI_FLASH_SECTOR_ERASE_TIMEOUT (10 * CONFIG_SYS_HZ)
56
57/* SST specific */
58#ifdef CONFIG_SPI_FLASH_SST
59# define SST_WP 0x01 /* Supports AAI word program */
Jagannadha Sutradharudu Tekif3b2dd82013-10-07 19:34:56 +053060# define CMD_SST_BP 0x02 /* Byte Program */
Jagannadha Sutradharudu Teki25dc86a2013-10-02 19:38:49 +053061# define CMD_SST_AAI_WP 0xAD /* Auto Address Incr Word Program */
62
63int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len,
64 const void *buf);
65#endif
66
Haavard Skinnemoen2f5bfb72008-05-16 11:10:33 +020067/* Send a single-byte command to the device and read the response */
68int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len);
69
70/*
71 * Send a multi-byte command to the device and read the response. Used
72 * for flash array reads, etc.
73 */
74int spi_flash_cmd_read(struct spi_slave *spi, const u8 *cmd,
75 size_t cmd_len, void *data, size_t data_len);
76
77/*
78 * Send a multi-byte command to the device followed by (optional)
79 * data. Used for programming the flash array, etc.
80 */
81int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len,
82 const void *data, size_t data_len);
83
Mike Frysinger301e9b42011-04-25 06:58:29 +000084
Jagannadha Sutradharudu Teki25dc86a2013-10-02 19:38:49 +053085/* Flash erase(sectors) operation, support all possible erase commands */
86int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len);
Jagannadha Sutradharudu Teki08032422013-10-02 19:34:53 +053087
Jagannadha Sutradharudu Teki25dc86a2013-10-02 19:38:49 +053088/* Program the status register */
89int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr);
90
91/* Set quad enbale bit */
92int spi_flash_set_qeb(struct spi_flash *flash);
93
94/* Enable writing on the SPI flash */
Mike Frysinger8ec7f4c2011-04-23 23:05:55 +000095static inline int spi_flash_cmd_write_enable(struct spi_flash *flash)
96{
97 return spi_flash_cmd(flash->spi, CMD_WRITE_ENABLE, NULL, 0);
98}
99
Jagannadha Sutradharudu Teki25dc86a2013-10-02 19:38:49 +0530100/* Disable writing on the SPI flash */
Mike Frysinger79112112011-04-25 06:59:53 +0000101static inline int spi_flash_cmd_write_disable(struct spi_flash *flash)
102{
103 return spi_flash_cmd(flash->spi, CMD_WRITE_DISABLE, NULL, 0);
104}
105
106/*
Jagannadha Sutradharudu Teki25dc86a2013-10-02 19:38:49 +0530107 * Send the read status command to the device and wait for the wip
108 * (write-in-progress) bit to clear itself.
Haavard Skinnemoen2f5bfb72008-05-16 11:10:33 +0200109 */
Jagannadha Sutradharudu Teki25dc86a2013-10-02 19:38:49 +0530110int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout);
111
Jagannadha Sutradharudu Tekidc78b852013-06-21 19:19:00 +0530112/*
113 * Used for spi_flash write operation
114 * - SPI claim
115 * - spi_flash_cmd_write_enable
116 * - spi_flash_cmd_write
117 * - spi_flash_cmd_wait_ready
118 * - SPI release
119 */
120int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd,
121 size_t cmd_len, const void *buf, size_t buf_len);
Mike Frysinger37e13bc2011-01-10 02:20:12 -0500122
123/*
Jagannadha Sutradharudu Teki25dc86a2013-10-02 19:38:49 +0530124 * Flash write operation, support all possible write commands.
125 * Write the requested data out breaking it up into multiple write
126 * commands as needed per the write size.
Mike Frysinger37e13bc2011-01-10 02:20:12 -0500127 */
Jagannadha Sutradharudu Teki25dc86a2013-10-02 19:38:49 +0530128int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
129 size_t len, const void *buf);
130
131/*
132 * Same as spi_flash_cmd_read() except it also claims/releases the SPI
133 * bus. Used as common part of the ->read() operation.
134 */
135int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd,
136 size_t cmd_len, void *data, size_t data_len);
137
138/* Flash read operation, support all possible read commands */
139int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
140 size_t len, void *data);
Mike Frysinger37e13bc2011-01-10 02:20:12 -0500141
Jagannadha Sutradharudu Teki84fb8632013-10-10 22:14:09 +0530142#endif /* _SF_INTERNAL_H_ */