arch/arm/dts/rk3588-rock-5b-u-boot.dtsi

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2023 Collabora Ltd.
 */

#include "rk3588-u-boot.dtsi"
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>

/ {
	aliases {
		mmc1 = &sdmmc;
		spi0 = &sfc;
	};

	chosen {
		u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci;
	};

	vcc5v0_host: vcc5v0-host-regulator {
		compatible = "regulator-fixed";
		regulator-name = "vcc5v0_host";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		enable-active-high;
		gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&vcc5v0_host_en>;
		vin-supply = <&vcc5v0_sys>;
	};
};

&combphy0_ps {
	status = "okay";
};

&emmc_bus8 {
	bootph-all;
};

&emmc_clk {
	bootph-all;
};

&emmc_cmd {
	bootph-all;
};

&emmc_data_strobe {
	bootph-all;
};

&emmc_rstnout {
	bootph-all;
};

&fspim2_pins {
	bootph-all;
};

&pcie2x1l2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pcie2x1l2_pins &pcie_reset_h>;
	reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>;
	status = "okay";
};

&pinctrl {
	bootph-all;

	pcie {
		pcie_reset_h: pcie-reset-h {
			rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
		};

		pcie2x1l2_pins: pcie2x1l2-pins {
			rockchip,pins = <3 RK_PC7 4 &pcfg_pull_none>,
					<3 RK_PD0 4 &pcfg_pull_none>;
		};
	};

	usb {
		vcc5v0_host_en: vcc5v0-host-en {
			rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
		};
	};
};

&pcfg_pull_none {
	bootph-all;
};

&pcfg_pull_up_drv_level_2 {
	bootph-all;
};

&pcfg_pull_up {
	bootph-all;
};

&sdmmc {
	bus-width = <4>;
	status = "okay";
};

&sdmmc_bus4 {
	bootph-all;
};

&sdmmc_clk {
	bootph-all;
};

&sdmmc_cmd {
	bootph-all;
};

&sdmmc_det {
	bootph-all;
};

&sdhci {
	cap-mmc-highspeed;
	mmc-ddr-1_8v;
	mmc-hs200-1_8v;
	pinctrl-names = "default";
	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_data_strobe &emmc_rstnout>;
};

&sfc {
	bootph-pre-ram;
	u-boot,spl-sfc-no-dma;
	pinctrl-names = "default";
	pinctrl-0 = <&fspim2_pins>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "okay";

	flash@0 {
		bootph-pre-ram;
		compatible = "jedec,spi-nor";
		reg = <0>;
		spi-max-frequency = <24000000>;
		spi-rx-bus-width = <4>;
		spi-tx-bus-width = <1>;
	};
};

&uart2m0_xfer {
	bootph-all;
};

&usb_host0_ehci {
	companion = <&usb_host0_ohci>;
	phys = <&u2phy2_host>;
	phy-names = "usb2-phy";
	status = "okay";
};

&usb_host0_ohci {
	phys = <&u2phy2_host>;
	phy-names = "usb2-phy";
	status = "okay";
};

&usb2phy2_grf {
	status = "okay";
};

&u2phy2 {
	resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>;
	reset-names = "phy", "apb";
	clock-output-names = "usb480m_phy2";
	status = "okay";
};

&u2phy2_host {
	phy-supply = <&vcc5v0_host>;
	status = "okay";
};

&usb_host1_ehci {
	companion = <&usb_host1_ohci>;
	phys = <&u2phy3_host>;
	phy-names = "usb2-phy";
	status = "okay";
};

&usb_host1_ohci {
	phys = <&u2phy3_host>;
	phy-names = "usb2-phy";
	status = "okay";
};

&usb2phy3_grf {
	status = "okay";
};

&u2phy3 {
	resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>;
	reset-names = "phy", "apb";
	clock-output-names = "usb480m_phy3";
	status = "okay";
};

&u2phy3_host {
	phy-supply = <&vcc5v0_host>;
	status = "okay";
};