Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
TENART Antoine | 7a5eb65 | 2013-07-02 12:06:00 +0200 | [diff] [blame] | 2 | /* |
| 3 | * ti816x_evm.h |
| 4 | * |
| 5 | * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com> |
| 6 | * Antoine Tenart, <atenart@adeneo-embedded.com> |
TENART Antoine | 7a5eb65 | 2013-07-02 12:06:00 +0200 | [diff] [blame] | 7 | */ |
| 8 | |
| 9 | #ifndef __CONFIG_TI816X_EVM_H |
| 10 | #define __CONFIG_TI816X_EVM_H |
| 11 | |
Tom Rini | b05ee2f | 2017-05-16 14:46:39 -0400 | [diff] [blame] | 12 | #include <configs/ti_armv7_omap.h> |
TENART Antoine | 7a5eb65 | 2013-07-02 12:06:00 +0200 | [diff] [blame] | 13 | #include <asm/arch/omap.h> |
| 14 | |
TENART Antoine | 7a5eb65 | 2013-07-02 12:06:00 +0200 | [diff] [blame] | 15 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
Tom Rini | b05ee2f | 2017-05-16 14:46:39 -0400 | [diff] [blame] | 16 | DEFAULT_LINUX_BOOT_ENV \ |
Tom Rini | 5ad8e11 | 2017-10-22 17:55:07 -0400 | [diff] [blame] | 17 | "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ |
| 18 | "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ |
TENART Antoine | 7a5eb65 | 2013-07-02 12:06:00 +0200 | [diff] [blame] | 19 | |
TENART Antoine | 7a5eb65 | 2013-07-02 12:06:00 +0200 | [diff] [blame] | 20 | /* Clock Defines */ |
| 21 | #define V_OSCK 24000000 /* Clock output from T2 */ |
| 22 | #define V_SCLK (V_OSCK >> 1) |
| 23 | |
TENART Antoine | 7a5eb65 | 2013-07-02 12:06:00 +0200 | [diff] [blame] | 24 | #define CONFIG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2048MB */ |
Tom Rini | b05ee2f | 2017-05-16 14:46:39 -0400 | [diff] [blame] | 25 | #define CONFIG_SYS_SDRAM_BASE 0x80000000 |
TENART Antoine | 7a5eb65 | 2013-07-02 12:06:00 +0200 | [diff] [blame] | 26 | |
| 27 | /** |
| 28 | * Platform/Board specific defs |
| 29 | */ |
TENART Antoine | 7a5eb65 | 2013-07-02 12:06:00 +0200 | [diff] [blame] | 30 | #define CONFIG_SYS_TIMERBASE 0x4802E000 |
TENART Antoine | 7a5eb65 | 2013-07-02 12:06:00 +0200 | [diff] [blame] | 31 | |
TENART Antoine | 7a5eb65 | 2013-07-02 12:06:00 +0200 | [diff] [blame] | 32 | /* |
| 33 | * NS16550 Configuration |
| 34 | */ |
TENART Antoine | 7a5eb65 | 2013-07-02 12:06:00 +0200 | [diff] [blame] | 35 | #define CONFIG_SYS_NS16550_SERIAL |
| 36 | #define CONFIG_SYS_NS16550_REG_SIZE (-4) |
| 37 | #define CONFIG_SYS_NS16550_CLK (48000000) |
| 38 | #define CONFIG_SYS_NS16550_COM1 0x48024000 /* Base EVM has UART2 */ |
| 39 | |
TENART Antoine | 7a5eb65 | 2013-07-02 12:06:00 +0200 | [diff] [blame] | 40 | /* allow overwriting serial config and ethaddr */ |
TENART Antoine | 7a5eb65 | 2013-07-02 12:06:00 +0200 | [diff] [blame] | 41 | |
TENART Antoine | 7a5eb65 | 2013-07-02 12:06:00 +0200 | [diff] [blame] | 42 | |
Tom Rini | 28bfc1b | 2017-05-16 14:46:37 -0400 | [diff] [blame] | 43 | /* |
| 44 | * GPMC NAND block. We support 1 device and the physical address to |
| 45 | * access CS0 at is 0x8000000. |
| 46 | */ |
| 47 | #define CONFIG_SYS_NAND_BASE 0x8000000 |
| 48 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
| 49 | |
| 50 | /* NAND: SPL related configs */ |
Tom Rini | 28bfc1b | 2017-05-16 14:46:37 -0400 | [diff] [blame] | 51 | |
| 52 | /* NAND: device related configs */ |
Tom Rini | 28bfc1b | 2017-05-16 14:46:37 -0400 | [diff] [blame] | 53 | /* NAND: driver related configs */ |
Tom Rini | 28bfc1b | 2017-05-16 14:46:37 -0400 | [diff] [blame] | 54 | #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ |
| 55 | 10, 11, 12, 13, 14, 15, 16, 17, \ |
| 56 | 18, 19, 20, 21, 22, 23, 24, 25, \ |
| 57 | 26, 27, 28, 29, 30, 31, 32, 33, \ |
| 58 | 34, 35, 36, 37, 38, 39, 40, 41, \ |
| 59 | 42, 43, 44, 45, 46, 47, 48, 49, \ |
| 60 | 50, 51, 52, 53, 54, 55, 56, 57, } |
| 61 | |
| 62 | #define CONFIG_SYS_NAND_ECCSIZE 512 |
| 63 | #define CONFIG_SYS_NAND_ECCBYTES 14 |
TENART Antoine | 7a5eb65 | 2013-07-02 12:06:00 +0200 | [diff] [blame] | 64 | |
| 65 | /* SPL */ |
| 66 | /* Defines for SPL */ |
TENART Antoine | 7a5eb65 | 2013-07-02 12:06:00 +0200 | [diff] [blame] | 67 | |
TENART Antoine | 7a5eb65 | 2013-07-02 12:06:00 +0200 | [diff] [blame] | 68 | #endif |