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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
York Sun7b08d212014-06-23 15:15:56 -07002/*
Priyanka Jain7d05b992017-04-28 10:41:35 +05303 * Copyright 2017 NXP
York Sun7b08d212014-06-23 15:15:56 -07004 * Copyright (C) 2014 Freescale Semiconductor
York Sun7b08d212014-06-23 15:15:56 -07005 */
6
7#ifndef __LS2_COMMON_H
8#define __LS2_COMMON_H
9
Bharat Bhushan70239992017-03-22 12:06:25 +053010#include <asm/arch/stream_id_lsch3.h>
Mingkai Hu0e58b512015-10-26 19:47:50 +080011#include <asm/arch/config.h>
Minghuan Lian0e3a2b92015-03-20 19:28:16 -070012
Mingkai Hu0e58b512015-10-26 19:47:50 +080013/* Link Definitions */
Mingkai Hu0e58b512015-10-26 19:47:50 +080014
Bhupesh Sharma25b8efe2015-03-19 09:20:43 -070015/* We need architecture specific misc initializations */
Bhupesh Sharma25b8efe2015-03-19 09:20:43 -070016
York Sun7b08d212014-06-23 15:15:56 -070017/* Link Definitions */
York Sun7b08d212014-06-23 15:15:56 -070018
York Sun7b08d212014-06-23 15:15:56 -070019#ifndef CONFIG_SYS_FSL_DDR4
York Sun7b08d212014-06-23 15:15:56 -070020#define CONFIG_SYS_DDR_RAW_TIMING
21#endif
York Sun7b08d212014-06-23 15:15:56 -070022
23#define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */
24
Mingkai Hu0e58b512015-10-26 19:47:50 +080025#define CONFIG_VERY_BIG_RAM
York Sun7b08d212014-06-23 15:15:56 -070026#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
27#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
28#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
29#define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
York Sunc7a0e302014-08-13 10:21:05 -070030#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2
31
York Sun290a83a2014-09-08 12:20:01 -070032/*
33 * SMP Definitinos
34 */
Michael Wallef056e0f2020-06-01 21:53:26 +020035#define CPU_RELEASE_ADDR secondary_boot_addr
York Sun290a83a2014-09-08 12:20:01 -070036
York Sunc7a0e302014-08-13 10:21:05 -070037#define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
York Sun7b08d212014-06-23 15:15:56 -070038
York Sun77a10972015-03-20 19:28:08 -070039/*
40 * This is not an accurate number. It is used in start.S. The frequency
41 * will be udpated later when get_bus_freq(0) is available.
42 */
York Sun7b08d212014-06-23 15:15:56 -070043
Biwen Li66c0e362021-02-05 19:01:59 +080044/* GPIO */
Biwen Li66c0e362021-02-05 19:01:59 +080045
York Sun7b08d212014-06-23 15:15:56 -070046/* I2C */
York Sun7b08d212014-06-23 15:15:56 -070047
48/* Serial Port */
York Sun7b08d212014-06-23 15:15:56 -070049#define CONFIG_SYS_NS16550_SERIAL
50#define CONFIG_SYS_NS16550_REG_SIZE 1
Hou Zhiqiang3a76dd52017-01-10 16:44:16 +080051#define CONFIG_SYS_NS16550_CLK (get_serial_clock())
York Sun7b08d212014-06-23 15:15:56 -070052
York Sun7b08d212014-06-23 15:15:56 -070053/*
York Sun03017032015-03-20 19:28:23 -070054 * During booting, IFC is mapped at the region of 0x30000000.
55 * But this region is limited to 256MB. To accommodate NOR, promjet
56 * and FPGA. This region is divided as below:
57 * 0x30000000 - 0x37ffffff : 128MB : NOR flash
58 * 0x38000000 - 0x3BFFFFFF : 64MB : Promjet
59 * 0x3C000000 - 0x40000000 : 64MB : FPGA etc
60 *
61 * To accommodate bigger NOR flash and other devices, we will map IFC
62 * chip selects to as below:
63 * 0x5_1000_0000..0x5_1fff_ffff Memory Hole
64 * 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB)
65 * 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB
66 * 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet)
67 * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet)
68 *
69 * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation.
York Sun7b08d212014-06-23 15:15:56 -070070 * CONFIG_SYS_FLASH_BASE has the final address (core view)
71 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
72 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
73 * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting
74 */
York Sun03017032015-03-20 19:28:23 -070075
York Sun7b08d212014-06-23 15:15:56 -070076#define CONFIG_SYS_FLASH_BASE 0x580000000ULL
77#define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000
78#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
79
York Sun03017032015-03-20 19:28:23 -070080#define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000
81#define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000
82
York Sun03017032015-03-20 19:28:23 -070083#ifndef __ASSEMBLY__
84unsigned long long get_qixis_addr(void);
85#endif
86#define QIXIS_BASE get_qixis_addr()
87#define QIXIS_BASE_PHYS 0x20000000
88#define QIXIS_BASE_PHYS_EARLY 0xC000000
Yangbo Lud0e295d2015-03-20 19:28:31 -070089#define QIXIS_STAT_PRES1 0xb
90#define QIXIS_SDID_MASK 0x07
91#define QIXIS_ESDHC_NO_ADAPTER 0x7
York Sun03017032015-03-20 19:28:23 -070092
93#define CONFIG_SYS_NAND_BASE 0x530000000ULL
94#define CONFIG_SYS_NAND_BASE_PHYS 0x30000000
Prabhakar Kushwaha962b2de2014-07-16 09:21:12 +053095
York Sun7b08d212014-06-23 15:15:56 -070096/* MC firmware */
York Sun7b08d212014-06-23 15:15:56 -070097/* TODO Actual DPL max length needs to be confirmed with the MC FW team */
J. German Riveraf4fed4b2015-03-20 19:28:18 -070098#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
99#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
100#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
101#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
York Suncbe8e1c2016-04-04 11:41:26 -0700102/* For LS2085A */
J. German Riverac3b505f2015-07-02 11:28:58 +0530103#define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000
104#define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000
York Sun7b08d212014-06-23 15:15:56 -0700105
Prabhakar Kushwaha853a9012015-06-02 10:55:52 +0530106/*
107 * Carve out a DDR region which will not be used by u-boot/Linux
108 *
109 * It will be used by MC and Debug Server. The MC region must be
110 * 512MB aligned, so the min size to hide is 512MB.
111 */
York Sune45e13e2016-08-03 12:33:00 -0700112#ifdef CONFIG_FSL_MC_ENET
Meenakshi Aggarwal67f195c2019-02-27 14:41:02 +0530113#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (128UL * 1024 * 1024)
York Sun7b08d212014-06-23 15:15:56 -0700114#endif
115
York Sun7b08d212014-06-23 15:15:56 -0700116/* Miscellaneous configurable options */
York Sun7b08d212014-06-23 15:15:56 -0700117
118/* Physical Memory Map */
119/* fixme: these need to be checked against the board */
York Sun7b08d212014-06-23 15:15:56 -0700120
York Sun7b08d212014-06-23 15:15:56 -0700121#define CONFIG_HWCONFIG
122#define HWCONFIG_BUFFER_SIZE 128
123
York Sun7b08d212014-06-23 15:15:56 -0700124/* Initial environment variables */
125#define CONFIG_EXTRA_ENV_SETTINGS \
126 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
127 "loadaddr=0x80100000\0" \
128 "kernel_addr=0x100000\0" \
129 "ramdisk_addr=0x800000\0" \
130 "ramdisk_size=0x2000000\0" \
Prabhakar Kushwaha23931692015-03-20 19:28:06 -0700131 "fdt_high=0xa0000000\0" \
York Sun7b08d212014-06-23 15:15:56 -0700132 "initrd_high=0xffffffffffffffff\0" \
Santan Kumar0f0173d2017-04-28 12:47:24 +0530133 "kernel_start=0x581000000\0" \
Stuart Yoderd4792d82015-01-06 13:18:57 -0800134 "kernel_load=0xa0000000\0" \
Prabhakar Kushwaha2c0a13d2015-07-01 16:28:22 +0530135 "kernel_size=0x2800000\0" \
Prabhakar Kushwahaae193f92016-02-03 17:03:51 +0530136 "console=ttyAMA0,38400n8\0" \
Santan Kumar0f0173d2017-04-28 12:47:24 +0530137 "mcinitcmd=fsl_mc start mc 0x580a00000" \
138 " 0x580e00000 \0"
York Sun7b08d212014-06-23 15:15:56 -0700139
Santan Kumar99136482017-05-05 15:42:28 +0530140#ifdef CONFIG_NAND_BOOT
Scott Wood8e728cd2015-03-24 13:25:02 -0700141#define CONFIG_SYS_NAND_U_BOOT_DST 0x80400000
142#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
Santan Kumar99136482017-05-05 15:42:28 +0530143#endif
York Sunfb383062017-12-18 08:24:55 -0800144#define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
Scott Wood8e728cd2015-03-24 13:25:02 -0700145
Bhupesh Sharma37fbf612015-05-28 14:54:02 +0530146#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
147
Simon Glass89e0a3a2017-05-17 08:23:10 -0600148#include <asm/arch/soc.h>
149
York Sun7b08d212014-06-23 15:15:56 -0700150#endif /* __LS2_COMMON_H */