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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Mingkai Hud2396512016-09-07 18:47:28 +08002/*
3 * Copyright 2016 Freescale Semiconductor
Yangbo Lubb32e682021-06-03 10:51:19 +08004 * Copyright 2019-2021 NXP
Mingkai Hud2396512016-09-07 18:47:28 +08005 */
6
7#ifndef __LS1046A_COMMON_H
8#define __LS1046A_COMMON_H
9
Sumit Gargc064fc72017-03-30 09:53:13 +053010/* SPL build */
11#ifdef CONFIG_SPL_BUILD
12#define SPL_NO_QBMAN
13#define SPL_NO_FMAN
14#define SPL_NO_ENV
15#define SPL_NO_MISC
16#define SPL_NO_QSPI
17#define SPL_NO_USB
18#define SPL_NO_SATA
19#endif
York Sun3e512d82018-06-26 14:48:29 -070020#if defined(CONFIG_SPL_BUILD) && \
21 (defined(CONFIG_NAND_BOOT) || defined(CONFIG_QSPI_BOOT))
Sumit Gargc064fc72017-03-30 09:53:13 +053022#define SPL_NO_MMC
23#endif
York Sunc5c8e1e2018-06-08 16:37:27 -070024#if defined(CONFIG_SPL_BUILD) && \
York Sunc5c8e1e2018-06-08 16:37:27 -070025 !defined(CONFIG_SPL_FSL_LS_PPA)
Sumit Gargc064fc72017-03-30 09:53:13 +053026#define SPL_NO_IFC
27#endif
28
Mingkai Hud2396512016-09-07 18:47:28 +080029#include <asm/arch/config.h>
Bharat Bhushanc882dd72017-03-22 12:06:28 +053030#include <asm/arch/stream_id_lsch2.h>
Mingkai Hud2396512016-09-07 18:47:28 +080031
32/* Link Definitions */
Mingkai Hud2396512016-09-07 18:47:28 +080033
Mingkai Hud2396512016-09-07 18:47:28 +080034#define CONFIG_VERY_BIG_RAM
35#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
36#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
37#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
38#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
39
Michael Wallef056e0f2020-06-01 21:53:26 +020040#define CPU_RELEASE_ADDR secondary_boot_addr
Mingkai Hud2396512016-09-07 18:47:28 +080041
Mingkai Hud2396512016-09-07 18:47:28 +080042/* Serial Port */
Mingkai Hud2396512016-09-07 18:47:28 +080043#define CONFIG_SYS_NS16550_SERIAL
44#define CONFIG_SYS_NS16550_REG_SIZE 1
Hou Zhiqiang3f91cda2017-01-10 16:44:15 +080045#define CONFIG_SYS_NS16550_CLK (get_serial_clock())
Mingkai Hud2396512016-09-07 18:47:28 +080046
Mingkai Hud2396512016-09-07 18:47:28 +080047/* SD boot SPL */
48#ifdef CONFIG_SD_BOOT
Udit Agarwal22ec2382019-11-07 16:11:32 +000049#ifdef CONFIG_NXP_ESBC
Ruchika Gupta0009c8f2017-04-17 18:07:19 +053050#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
51/*
52 * HDR would be appended at end of image and copied to DDR along
53 * with U-Boot image. Here u-boot max. size is 512K. So if binary
54 * size increases then increase this size in case of secure boot as
55 * it uses raw u-boot image instead of fit image.
56 */
57#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
58#else
59#define CONFIG_SYS_MONITOR_LEN 0x100000
Udit Agarwal22ec2382019-11-07 16:11:32 +000060#endif /* ifdef CONFIG_NXP_ESBC */
Mingkai Hud2396512016-09-07 18:47:28 +080061#endif
62
York Sun3e512d82018-06-26 14:48:29 -070063#if defined(CONFIG_QSPI_BOOT) && defined(CONFIG_SPL)
York Sun3e512d82018-06-26 14:48:29 -070064#define CONFIG_SYS_MONITOR_LEN 0x100000
York Sun3e512d82018-06-26 14:48:29 -070065#endif
66
Shaohui Xie085ac1c2016-09-07 17:56:14 +080067/* NAND SPL */
68#ifdef CONFIG_NAND_BOOT
Shaohui Xie085ac1c2016-09-07 17:56:14 +080069#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
70#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
71
Shaohui Xie085ac1c2016-09-07 17:56:14 +080072#define CONFIG_SYS_MONITOR_LEN 0xa0000
73#endif
74
Biwen Li479b9bd2021-02-05 19:02:01 +080075/* GPIO */
Biwen Li479b9bd2021-02-05 19:02:01 +080076
Mingkai Hud2396512016-09-07 18:47:28 +080077/* I2C */
Mingkai Hud2396512016-09-07 18:47:28 +080078
Hou Zhiqiang105457e2017-04-14 16:49:01 +080079/* PCIe */
80#define CONFIG_PCIE1 /* PCIE controller 1 */
81#define CONFIG_PCIE2 /* PCIE controller 2 */
82#define CONFIG_PCIE3 /* PCIE controller 3 */
83
84#ifdef CONFIG_PCI
85#define CONFIG_PCI_SCAN_SHOW
Hou Zhiqiang105457e2017-04-14 16:49:01 +080086#endif
87
Yuantian Tangd24716d2018-01-03 15:53:09 +080088/* SATA */
89#ifndef SPL_NO_SATA
Yuantian Tangd24716d2018-01-03 15:53:09 +080090#define CONFIG_SYS_SATA AHCI_BASE_ADDR
Yuantian Tangd24716d2018-01-03 15:53:09 +080091#endif
92
Mingkai Hud2396512016-09-07 18:47:28 +080093/* FMan ucode */
Sumit Gargc064fc72017-03-30 09:53:13 +053094#ifndef SPL_NO_FMAN
Mingkai Hud2396512016-09-07 18:47:28 +080095#define CONFIG_SYS_DPAA_FMAN
96#ifdef CONFIG_SYS_DPAA_FMAN
97#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
Sumit Gargc064fc72017-03-30 09:53:13 +053098#endif
Mingkai Hud2396512016-09-07 18:47:28 +080099#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
100#endif
101
102/* Miscellaneous configurable options */
Mingkai Hud2396512016-09-07 18:47:28 +0800103
104#define CONFIG_HWCONFIG
105#define HWCONFIG_BUFFER_SIZE 128
106
Qianyu Gong6264ab62017-06-15 11:10:09 +0800107#ifndef CONFIG_SPL_BUILD
108#define BOOT_TARGET_DEVICES(func) \
Yuantian Tangd24716d2018-01-03 15:53:09 +0800109 func(SCSI, scsi, 0) \
Qianyu Gong6264ab62017-06-15 11:10:09 +0800110 func(MMC, mmc, 0) \
Mian Yousaf Kaukabe1721582019-01-29 16:38:37 +0100111 func(USB, usb, 0) \
112 func(DHCP, dhcp, na)
Qianyu Gong6264ab62017-06-15 11:10:09 +0800113#include <config_distro_bootcmd.h>
114#endif
115
Vabhav Sharma51641912019-06-06 12:35:28 +0000116#if defined(CONFIG_TARGET_LS1046AFRWY)
117#define LS1046A_BOOT_SRC_AND_HDR\
118 "boot_scripts=ls1046afrwy_boot.scr\0" \
119 "boot_script_hdr=hdr_ls1046afrwy_bs.out\0"
Biwen Li88dd2e82020-04-20 18:29:06 +0800120#elif defined(CONFIG_TARGET_LS1046AQDS)
121#define LS1046A_BOOT_SRC_AND_HDR\
122 "boot_scripts=ls1046aqds_boot.scr\0" \
123 "boot_script_hdr=hdr_ls1046aqds_bs.out\0"
Vabhav Sharma51641912019-06-06 12:35:28 +0000124#else
125#define LS1046A_BOOT_SRC_AND_HDR\
126 "boot_scripts=ls1046ardb_boot.scr\0" \
127 "boot_script_hdr=hdr_ls1046ardb_bs.out\0"
128#endif
Sumit Gargc064fc72017-03-30 09:53:13 +0530129#ifndef SPL_NO_MISC
Mingkai Hud2396512016-09-07 18:47:28 +0800130/* Initial environment variables */
131#define CONFIG_EXTRA_ENV_SETTINGS \
132 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
Mingkai Hud2396512016-09-07 18:47:28 +0800133 "ramdisk_addr=0x800000\0" \
134 "ramdisk_size=0x2000000\0" \
Yuantian Tange1786d32020-02-19 17:02:22 +0800135 "bootm_size=0x10000000\0" \
Biwen Li88dd2e82020-04-20 18:29:06 +0800136 "kernel_addr=0x61000000\0" \
Qianyu Gong6264ab62017-06-15 11:10:09 +0800137 "scriptaddr=0x80000000\0" \
Sumit Garg860a3bd2017-06-06 20:50:29 +0530138 "scripthdraddr=0x80080000\0" \
Qianyu Gong6264ab62017-06-15 11:10:09 +0800139 "fdtheader_addr_r=0x80100000\0" \
140 "kernelheader_addr_r=0x80200000\0" \
141 "load_addr=0xa0000000\0" \
Sumit Garg860a3bd2017-06-06 20:50:29 +0530142 "kernel_addr_r=0x81000000\0" \
Qianyu Gong6264ab62017-06-15 11:10:09 +0800143 "fdt_addr_r=0x90000000\0" \
144 "ramdisk_addr_r=0xa0000000\0" \
Mingkai Hud2396512016-09-07 18:47:28 +0800145 "kernel_start=0x1000000\0" \
Priyanka Singha83b8db2020-01-22 10:29:46 +0000146 "kernelheader_start=0x600000\0" \
Mingkai Hud2396512016-09-07 18:47:28 +0800147 "kernel_load=0xa0000000\0" \
148 "kernel_size=0x2800000\0" \
Vinitha Pillai-B572230c6e10a2017-11-22 10:38:35 +0530149 "kernelheader_size=0x40000\0" \
Shengzhou Liu47e7e032017-11-09 17:57:56 +0800150 "kernel_addr_sd=0x8000\0" \
151 "kernel_size_sd=0x14000\0" \
Priyanka Singha83b8db2020-01-22 10:29:46 +0000152 "kernelhdr_addr_sd=0x3000\0" \
Vinitha Pillai-B572230c6e10a2017-11-22 10:38:35 +0530153 "kernelhdr_size_sd=0x10\0" \
Mingkai Hud2396512016-09-07 18:47:28 +0800154 "console=ttyS0,115200\0" \
Tom Rini5ad8e112017-10-22 17:55:07 -0400155 CONFIG_MTDPARTS_DEFAULT "\0" \
Qianyu Gong6264ab62017-06-15 11:10:09 +0800156 BOOTENV \
Vabhav Sharma51641912019-06-06 12:35:28 +0000157 LS1046A_BOOT_SRC_AND_HDR \
Qianyu Gong6264ab62017-06-15 11:10:09 +0800158 "scan_dev_for_boot_part=" \
159 "part list ${devtype} ${devnum} devplist; " \
160 "env exists devplist || setenv devplist 1; " \
161 "for distro_bootpart in ${devplist}; do " \
162 "if fstype ${devtype} " \
163 "${devnum}:${distro_bootpart} " \
164 "bootfstype; then " \
165 "run scan_dev_for_boot; " \
166 "fi; " \
167 "done\0" \
Sumit Garg860a3bd2017-06-06 20:50:29 +0530168 "boot_a_script=" \
169 "load ${devtype} ${devnum}:${distro_bootpart} " \
170 "${scriptaddr} ${prefix}${script}; " \
171 "env exists secureboot && load ${devtype} " \
172 "${devnum}:${distro_bootpart} " \
Vinitha V Pillai25355ec2019-04-23 05:52:17 +0000173 "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
174 "env exists secureboot " \
175 "&& esbc_validate ${scripthdraddr};" \
Sumit Garg860a3bd2017-06-06 20:50:29 +0530176 "source ${scriptaddr}\0" \
Qianyu Gong6264ab62017-06-15 11:10:09 +0800177 "qspi_bootcmd=echo Trying load from qspi..;" \
178 "sf probe && sf read $load_addr " \
Vinitha Pillai-B572230c6e10a2017-11-22 10:38:35 +0530179 "$kernel_start $kernel_size; env exists secureboot " \
180 "&& sf read $kernelheader_addr_r $kernelheader_start " \
181 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
182 "bootm $load_addr#$board\0" \
Biwen Li88dd2e82020-04-20 18:29:06 +0800183 "nand_bootcmd=echo Trying load from nand..;" \
184 "nand info; nand read $load_addr " \
185 "$kernel_start $kernel_size; env exists secureboot " \
186 "&& nand read $kernelheader_addr_r $kernelheader_start " \
187 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
188 "bootm $load_addr#$board\0" \
189 "nor_bootcmd=echo Trying load from nor..;" \
190 "cp.b $kernel_addr $load_addr " \
191 "$kernel_size; env exists secureboot " \
192 "&& cp.b $kernelheader_addr $kernelheader_addr_r " \
193 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
194 "bootm $load_addr#$board\0" \
Shengzhou Liu47e7e032017-11-09 17:57:56 +0800195 "sd_bootcmd=echo Trying load from SD ..;" \
196 "mmcinfo; mmc read $load_addr " \
197 "$kernel_addr_sd $kernel_size_sd && " \
Vinitha Pillai-B572230c6e10a2017-11-22 10:38:35 +0530198 "env exists secureboot && mmc read $kernelheader_addr_r " \
199 "$kernelhdr_addr_sd $kernelhdr_size_sd " \
200 " && esbc_validate ${kernelheader_addr_r};" \
Shengzhou Liu47e7e032017-11-09 17:57:56 +0800201 "bootm $load_addr#$board\0"
Qianyu Gong6264ab62017-06-15 11:10:09 +0800202
Sumit Gargc064fc72017-03-30 09:53:13 +0530203#endif
204
Mingkai Hud2396512016-09-07 18:47:28 +0800205#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
206
Simon Glass89e0a3a2017-05-17 08:23:10 -0600207#include <asm/arch/soc.h>
208
Mingkai Hud2396512016-09-07 18:47:28 +0800209#endif /* __LS1046A_COMMON_H */