Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Ben Warren | 7efe927 | 2008-01-16 22:37:35 -0500 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (c) 2006 Ben Warren, Qstreams Networks Inc. |
Stefan Roese | 88fbf93 | 2010-04-15 16:07:28 +0200 | [diff] [blame] | 4 | * With help from the common/soft_spi and arch/powerpc/cpu/mpc8260 drivers |
Ben Warren | 7efe927 | 2008-01-16 22:37:35 -0500 | [diff] [blame] | 5 | */ |
| 6 | |
Tom Rini | abb9a04 | 2024-05-18 20:20:43 -0600 | [diff] [blame] | 7 | #include <common.h> |
Rasmus Villemoes | 1534031 | 2020-02-11 15:20:25 +0000 | [diff] [blame] | 8 | #include <clk.h> |
Jagan Teki | 52515d5 | 2019-04-29 01:58:53 +0530 | [diff] [blame] | 9 | #include <dm.h> |
| 10 | #include <errno.h> |
Simon Glass | 0f2af88 | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 11 | #include <log.h> |
Haavard Skinnemoen | d74084a | 2008-05-16 11:10:31 +0200 | [diff] [blame] | 12 | #include <malloc.h> |
Ben Warren | 7efe927 | 2008-01-16 22:37:35 -0500 | [diff] [blame] | 13 | #include <spi.h> |
| 14 | #include <asm/mpc8xxx_spi.h> |
Jagan Teki | 52515d5 | 2019-04-29 01:58:53 +0530 | [diff] [blame] | 15 | #include <asm-generic/gpio.h> |
Rasmus Villemoes | d4e78c3 | 2020-04-20 16:13:41 +0200 | [diff] [blame] | 16 | #include <dm/device_compat.h> |
Simon Glass | 4dcacfc | 2020-05-10 11:40:13 -0600 | [diff] [blame] | 17 | #include <linux/bitops.h> |
Simon Glass | dbd7954 | 2020-05-10 11:40:11 -0600 | [diff] [blame] | 18 | #include <linux/delay.h> |
Christophe Leroy | c58bd4a | 2023-03-02 16:26:26 +0100 | [diff] [blame] | 19 | #include <asm/arch/soc.h> |
Ben Warren | 7efe927 | 2008-01-16 22:37:35 -0500 | [diff] [blame] | 20 | |
Mario Six | 10f300a | 2019-04-29 01:58:41 +0530 | [diff] [blame] | 21 | enum { |
| 22 | SPI_EV_NE = BIT(31 - 22), /* Receiver Not Empty */ |
| 23 | SPI_EV_NF = BIT(31 - 23), /* Transmitter Not Full */ |
| 24 | }; |
| 25 | |
| 26 | enum { |
| 27 | SPI_MODE_LOOP = BIT(31 - 1), /* Loopback mode */ |
| 28 | SPI_MODE_CI = BIT(31 - 2), /* Clock invert */ |
| 29 | SPI_MODE_CP = BIT(31 - 3), /* Clock phase */ |
| 30 | SPI_MODE_DIV16 = BIT(31 - 4), /* Divide clock source by 16 */ |
| 31 | SPI_MODE_REV = BIT(31 - 5), /* Reverse mode - MSB first */ |
| 32 | SPI_MODE_MS = BIT(31 - 6), /* Always master */ |
| 33 | SPI_MODE_EN = BIT(31 - 7), /* Enable interface */ |
Christophe Leroy | c58bd4a | 2023-03-02 16:26:26 +0100 | [diff] [blame] | 34 | SPI_MODE_OP = BIT(31 - 17), /* CPU Mode, QE otherwise */ |
Mario Six | 10f300a | 2019-04-29 01:58:41 +0530 | [diff] [blame] | 35 | |
| 36 | SPI_MODE_LEN_MASK = 0xf00000, |
Rasmus Villemoes | 379e25d | 2020-02-11 15:20:25 +0000 | [diff] [blame] | 37 | SPI_MODE_LEN_SHIFT = 20, |
Rasmus Villemoes | 1534031 | 2020-02-11 15:20:25 +0000 | [diff] [blame] | 38 | SPI_MODE_PM_SHIFT = 16, |
Mario Six | 10f300a | 2019-04-29 01:58:41 +0530 | [diff] [blame] | 39 | SPI_MODE_PM_MASK = 0xf0000, |
Ben Warren | 7efe927 | 2008-01-16 22:37:35 -0500 | [diff] [blame] | 40 | |
Mario Six | 10f300a | 2019-04-29 01:58:41 +0530 | [diff] [blame] | 41 | SPI_COM_LST = BIT(31 - 9), |
| 42 | }; |
Ben Warren | 7efe927 | 2008-01-16 22:37:35 -0500 | [diff] [blame] | 43 | |
Jagan Teki | 52515d5 | 2019-04-29 01:58:53 +0530 | [diff] [blame] | 44 | struct mpc8xxx_priv { |
| 45 | spi8xxx_t *spi; |
| 46 | struct gpio_desc gpios[16]; |
Rasmus Villemoes | d31ec8b | 2020-02-11 15:20:24 +0000 | [diff] [blame] | 47 | int cs_count; |
Rasmus Villemoes | 1534031 | 2020-02-11 15:20:25 +0000 | [diff] [blame] | 48 | ulong clk_rate; |
Jagan Teki | 52515d5 | 2019-04-29 01:58:53 +0530 | [diff] [blame] | 49 | }; |
| 50 | |
Ben Warren | 7efe927 | 2008-01-16 22:37:35 -0500 | [diff] [blame] | 51 | #define SPI_TIMEOUT 1000 |
| 52 | |
Simon Glass | aad29ae | 2020-12-03 16:55:21 -0700 | [diff] [blame] | 53 | static int mpc8xxx_spi_of_to_plat(struct udevice *dev) |
Haavard Skinnemoen | d74084a | 2008-05-16 11:10:31 +0200 | [diff] [blame] | 54 | { |
Jagan Teki | 52515d5 | 2019-04-29 01:58:53 +0530 | [diff] [blame] | 55 | struct mpc8xxx_priv *priv = dev_get_priv(dev); |
Rasmus Villemoes | 1534031 | 2020-02-11 15:20:25 +0000 | [diff] [blame] | 56 | struct clk clk; |
Jagan Teki | 52515d5 | 2019-04-29 01:58:53 +0530 | [diff] [blame] | 57 | int ret; |
| 58 | |
Johan Jonker | 8d5d8e0 | 2023-03-13 01:32:04 +0100 | [diff] [blame] | 59 | priv->spi = dev_read_addr_ptr(dev); |
Jagan Teki | 52515d5 | 2019-04-29 01:58:53 +0530 | [diff] [blame] | 60 | |
Jagan Teki | 52515d5 | 2019-04-29 01:58:53 +0530 | [diff] [blame] | 61 | ret = gpio_request_list_by_name(dev, "gpios", priv->gpios, |
| 62 | ARRAY_SIZE(priv->gpios), GPIOD_IS_OUT | GPIOD_ACTIVE_LOW); |
| 63 | if (ret < 0) |
| 64 | return -EINVAL; |
| 65 | |
Rasmus Villemoes | d31ec8b | 2020-02-11 15:20:24 +0000 | [diff] [blame] | 66 | priv->cs_count = ret; |
Jagan Teki | 52515d5 | 2019-04-29 01:58:53 +0530 | [diff] [blame] | 67 | |
Rasmus Villemoes | 1534031 | 2020-02-11 15:20:25 +0000 | [diff] [blame] | 68 | ret = clk_get_by_index(dev, 0, &clk); |
| 69 | if (ret) { |
| 70 | dev_err(dev, "%s: clock not defined\n", __func__); |
| 71 | return ret; |
| 72 | } |
| 73 | |
| 74 | priv->clk_rate = clk_get_rate(&clk); |
| 75 | if (!priv->clk_rate) { |
| 76 | dev_err(dev, "%s: failed to get clock rate\n", __func__); |
| 77 | return -EINVAL; |
| 78 | } |
| 79 | |
Jagan Teki | 52515d5 | 2019-04-29 01:58:53 +0530 | [diff] [blame] | 80 | return 0; |
Haavard Skinnemoen | d74084a | 2008-05-16 11:10:31 +0200 | [diff] [blame] | 81 | } |
| 82 | |
Jagan Teki | 52515d5 | 2019-04-29 01:58:53 +0530 | [diff] [blame] | 83 | static int mpc8xxx_spi_probe(struct udevice *dev) |
Ben Warren | 7efe927 | 2008-01-16 22:37:35 -0500 | [diff] [blame] | 84 | { |
Jagan Teki | 52515d5 | 2019-04-29 01:58:53 +0530 | [diff] [blame] | 85 | struct mpc8xxx_priv *priv = dev_get_priv(dev); |
Rasmus Villemoes | 379e25d | 2020-02-11 15:20:25 +0000 | [diff] [blame] | 86 | spi8xxx_t *spi = priv->spi; |
Ben Warren | 7efe927 | 2008-01-16 22:37:35 -0500 | [diff] [blame] | 87 | |
Kim Phillips | b8e2520 | 2008-01-17 12:48:00 -0600 | [diff] [blame] | 88 | /* |
Ben Warren | 7efe927 | 2008-01-16 22:37:35 -0500 | [diff] [blame] | 89 | * SPI pins on the MPC83xx are not muxed, so all we do is initialize |
| 90 | * some registers |
Kim Phillips | b8e2520 | 2008-01-17 12:48:00 -0600 | [diff] [blame] | 91 | */ |
Rasmus Villemoes | 379e25d | 2020-02-11 15:20:25 +0000 | [diff] [blame] | 92 | out_be32(&priv->spi->mode, SPI_MODE_REV | SPI_MODE_MS); |
| 93 | |
Christophe Leroy | c58bd4a | 2023-03-02 16:26:26 +0100 | [diff] [blame] | 94 | if (dev_get_driver_data(dev) == SOC_MPC832X) |
| 95 | setbits_be32(&priv->spi->mode, SPI_MODE_OP); |
| 96 | |
Rasmus Villemoes | 379e25d | 2020-02-11 15:20:25 +0000 | [diff] [blame] | 97 | /* set len to 8 bits */ |
| 98 | setbits_be32(&spi->mode, (8 - 1) << SPI_MODE_LEN_SHIFT); |
Jagan Teki | 52515d5 | 2019-04-29 01:58:53 +0530 | [diff] [blame] | 99 | |
Rasmus Villemoes | 379e25d | 2020-02-11 15:20:25 +0000 | [diff] [blame] | 100 | setbits_be32(&spi->mode, SPI_MODE_EN); |
Jagan Teki | 52515d5 | 2019-04-29 01:58:53 +0530 | [diff] [blame] | 101 | |
Mario Six | 4d3082b | 2019-04-29 01:58:37 +0530 | [diff] [blame] | 102 | /* Clear all SPI events */ |
Jagan Teki | 52515d5 | 2019-04-29 01:58:53 +0530 | [diff] [blame] | 103 | setbits_be32(&priv->spi->event, 0xffffffff); |
Mario Six | 4d3082b | 2019-04-29 01:58:37 +0530 | [diff] [blame] | 104 | /* Mask all SPI interrupts */ |
Jagan Teki | 52515d5 | 2019-04-29 01:58:53 +0530 | [diff] [blame] | 105 | clrbits_be32(&priv->spi->mask, 0xffffffff); |
Mario Six | 4d3082b | 2019-04-29 01:58:37 +0530 | [diff] [blame] | 106 | /* LST bit doesn't do anything, so disregard */ |
Jagan Teki | 52515d5 | 2019-04-29 01:58:53 +0530 | [diff] [blame] | 107 | out_be32(&priv->spi->com, 0); |
| 108 | |
| 109 | return 0; |
Ben Warren | 7efe927 | 2008-01-16 22:37:35 -0500 | [diff] [blame] | 110 | } |
| 111 | |
Jagan Teki | 52515d5 | 2019-04-29 01:58:53 +0530 | [diff] [blame] | 112 | static void mpc8xxx_spi_cs_activate(struct udevice *dev) |
Haavard Skinnemoen | d74084a | 2008-05-16 11:10:31 +0200 | [diff] [blame] | 113 | { |
Jagan Teki | 52515d5 | 2019-04-29 01:58:53 +0530 | [diff] [blame] | 114 | struct mpc8xxx_priv *priv = dev_get_priv(dev->parent); |
Simon Glass | b75b15b | 2020-12-03 16:55:23 -0700 | [diff] [blame] | 115 | struct dm_spi_slave_plat *plat = dev_get_parent_plat(dev); |
Jagan Teki | 52515d5 | 2019-04-29 01:58:53 +0530 | [diff] [blame] | 116 | |
Simon Glass | 71fa5b4 | 2020-12-03 16:55:18 -0700 | [diff] [blame] | 117 | dm_gpio_set_value(&priv->gpios[plat->cs], 1); |
Haavard Skinnemoen | d74084a | 2008-05-16 11:10:31 +0200 | [diff] [blame] | 118 | } |
| 119 | |
Jagan Teki | 52515d5 | 2019-04-29 01:58:53 +0530 | [diff] [blame] | 120 | static void mpc8xxx_spi_cs_deactivate(struct udevice *dev) |
Haavard Skinnemoen | d74084a | 2008-05-16 11:10:31 +0200 | [diff] [blame] | 121 | { |
Jagan Teki | 52515d5 | 2019-04-29 01:58:53 +0530 | [diff] [blame] | 122 | struct mpc8xxx_priv *priv = dev_get_priv(dev->parent); |
Simon Glass | b75b15b | 2020-12-03 16:55:23 -0700 | [diff] [blame] | 123 | struct dm_spi_slave_plat *plat = dev_get_parent_plat(dev); |
Jagan Teki | 52515d5 | 2019-04-29 01:58:53 +0530 | [diff] [blame] | 124 | |
Simon Glass | 71fa5b4 | 2020-12-03 16:55:18 -0700 | [diff] [blame] | 125 | dm_gpio_set_value(&priv->gpios[plat->cs], 0); |
Haavard Skinnemoen | d74084a | 2008-05-16 11:10:31 +0200 | [diff] [blame] | 126 | } |
| 127 | |
Jagan Teki | 52515d5 | 2019-04-29 01:58:53 +0530 | [diff] [blame] | 128 | static int mpc8xxx_spi_xfer(struct udevice *dev, uint bitlen, |
| 129 | const void *dout, void *din, ulong flags) |
Ben Warren | 7efe927 | 2008-01-16 22:37:35 -0500 | [diff] [blame] | 130 | { |
Jagan Teki | 52515d5 | 2019-04-29 01:58:53 +0530 | [diff] [blame] | 131 | struct udevice *bus = dev->parent; |
| 132 | struct mpc8xxx_priv *priv = dev_get_priv(bus); |
| 133 | spi8xxx_t *spi = priv->spi; |
Simon Glass | b75b15b | 2020-12-03 16:55:23 -0700 | [diff] [blame] | 134 | struct dm_spi_slave_plat *plat = dev_get_parent_plat(dev); |
Rasmus Villemoes | 379e25d | 2020-02-11 15:20:25 +0000 | [diff] [blame] | 135 | u32 tmpdin = 0, tmpdout = 0, n; |
| 136 | const u8 *cout = dout; |
| 137 | u8 *cin = din; |
Christophe Leroy | c58bd4a | 2023-03-02 16:26:26 +0100 | [diff] [blame] | 138 | ulong type = dev_get_driver_data(bus); |
Ben Warren | 7efe927 | 2008-01-16 22:37:35 -0500 | [diff] [blame] | 139 | |
Jagan Teki | 52515d5 | 2019-04-29 01:58:53 +0530 | [diff] [blame] | 140 | debug("%s: slave %s:%u dout %08X din %08X bitlen %u\n", __func__, |
Simon Glass | 71fa5b4 | 2020-12-03 16:55:18 -0700 | [diff] [blame] | 141 | bus->name, plat->cs, (uint)dout, (uint)din, bitlen); |
| 142 | if (plat->cs >= priv->cs_count) { |
Rasmus Villemoes | d31ec8b | 2020-02-11 15:20:24 +0000 | [diff] [blame] | 143 | dev_err(dev, "chip select index %d too large (cs_count=%d)\n", |
Simon Glass | 71fa5b4 | 2020-12-03 16:55:18 -0700 | [diff] [blame] | 144 | plat->cs, priv->cs_count); |
Rasmus Villemoes | d31ec8b | 2020-02-11 15:20:24 +0000 | [diff] [blame] | 145 | return -EINVAL; |
| 146 | } |
Rasmus Villemoes | 379e25d | 2020-02-11 15:20:25 +0000 | [diff] [blame] | 147 | if (bitlen % 8) { |
| 148 | printf("*** spi_xfer: bitlen must be multiple of 8\n"); |
| 149 | return -ENOTSUPP; |
| 150 | } |
Ben Warren | 7efe927 | 2008-01-16 22:37:35 -0500 | [diff] [blame] | 151 | |
Haavard Skinnemoen | d74084a | 2008-05-16 11:10:31 +0200 | [diff] [blame] | 152 | if (flags & SPI_XFER_BEGIN) |
Jagan Teki | 52515d5 | 2019-04-29 01:58:53 +0530 | [diff] [blame] | 153 | mpc8xxx_spi_cs_activate(dev); |
Ben Warren | 7efe927 | 2008-01-16 22:37:35 -0500 | [diff] [blame] | 154 | |
Mario Six | 4d3082b | 2019-04-29 01:58:37 +0530 | [diff] [blame] | 155 | /* Clear all SPI events */ |
Mario Six | dee9949 | 2019-04-29 01:58:42 +0530 | [diff] [blame] | 156 | setbits_be32(&spi->event, 0xffffffff); |
Rasmus Villemoes | 379e25d | 2020-02-11 15:20:25 +0000 | [diff] [blame] | 157 | n = bitlen / 8; |
Ben Warren | 7efe927 | 2008-01-16 22:37:35 -0500 | [diff] [blame] | 158 | |
Rasmus Villemoes | 379e25d | 2020-02-11 15:20:25 +0000 | [diff] [blame] | 159 | /* Handle data in 8-bit chunks */ |
| 160 | while (n--) { |
Mario Six | 9083b13 | 2019-04-29 01:58:52 +0530 | [diff] [blame] | 161 | ulong start; |
Ben Warren | 7efe927 | 2008-01-16 22:37:35 -0500 | [diff] [blame] | 162 | |
Rasmus Villemoes | 379e25d | 2020-02-11 15:20:25 +0000 | [diff] [blame] | 163 | if (cout) |
| 164 | tmpdout = *cout++; |
Ben Warren | 7efe927 | 2008-01-16 22:37:35 -0500 | [diff] [blame] | 165 | |
Christophe Leroy | c58bd4a | 2023-03-02 16:26:26 +0100 | [diff] [blame] | 166 | if (type == SOC_MPC832X) |
| 167 | tmpdout <<= 24; |
| 168 | |
Mario Six | 4d3082b | 2019-04-29 01:58:37 +0530 | [diff] [blame] | 169 | /* Write the data out */ |
Mario Six | dee9949 | 2019-04-29 01:58:42 +0530 | [diff] [blame] | 170 | out_be32(&spi->tx, tmpdout); |
Mario Six | 4d3082b | 2019-04-29 01:58:37 +0530 | [diff] [blame] | 171 | |
Mario Six | f9d5ca2 | 2019-04-29 01:58:40 +0530 | [diff] [blame] | 172 | debug("*** %s: ... %08x written\n", __func__, tmpdout); |
Ben Warren | 7efe927 | 2008-01-16 22:37:35 -0500 | [diff] [blame] | 173 | |
Kim Phillips | b8e2520 | 2008-01-17 12:48:00 -0600 | [diff] [blame] | 174 | /* |
Ben Warren | 7efe927 | 2008-01-16 22:37:35 -0500 | [diff] [blame] | 175 | * Wait for SPI transmit to get out |
| 176 | * or time out (1 second = 1000 ms) |
| 177 | * The NE event must be read and cleared first |
Kim Phillips | b8e2520 | 2008-01-17 12:48:00 -0600 | [diff] [blame] | 178 | */ |
Mario Six | 9083b13 | 2019-04-29 01:58:52 +0530 | [diff] [blame] | 179 | start = get_timer(0); |
| 180 | do { |
Mario Six | 8d684ec | 2019-04-29 01:58:46 +0530 | [diff] [blame] | 181 | u32 event = in_be32(&spi->event); |
Mario Six | 4b671e1 | 2019-04-29 01:58:44 +0530 | [diff] [blame] | 182 | bool have_ne = event & SPI_EV_NE; |
| 183 | bool have_nf = event & SPI_EV_NF; |
| 184 | |
Mario Six | 2afedfe | 2019-04-29 01:58:45 +0530 | [diff] [blame] | 185 | if (!have_ne) |
| 186 | continue; |
Ben Warren | 7efe927 | 2008-01-16 22:37:35 -0500 | [diff] [blame] | 187 | |
Mario Six | 2afedfe | 2019-04-29 01:58:45 +0530 | [diff] [blame] | 188 | tmpdin = in_be32(&spi->rx); |
| 189 | setbits_be32(&spi->event, SPI_EV_NE); |
| 190 | |
Christophe Leroy | c58bd4a | 2023-03-02 16:26:26 +0100 | [diff] [blame] | 191 | if (type == SOC_MPC832X) |
| 192 | tmpdin >>= 16; |
| 193 | |
Rasmus Villemoes | 379e25d | 2020-02-11 15:20:25 +0000 | [diff] [blame] | 194 | if (cin) |
| 195 | *cin++ = tmpdin; |
Mario Six | 2afedfe | 2019-04-29 01:58:45 +0530 | [diff] [blame] | 196 | |
Kim Phillips | b8e2520 | 2008-01-17 12:48:00 -0600 | [diff] [blame] | 197 | /* |
| 198 | * Only bail when we've had both NE and NF events. |
Ben Warren | 7efe927 | 2008-01-16 22:37:35 -0500 | [diff] [blame] | 199 | * This will cause timeouts on RO devices, so maybe |
| 200 | * in the future put an arbitrary delay after writing |
Kim Phillips | b8e2520 | 2008-01-17 12:48:00 -0600 | [diff] [blame] | 201 | * the device. Arbitrary delays suck, though... |
| 202 | */ |
Mario Six | 2afedfe | 2019-04-29 01:58:45 +0530 | [diff] [blame] | 203 | if (have_nf) |
Ben Warren | 7efe927 | 2008-01-16 22:37:35 -0500 | [diff] [blame] | 204 | break; |
Mario Six | 9083b13 | 2019-04-29 01:58:52 +0530 | [diff] [blame] | 205 | |
| 206 | mdelay(1); |
| 207 | } while (get_timer(start) < SPI_TIMEOUT); |
Mario Six | 2afedfe | 2019-04-29 01:58:45 +0530 | [diff] [blame] | 208 | |
Jagan Teki | 52515d5 | 2019-04-29 01:58:53 +0530 | [diff] [blame] | 209 | if (get_timer(start) >= SPI_TIMEOUT) { |
Mario Six | f9d5ca2 | 2019-04-29 01:58:40 +0530 | [diff] [blame] | 210 | debug("*** %s: Time out during SPI transfer\n", |
| 211 | __func__); |
Jagan Teki | 52515d5 | 2019-04-29 01:58:53 +0530 | [diff] [blame] | 212 | return -ETIMEDOUT; |
| 213 | } |
Ben Warren | 7efe927 | 2008-01-16 22:37:35 -0500 | [diff] [blame] | 214 | |
Mario Six | f9d5ca2 | 2019-04-29 01:58:40 +0530 | [diff] [blame] | 215 | debug("*** %s: transfer ended. Value=%08x\n", __func__, tmpdin); |
Ben Warren | 7efe927 | 2008-01-16 22:37:35 -0500 | [diff] [blame] | 216 | } |
| 217 | |
Haavard Skinnemoen | d74084a | 2008-05-16 11:10:31 +0200 | [diff] [blame] | 218 | if (flags & SPI_XFER_END) |
Jagan Teki | 52515d5 | 2019-04-29 01:58:53 +0530 | [diff] [blame] | 219 | mpc8xxx_spi_cs_deactivate(dev); |
| 220 | |
| 221 | return 0; |
| 222 | } |
| 223 | |
| 224 | static int mpc8xxx_spi_set_speed(struct udevice *dev, uint speed) |
| 225 | { |
Rasmus Villemoes | 1534031 | 2020-02-11 15:20:25 +0000 | [diff] [blame] | 226 | struct mpc8xxx_priv *priv = dev_get_priv(dev); |
| 227 | spi8xxx_t *spi = priv->spi; |
| 228 | u32 bits, mask, div16, pm; |
| 229 | u32 mode; |
| 230 | ulong clk; |
| 231 | |
| 232 | clk = priv->clk_rate; |
| 233 | if (clk / 64 > speed) { |
| 234 | div16 = SPI_MODE_DIV16; |
| 235 | clk /= 16; |
| 236 | } else { |
| 237 | div16 = 0; |
| 238 | } |
| 239 | pm = (clk - 1)/(4*speed) + 1; |
| 240 | if (pm > 16) { |
| 241 | dev_err(dev, "requested speed %u too small\n", speed); |
| 242 | return -EINVAL; |
| 243 | } |
| 244 | pm--; |
| 245 | |
| 246 | bits = div16 | (pm << SPI_MODE_PM_SHIFT); |
| 247 | mask = SPI_MODE_DIV16 | SPI_MODE_PM_MASK; |
| 248 | mode = in_be32(&spi->mode); |
| 249 | if ((mode & mask) != bits) { |
| 250 | /* Must clear mode[EN] while changing speed. */ |
| 251 | mode &= ~(mask | SPI_MODE_EN); |
| 252 | out_be32(&spi->mode, mode); |
| 253 | mode |= bits; |
| 254 | out_be32(&spi->mode, mode); |
| 255 | mode |= SPI_MODE_EN; |
| 256 | out_be32(&spi->mode, mode); |
| 257 | } |
| 258 | |
| 259 | debug("requested speed %u, set speed to %lu/(%s4*%u) == %lu\n", |
| 260 | speed, priv->clk_rate, div16 ? "16*" : "", pm + 1, |
| 261 | clk/(4*(pm + 1))); |
| 262 | |
Rasmus Villemoes | 379e25d | 2020-02-11 15:20:25 +0000 | [diff] [blame] | 263 | return 0; |
Jagan Teki | 52515d5 | 2019-04-29 01:58:53 +0530 | [diff] [blame] | 264 | } |
Kim Phillips | b8e2520 | 2008-01-17 12:48:00 -0600 | [diff] [blame] | 265 | |
Jagan Teki | 52515d5 | 2019-04-29 01:58:53 +0530 | [diff] [blame] | 266 | static int mpc8xxx_spi_set_mode(struct udevice *dev, uint mode) |
| 267 | { |
| 268 | /* TODO(mario.six@gdsys.cc): Using SPI_CPHA (for clock phase) and |
| 269 | * SPI_CPOL (for clock polarity) should work |
| 270 | */ |
Ben Warren | 7efe927 | 2008-01-16 22:37:35 -0500 | [diff] [blame] | 271 | return 0; |
| 272 | } |
Jagan Teki | 52515d5 | 2019-04-29 01:58:53 +0530 | [diff] [blame] | 273 | |
| 274 | static const struct dm_spi_ops mpc8xxx_spi_ops = { |
| 275 | .xfer = mpc8xxx_spi_xfer, |
| 276 | .set_speed = mpc8xxx_spi_set_speed, |
| 277 | .set_mode = mpc8xxx_spi_set_mode, |
| 278 | /* |
| 279 | * cs_info is not needed, since we require all chip selects to be |
| 280 | * in the device tree explicitly |
| 281 | */ |
| 282 | }; |
| 283 | |
| 284 | static const struct udevice_id mpc8xxx_spi_ids[] = { |
| 285 | { .compatible = "fsl,spi" }, |
Christophe Leroy | c58bd4a | 2023-03-02 16:26:26 +0100 | [diff] [blame] | 286 | { .compatible = "fsl,mpc832x-spi", .data = SOC_MPC832X }, |
Jagan Teki | 52515d5 | 2019-04-29 01:58:53 +0530 | [diff] [blame] | 287 | { } |
| 288 | }; |
| 289 | |
| 290 | U_BOOT_DRIVER(mpc8xxx_spi) = { |
| 291 | .name = "mpc8xxx_spi", |
| 292 | .id = UCLASS_SPI, |
| 293 | .of_match = mpc8xxx_spi_ids, |
| 294 | .ops = &mpc8xxx_spi_ops, |
Simon Glass | aad29ae | 2020-12-03 16:55:21 -0700 | [diff] [blame] | 295 | .of_to_plat = mpc8xxx_spi_of_to_plat, |
Jagan Teki | 52515d5 | 2019-04-29 01:58:53 +0530 | [diff] [blame] | 296 | .probe = mpc8xxx_spi_probe, |
Simon Glass | 8a2b47f | 2020-12-03 16:55:17 -0700 | [diff] [blame] | 297 | .priv_auto = sizeof(struct mpc8xxx_priv), |
Jagan Teki | 52515d5 | 2019-04-29 01:58:53 +0530 | [diff] [blame] | 298 | }; |