Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Yegor Yefremov | fa8b71b | 2015-05-29 19:27:29 +0200 | [diff] [blame] | 2 | /* |
| 3 | * board.c |
| 4 | * |
| 5 | * Board functions for TI AM335X based boards |
| 6 | * |
Nishanth Menon | eaa39c6 | 2023-11-01 15:56:03 -0500 | [diff] [blame] | 7 | * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/ |
Yegor Yefremov | fa8b71b | 2015-05-29 19:27:29 +0200 | [diff] [blame] | 8 | */ |
| 9 | |
Tom Rini | abb9a04 | 2024-05-18 20:20:43 -0600 | [diff] [blame] | 10 | #include <common.h> |
Simon Glass | 5e6201b | 2019-08-01 09:46:51 -0600 | [diff] [blame] | 11 | #include <env.h> |
Yegor Yefremov | fa8b71b | 2015-05-29 19:27:29 +0200 | [diff] [blame] | 12 | #include <errno.h> |
Simon Glass | a7b5130 | 2019-11-14 12:57:46 -0700 | [diff] [blame] | 13 | #include <init.h> |
Simon Glass | 274e0b0 | 2020-05-10 11:39:56 -0600 | [diff] [blame] | 14 | #include <net.h> |
Simon Glass | 3673618 | 2019-11-14 12:57:24 -0700 | [diff] [blame] | 15 | #include <serial.h> |
Simon Glass | 3ba929a | 2020-10-30 21:38:53 -0600 | [diff] [blame] | 16 | #include <asm/global_data.h> |
Masahiro Yamada | 75f82d0 | 2018-03-05 01:20:11 +0900 | [diff] [blame] | 17 | #include <linux/libfdt.h> |
Yegor Yefremov | fa8b71b | 2015-05-29 19:27:29 +0200 | [diff] [blame] | 18 | #include <spl.h> |
| 19 | #include <asm/arch/cpu.h> |
| 20 | #include <asm/arch/hardware.h> |
| 21 | #include <asm/arch/omap.h> |
| 22 | #include <asm/arch/ddr_defs.h> |
| 23 | #include <asm/arch/clock.h> |
| 24 | #include <asm/arch/gpio.h> |
| 25 | #include <asm/arch/mmc_host_def.h> |
| 26 | #include <asm/arch/sys_proto.h> |
| 27 | #include <asm/arch/mem.h> |
| 28 | #include <asm/arch/mux.h> |
| 29 | #include <asm/io.h> |
| 30 | #include <asm/emif.h> |
| 31 | #include <asm/gpio.h> |
| 32 | #include <i2c.h> |
| 33 | #include <miiphy.h> |
| 34 | #include <cpsw.h> |
Yegor Yefremov | fa8b71b | 2015-05-29 19:27:29 +0200 | [diff] [blame] | 35 | #include <power/tps65910.h> |
Yegor Yefremov | fa8b71b | 2015-05-29 19:27:29 +0200 | [diff] [blame] | 36 | #include <watchdog.h> |
| 37 | #include "board.h" |
| 38 | |
| 39 | DECLARE_GLOBAL_DATA_PTR; |
| 40 | |
Yegor Yefremov | 18668a4 | 2018-11-22 09:19:30 +0100 | [diff] [blame] | 41 | /* GPIO that controls DIP switch and mPCIe slot */ |
Yegor Yefremov | fa8b71b | 2015-05-29 19:27:29 +0200 | [diff] [blame] | 42 | #define DIP_S1 44 |
Yegor Yefremov | 3b987da | 2016-12-01 12:52:17 +0100 | [diff] [blame] | 43 | #define MPCIE_SW 100 |
Yegor Yefremov | fa8b71b | 2015-05-29 19:27:29 +0200 | [diff] [blame] | 44 | |
| 45 | static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; |
| 46 | |
| 47 | static int baltos_set_console(void) |
| 48 | { |
| 49 | int val, i, dips = 0; |
| 50 | char buf[7]; |
| 51 | |
| 52 | for (i = 0; i < 4; i++) { |
| 53 | sprintf(buf, "dip_s%d", i + 1); |
| 54 | |
| 55 | if (gpio_request(DIP_S1 + i, buf)) { |
| 56 | printf("failed to export GPIO %d\n", DIP_S1 + i); |
| 57 | return 0; |
| 58 | } |
| 59 | |
| 60 | if (gpio_direction_input(DIP_S1 + i)) { |
| 61 | printf("failed to set GPIO %d direction\n", DIP_S1 + i); |
| 62 | return 0; |
| 63 | } |
| 64 | |
| 65 | val = gpio_get_value(DIP_S1 + i); |
| 66 | dips |= val << i; |
| 67 | } |
| 68 | |
| 69 | printf("DIPs: 0x%1x\n", (~dips) & 0xf); |
| 70 | |
| 71 | if ((dips & 0xf) == 0xe) |
Simon Glass | 6a38e41 | 2017-08-03 12:22:09 -0600 | [diff] [blame] | 72 | env_set("console", "ttyUSB0,115200n8"); |
Yegor Yefremov | fa8b71b | 2015-05-29 19:27:29 +0200 | [diff] [blame] | 73 | |
| 74 | return 0; |
| 75 | } |
| 76 | |
| 77 | static int read_eeprom(BSP_VS_HWPARAM *header) |
| 78 | { |
Yegor Yefremov | ded7f38 | 2023-05-15 16:26:44 +0200 | [diff] [blame] | 79 | int rc; |
| 80 | struct udevice *dev; |
| 81 | struct udevice *bus; |
| 82 | |
| 83 | rc = uclass_get_device_by_seq(UCLASS_I2C, 1, &bus); |
| 84 | if (rc) |
| 85 | return rc; |
Yegor Yefremov | fa8b71b | 2015-05-29 19:27:29 +0200 | [diff] [blame] | 86 | |
| 87 | /* Check if baseboard eeprom is available */ |
Yegor Yefremov | ded7f38 | 2023-05-15 16:26:44 +0200 | [diff] [blame] | 88 | if (dm_i2c_probe(bus, CONFIG_SYS_I2C_EEPROM_ADDR, 0, &dev)) { |
Yegor Yefremov | fa8b71b | 2015-05-29 19:27:29 +0200 | [diff] [blame] | 89 | puts("Could not probe the EEPROM; something fundamentally " |
| 90 | "wrong on the I2C bus.\n"); |
| 91 | return -ENODEV; |
| 92 | } |
| 93 | |
| 94 | /* read the eeprom using i2c */ |
Yegor Yefremov | ded7f38 | 2023-05-15 16:26:44 +0200 | [diff] [blame] | 95 | if (dm_i2c_read(dev, 0, (uchar *)header, |
Yegor Yefremov | fa8b71b | 2015-05-29 19:27:29 +0200 | [diff] [blame] | 96 | sizeof(BSP_VS_HWPARAM))) { |
| 97 | puts("Could not read the EEPROM; something fundamentally" |
| 98 | " wrong on the I2C bus.\n"); |
| 99 | return -EIO; |
| 100 | } |
| 101 | |
| 102 | if (header->Magic != 0xDEADBEEF) { |
| 103 | |
| 104 | printf("Incorrect magic number (0x%x) in EEPROM\n", |
| 105 | header->Magic); |
| 106 | |
| 107 | /* fill default values */ |
| 108 | header->SystemId = 211; |
| 109 | header->MAC1[0] = 0x00; |
| 110 | header->MAC1[1] = 0x00; |
| 111 | header->MAC1[2] = 0x00; |
| 112 | header->MAC1[3] = 0x00; |
| 113 | header->MAC1[4] = 0x00; |
| 114 | header->MAC1[5] = 0x01; |
| 115 | |
| 116 | header->MAC2[0] = 0x00; |
| 117 | header->MAC2[1] = 0x00; |
| 118 | header->MAC2[2] = 0x00; |
| 119 | header->MAC2[3] = 0x00; |
| 120 | header->MAC2[4] = 0x00; |
| 121 | header->MAC2[5] = 0x02; |
| 122 | |
| 123 | header->MAC3[0] = 0x00; |
| 124 | header->MAC3[1] = 0x00; |
| 125 | header->MAC3[2] = 0x00; |
| 126 | header->MAC3[3] = 0x00; |
| 127 | header->MAC3[4] = 0x00; |
| 128 | header->MAC3[5] = 0x03; |
| 129 | } |
| 130 | |
| 131 | return 0; |
| 132 | } |
| 133 | |
| 134 | #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT) |
| 135 | |
| 136 | static const struct ddr_data ddr3_baltos_data = { |
| 137 | .datardsratio0 = MT41K256M16HA125E_RD_DQS, |
| 138 | .datawdsratio0 = MT41K256M16HA125E_WR_DQS, |
| 139 | .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE, |
| 140 | .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA, |
| 141 | }; |
| 142 | |
| 143 | static const struct cmd_control ddr3_baltos_cmd_ctrl_data = { |
| 144 | .cmd0csratio = MT41K256M16HA125E_RATIO, |
| 145 | .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT, |
| 146 | |
| 147 | .cmd1csratio = MT41K256M16HA125E_RATIO, |
| 148 | .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT, |
| 149 | |
| 150 | .cmd2csratio = MT41K256M16HA125E_RATIO, |
| 151 | .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT, |
| 152 | }; |
| 153 | |
| 154 | static struct emif_regs ddr3_baltos_emif_reg_data = { |
| 155 | .sdram_config = MT41K256M16HA125E_EMIF_SDCFG, |
| 156 | .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF, |
| 157 | .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1, |
| 158 | .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2, |
| 159 | .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3, |
| 160 | .zq_config = MT41K256M16HA125E_ZQ_CFG, |
| 161 | .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY, |
| 162 | }; |
| 163 | |
| 164 | #ifdef CONFIG_SPL_OS_BOOT |
| 165 | int spl_start_uboot(void) |
| 166 | { |
| 167 | /* break into full u-boot on 'c' */ |
| 168 | return (serial_tstc() && serial_getc() == 'c'); |
| 169 | } |
| 170 | #endif |
| 171 | |
| 172 | #define OSC (V_OSCK/1000000) |
| 173 | const struct dpll_params dpll_ddr = { |
| 174 | 266, OSC-1, 1, -1, -1, -1, -1}; |
| 175 | const struct dpll_params dpll_ddr_evm_sk = { |
| 176 | 303, OSC-1, 1, -1, -1, -1, -1}; |
| 177 | const struct dpll_params dpll_ddr_baltos = { |
| 178 | 400, OSC-1, 1, -1, -1, -1, -1}; |
| 179 | |
| 180 | void am33xx_spl_board_init(void) |
| 181 | { |
Yegor Yefremov | ded7f38 | 2023-05-15 16:26:44 +0200 | [diff] [blame] | 182 | int sil_rev, mpu_vdd; |
| 183 | int freq; |
| 184 | |
| 185 | enable_i2c1_pin_mux(); |
| 186 | i2c_set_bus_num(1); |
Yegor Yefremov | fa8b71b | 2015-05-29 19:27:29 +0200 | [diff] [blame] | 187 | |
Yegor Yefremov | ded7f38 | 2023-05-15 16:26:44 +0200 | [diff] [blame] | 188 | freq = am335x_get_efuse_mpu_max_freq(cdev); |
Yegor Yefremov | fa8b71b | 2015-05-29 19:27:29 +0200 | [diff] [blame] | 189 | |
| 190 | /* |
Yegor Yefremov | ded7f38 | 2023-05-15 16:26:44 +0200 | [diff] [blame] | 191 | * The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all |
Yegor Yefremov | fa8b71b | 2015-05-29 19:27:29 +0200 | [diff] [blame] | 192 | * MPU frequencies we support we use a CORE voltage of |
Yegor Yefremov | ded7f38 | 2023-05-15 16:26:44 +0200 | [diff] [blame] | 193 | * 1.1375V. For MPU voltage we need to switch based on |
Yegor Yefremov | fa8b71b | 2015-05-29 19:27:29 +0200 | [diff] [blame] | 194 | * the frequency we are running at. |
| 195 | */ |
Yegor Yefremov | ded7f38 | 2023-05-15 16:26:44 +0200 | [diff] [blame] | 196 | if (power_tps65910_init(1)) |
Yegor Yefremov | fa8b71b | 2015-05-29 19:27:29 +0200 | [diff] [blame] | 197 | return; |
Yegor Yefremov | fa8b71b | 2015-05-29 19:27:29 +0200 | [diff] [blame] | 198 | /* |
| 199 | * Depending on MPU clock and PG we will need a different |
| 200 | * VDD to drive at that speed. |
| 201 | */ |
| 202 | sil_rev = readl(&cdev->deviceid) >> 28; |
Yegor Yefremov | ded7f38 | 2023-05-15 16:26:44 +0200 | [diff] [blame] | 203 | mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, freq); |
Yegor Yefremov | fa8b71b | 2015-05-29 19:27:29 +0200 | [diff] [blame] | 204 | |
| 205 | /* Tell the TPS65910 to use i2c */ |
| 206 | tps65910_set_i2c_control(); |
| 207 | |
| 208 | /* First update MPU voltage. */ |
| 209 | if (tps65910_voltage_update(MPU, mpu_vdd)) |
| 210 | return; |
| 211 | |
| 212 | /* Second, update the CORE voltage. */ |
| 213 | if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3)) |
| 214 | return; |
| 215 | |
Yegor Yefremov | fa8b71b | 2015-05-29 19:27:29 +0200 | [diff] [blame] | 216 | writel(0x000010ff, PRM_DEVICE_INST + 4); |
| 217 | } |
| 218 | |
| 219 | const struct dpll_params *get_dpll_ddr_params(void) |
| 220 | { |
| 221 | enable_i2c1_pin_mux(); |
| 222 | i2c_set_bus_num(1); |
| 223 | |
| 224 | return &dpll_ddr_baltos; |
| 225 | } |
| 226 | |
| 227 | void set_uart_mux_conf(void) |
| 228 | { |
| 229 | enable_uart0_pin_mux(); |
| 230 | } |
| 231 | |
| 232 | void set_mux_conf_regs(void) |
| 233 | { |
| 234 | enable_board_pin_mux(); |
| 235 | } |
| 236 | |
| 237 | const struct ctrl_ioregs ioregs_baltos = { |
| 238 | .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, |
| 239 | .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, |
| 240 | .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE, |
| 241 | .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, |
| 242 | .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, |
| 243 | }; |
| 244 | |
| 245 | void sdram_init(void) |
| 246 | { |
Yegor Yefremov | fa8b71b | 2015-05-29 19:27:29 +0200 | [diff] [blame] | 247 | config_ddr(400, &ioregs_baltos, |
| 248 | &ddr3_baltos_data, |
| 249 | &ddr3_baltos_cmd_ctrl_data, |
| 250 | &ddr3_baltos_emif_reg_data, 0); |
| 251 | } |
| 252 | #endif |
| 253 | |
| 254 | /* |
| 255 | * Basic board specific setup. Pinmux has been handled already. |
| 256 | */ |
| 257 | int board_init(void) |
| 258 | { |
| 259 | #if defined(CONFIG_HW_WATCHDOG) |
| 260 | hw_watchdog_init(); |
| 261 | #endif |
| 262 | |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 263 | gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; |
Miquel Raynal | d093536 | 2019-10-03 19:50:03 +0200 | [diff] [blame] | 264 | #if defined(CONFIG_NOR) || defined(CONFIG_MTD_RAW_NAND) |
Yegor Yefremov | fa8b71b | 2015-05-29 19:27:29 +0200 | [diff] [blame] | 265 | gpmc_init(); |
| 266 | #endif |
| 267 | return 0; |
| 268 | } |
| 269 | |
Masahiro Yamada | f7ed78b | 2020-06-26 15:13:33 +0900 | [diff] [blame] | 270 | int ft_board_setup(void *blob, struct bd_info *bd) |
Yegor Yefremov | fa8b71b | 2015-05-29 19:27:29 +0200 | [diff] [blame] | 271 | { |
| 272 | int node, ret; |
| 273 | unsigned char mac_addr[6]; |
| 274 | BSP_VS_HWPARAM header; |
| 275 | |
| 276 | /* get production data */ |
| 277 | if (read_eeprom(&header)) |
| 278 | return 0; |
| 279 | |
| 280 | /* setup MAC1 */ |
| 281 | mac_addr[0] = header.MAC1[0]; |
| 282 | mac_addr[1] = header.MAC1[1]; |
| 283 | mac_addr[2] = header.MAC1[2]; |
| 284 | mac_addr[3] = header.MAC1[3]; |
| 285 | mac_addr[4] = header.MAC1[4]; |
| 286 | mac_addr[5] = header.MAC1[5]; |
| 287 | |
| 288 | |
Yegor Yefremov | c2797f0 | 2019-08-09 07:21:57 +0200 | [diff] [blame] | 289 | node = fdt_path_offset(blob, "ethernet0"); |
Yegor Yefremov | fa8b71b | 2015-05-29 19:27:29 +0200 | [diff] [blame] | 290 | if (node < 0) { |
Yegor Yefremov | c2797f0 | 2019-08-09 07:21:57 +0200 | [diff] [blame] | 291 | printf("no ethernet0 path offset\n"); |
Yegor Yefremov | fa8b71b | 2015-05-29 19:27:29 +0200 | [diff] [blame] | 292 | return -ENODEV; |
| 293 | } |
| 294 | |
| 295 | ret = fdt_setprop(blob, node, "mac-address", &mac_addr, 6); |
| 296 | if (ret) { |
Yegor Yefremov | c2797f0 | 2019-08-09 07:21:57 +0200 | [diff] [blame] | 297 | printf("error setting mac-address property\n"); |
Yegor Yefremov | fa8b71b | 2015-05-29 19:27:29 +0200 | [diff] [blame] | 298 | return -ENODEV; |
| 299 | } |
| 300 | |
| 301 | /* setup MAC2 */ |
| 302 | mac_addr[0] = header.MAC2[0]; |
| 303 | mac_addr[1] = header.MAC2[1]; |
| 304 | mac_addr[2] = header.MAC2[2]; |
| 305 | mac_addr[3] = header.MAC2[3]; |
| 306 | mac_addr[4] = header.MAC2[4]; |
| 307 | mac_addr[5] = header.MAC2[5]; |
| 308 | |
Yegor Yefremov | c2797f0 | 2019-08-09 07:21:57 +0200 | [diff] [blame] | 309 | node = fdt_path_offset(blob, "ethernet1"); |
Yegor Yefremov | fa8b71b | 2015-05-29 19:27:29 +0200 | [diff] [blame] | 310 | if (node < 0) { |
Yegor Yefremov | c2797f0 | 2019-08-09 07:21:57 +0200 | [diff] [blame] | 311 | printf("no ethernet1 path offset\n"); |
Yegor Yefremov | fa8b71b | 2015-05-29 19:27:29 +0200 | [diff] [blame] | 312 | return -ENODEV; |
| 313 | } |
| 314 | |
| 315 | ret = fdt_setprop(blob, node, "mac-address", &mac_addr, 6); |
| 316 | if (ret) { |
Yegor Yefremov | c2797f0 | 2019-08-09 07:21:57 +0200 | [diff] [blame] | 317 | printf("error setting mac-address property\n"); |
Yegor Yefremov | fa8b71b | 2015-05-29 19:27:29 +0200 | [diff] [blame] | 318 | return -ENODEV; |
| 319 | } |
| 320 | |
| 321 | printf("\nFDT was successfully setup\n"); |
| 322 | |
| 323 | return 0; |
| 324 | } |
| 325 | |
Yegor Yefremov | 3b987da | 2016-12-01 12:52:17 +0100 | [diff] [blame] | 326 | static struct module_pin_mux pcie_sw_pin_mux[] = { |
| 327 | {OFFSET(mii1_rxdv), (MODE(7) | PULLUDEN )}, /* GPIO3_4 */ |
| 328 | {-1}, |
| 329 | }; |
| 330 | |
Yegor Yefremov | fa8b71b | 2015-05-29 19:27:29 +0200 | [diff] [blame] | 331 | static struct module_pin_mux dip_pin_mux[] = { |
| 332 | {OFFSET(gpmc_ad12), (MODE(7) | RXACTIVE )}, /* GPIO1_12 */ |
| 333 | {OFFSET(gpmc_ad13), (MODE(7) | RXACTIVE )}, /* GPIO1_13 */ |
| 334 | {OFFSET(gpmc_ad14), (MODE(7) | RXACTIVE )}, /* GPIO1_14 */ |
| 335 | {OFFSET(gpmc_ad15), (MODE(7) | RXACTIVE )}, /* GPIO1_15 */ |
| 336 | {-1}, |
| 337 | }; |
| 338 | |
| 339 | #ifdef CONFIG_BOARD_LATE_INIT |
| 340 | int board_late_init(void) |
| 341 | { |
| 342 | #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG |
| 343 | BSP_VS_HWPARAM header; |
| 344 | char model[4]; |
| 345 | |
| 346 | /* get production data */ |
| 347 | if (read_eeprom(&header)) { |
Ben Whitten | 34fd6c9 | 2015-12-30 13:05:58 +0000 | [diff] [blame] | 348 | strcpy(model, "211"); |
Yegor Yefremov | fa8b71b | 2015-05-29 19:27:29 +0200 | [diff] [blame] | 349 | } else { |
| 350 | sprintf(model, "%d", header.SystemId); |
| 351 | if (header.SystemId == 215) { |
| 352 | configure_module_pin_mux(dip_pin_mux); |
| 353 | baltos_set_console(); |
| 354 | } |
| 355 | } |
Yegor Yefremov | 3b987da | 2016-12-01 12:52:17 +0100 | [diff] [blame] | 356 | |
| 357 | /* turn power for the mPCIe slot */ |
| 358 | configure_module_pin_mux(pcie_sw_pin_mux); |
| 359 | if (gpio_request(MPCIE_SW, "mpcie_sw")) { |
| 360 | printf("failed to export GPIO %d\n", MPCIE_SW); |
| 361 | return -ENODEV; |
| 362 | } |
| 363 | if (gpio_direction_output(MPCIE_SW, 1)) { |
| 364 | printf("failed to set GPIO %d direction\n", MPCIE_SW); |
| 365 | return -ENODEV; |
| 366 | } |
| 367 | |
Simon Glass | 6a38e41 | 2017-08-03 12:22:09 -0600 | [diff] [blame] | 368 | env_set("board_name", model); |
Yegor Yefremov | fa8b71b | 2015-05-29 19:27:29 +0200 | [diff] [blame] | 369 | #endif |
| 370 | |
| 371 | return 0; |
| 372 | } |
| 373 | #endif |
| 374 | |
| 375 | #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ |
Simon Glass | e5cd9a4 | 2021-07-10 21:14:26 -0600 | [diff] [blame] | 376 | (defined(CONFIG_SPL_ETH) && defined(CONFIG_SPL_BUILD)) |
Yegor Yefremov | fa8b71b | 2015-05-29 19:27:29 +0200 | [diff] [blame] | 377 | static void cpsw_control(int enabled) |
| 378 | { |
| 379 | /* VTP can be added here */ |
| 380 | |
| 381 | return; |
| 382 | } |
| 383 | |
| 384 | static struct cpsw_slave_data cpsw_slaves[] = { |
| 385 | { |
| 386 | .slave_reg_ofs = 0x208, |
| 387 | .sliver_reg_ofs = 0xd80, |
| 388 | .phy_addr = 0, |
| 389 | }, |
| 390 | { |
| 391 | .slave_reg_ofs = 0x308, |
| 392 | .sliver_reg_ofs = 0xdc0, |
| 393 | .phy_addr = 7, |
| 394 | }, |
| 395 | }; |
| 396 | |
| 397 | static struct cpsw_platform_data cpsw_data = { |
| 398 | .mdio_base = CPSW_MDIO_BASE, |
| 399 | .cpsw_base = CPSW_BASE, |
| 400 | .mdio_div = 0xff, |
| 401 | .channels = 8, |
| 402 | .cpdma_reg_ofs = 0x800, |
| 403 | .slaves = 2, |
| 404 | .slave_data = cpsw_slaves, |
| 405 | .active_slave = 1, |
| 406 | .ale_reg_ofs = 0xd00, |
| 407 | .ale_entries = 1024, |
| 408 | .host_port_reg_ofs = 0x108, |
| 409 | .hw_stats_reg_ofs = 0x900, |
| 410 | .bd_ram_ofs = 0x2000, |
| 411 | .mac_control = (1 << 5), |
| 412 | .control = cpsw_control, |
| 413 | .host_port_num = 0, |
| 414 | .version = CPSW_CTRL_VERSION_2, |
| 415 | }; |
| 416 | #endif |
| 417 | |
Simon Glass | e5cd9a4 | 2021-07-10 21:14:26 -0600 | [diff] [blame] | 418 | #if ((defined(CONFIG_SPL_ETH) || defined(CONFIG_SPL_USB_ETHER)) \ |
Yegor Yefremov | fa8b71b | 2015-05-29 19:27:29 +0200 | [diff] [blame] | 419 | && defined(CONFIG_SPL_BUILD)) || \ |
| 420 | ((defined(CONFIG_DRIVER_TI_CPSW) || \ |
Paul Kocialkowski | f34dfcb | 2015-08-04 17:04:06 +0200 | [diff] [blame] | 421 | defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)) && \ |
Yegor Yefremov | fa8b71b | 2015-05-29 19:27:29 +0200 | [diff] [blame] | 422 | !defined(CONFIG_SPL_BUILD)) |
Masahiro Yamada | f7ed78b | 2020-06-26 15:13:33 +0900 | [diff] [blame] | 423 | int board_eth_init(struct bd_info *bis) |
Yegor Yefremov | fa8b71b | 2015-05-29 19:27:29 +0200 | [diff] [blame] | 424 | { |
| 425 | int rv, n = 0; |
| 426 | uint8_t mac_addr[6]; |
| 427 | uint32_t mac_hi, mac_lo; |
Yegor Yefremov | fa8b71b | 2015-05-29 19:27:29 +0200 | [diff] [blame] | 428 | |
| 429 | /* |
| 430 | * Note here that we're using CPSW1 since that has a 1Gbit PHY while |
| 431 | * CSPW0 has a 100Mbit PHY. |
| 432 | * |
| 433 | * On product, CPSW1 maps to port labeled WAN. |
| 434 | */ |
| 435 | |
| 436 | /* try reading mac address from efuse */ |
| 437 | mac_lo = readl(&cdev->macid1l); |
| 438 | mac_hi = readl(&cdev->macid1h); |
| 439 | mac_addr[0] = mac_hi & 0xFF; |
| 440 | mac_addr[1] = (mac_hi & 0xFF00) >> 8; |
| 441 | mac_addr[2] = (mac_hi & 0xFF0000) >> 16; |
| 442 | mac_addr[3] = (mac_hi & 0xFF000000) >> 24; |
| 443 | mac_addr[4] = mac_lo & 0xFF; |
| 444 | mac_addr[5] = (mac_lo & 0xFF00) >> 8; |
| 445 | |
| 446 | #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ |
Simon Glass | e5cd9a4 | 2021-07-10 21:14:26 -0600 | [diff] [blame] | 447 | (defined(CONFIG_SPL_ETH) && defined(CONFIG_SPL_BUILD)) |
Simon Glass | 64b723f | 2017-08-03 12:22:12 -0600 | [diff] [blame] | 448 | if (!env_get("ethaddr")) { |
Yegor Yefremov | fa8b71b | 2015-05-29 19:27:29 +0200 | [diff] [blame] | 449 | printf("<ethaddr> not set. Validating first E-fuse MAC\n"); |
| 450 | |
| 451 | if (is_valid_ethaddr(mac_addr)) |
Simon Glass | 8551d55 | 2017-08-03 12:22:11 -0600 | [diff] [blame] | 452 | eth_env_set_enetaddr("ethaddr", mac_addr); |
Yegor Yefremov | fa8b71b | 2015-05-29 19:27:29 +0200 | [diff] [blame] | 453 | } |
| 454 | |
| 455 | #ifdef CONFIG_DRIVER_TI_CPSW |
| 456 | writel((GMII1_SEL_RMII | GMII2_SEL_RGMII | RGMII2_IDMODE), &cdev->miisel); |
| 457 | cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII; |
| 458 | rv = cpsw_register(&cpsw_data); |
| 459 | if (rv < 0) |
| 460 | printf("Error %d registering CPSW switch\n", rv); |
| 461 | else |
| 462 | n += rv; |
| 463 | #endif |
| 464 | |
| 465 | /* |
| 466 | * |
| 467 | * CPSW RGMII Internal Delay Mode is not supported in all PVT |
| 468 | * operating points. So we must set the TX clock delay feature |
| 469 | * in the AR8051 PHY. Since we only support a single ethernet |
| 470 | * device in U-Boot, we only do this for the first instance. |
| 471 | */ |
| 472 | #define AR8051_PHY_DEBUG_ADDR_REG 0x1d |
| 473 | #define AR8051_PHY_DEBUG_DATA_REG 0x1e |
| 474 | #define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5 |
| 475 | #define AR8051_RGMII_TX_CLK_DLY 0x100 |
| 476 | const char *devname; |
| 477 | devname = miiphy_get_current_dev(); |
| 478 | |
| 479 | miiphy_write(devname, 0x7, AR8051_PHY_DEBUG_ADDR_REG, |
| 480 | AR8051_DEBUG_RGMII_CLK_DLY_REG); |
| 481 | miiphy_write(devname, 0x7, AR8051_PHY_DEBUG_DATA_REG, |
| 482 | AR8051_RGMII_TX_CLK_DLY); |
| 483 | #endif |
| 484 | return n; |
| 485 | } |
| 486 | #endif |