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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
wdenk0157ced2002-10-21 17:04:47 +00002/*
Wolfgang Denkf710efd2010-07-24 20:22:02 +02003 * (C) Copyright 2002-2010
wdenk0157ced2002-10-21 17:04:47 +00004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
wdenk0157ced2002-10-21 17:04:47 +00005 */
6
7#ifndef __ASM_GBL_DATA_H
8#define __ASM_GBL_DATA_H
Simon Glass3ac47d72012-12-13 20:48:30 +00009
Simon Glass3ba929a2020-10-30 21:38:53 -060010#include <asm/types.h>
11#include <linux/types.h>
12
Simon Glass3ac47d72012-12-13 20:48:30 +000013/* Architecture-specific global data */
14struct arch_global_data {
Yangbo Lu73340382019-06-21 11:42:28 +080015#if defined(CONFIG_FSL_ESDHC) || defined(CONFIG_FSL_ESDHC_IMX)
Simon Glass9e247d12012-12-13 20:49:05 +000016 u32 sdhc_clk;
17#endif
Zhao Qiang5ad93952014-09-25 13:52:25 +080018
Yangbo Lu0fa68762019-12-19 18:59:28 +080019#if defined(CONFIG_FSL_ESDHC)
20 u32 sdhc_per_clk;
21#endif
22
Zhao Qiang5ad93952014-09-25 13:52:25 +080023#if defined(CONFIG_U_QE)
24 u32 qe_clk;
25 u32 brg_clk;
26 uint mp_alloc_base;
27 uint mp_alloc_top;
28#endif /* CONFIG_U_QE */
29
Simon Glasse61accc2012-12-13 20:48:31 +000030#ifdef CONFIG_AT91FAMILY
31 /* "static data" needed by at91's clock.c */
32 unsigned long cpu_clk_rate_hz;
33 unsigned long main_clk_rate_hz;
34 unsigned long mck_rate_hz;
35 unsigned long plla_rate_hz;
36 unsigned long pllb_rate_hz;
37 unsigned long at91_pllb_usb_init;
38#endif
Simon Glass6ed6e032012-12-13 20:48:32 +000039 /* "static data" needed by most of timer.c on ARM platforms */
40 unsigned long timer_rate_hz;
Peng Fanf2d397b2017-05-09 10:32:02 +080041 unsigned int tbu;
42 unsigned int tbl;
Simon Glassa848da52012-12-13 20:48:35 +000043 unsigned long lastinc;
Simon Glass9cbe003a2012-12-13 20:48:36 +000044 unsigned long long timer_reset_value;
Trevor Woerner43ec7e02019-05-03 09:41:00 -040045#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
Simon Glass6b4ee152012-12-13 20:48:39 +000046 unsigned long tlb_addr;
Alexander Grafe317fe82016-03-04 01:09:47 +010047 unsigned long tlb_size;
Alexander Grafce0a64e2016-03-04 01:09:54 +010048#if defined(CONFIG_ARM64)
Alexander Grafe317fe82016-03-04 01:09:47 +010049 unsigned long tlb_fillptr;
50 unsigned long tlb_emerg;
Sergey Temerkhanov78eaa492015-10-14 09:55:45 -070051#endif
Simon Glass6b4ee152012-12-13 20:48:39 +000052#endif
York Sun1ef95cc2016-06-24 16:46:18 -070053#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
54#define MEM_RESERVE_SECURE_SECURED 0x1
55#define MEM_RESERVE_SECURE_MAINTAINED 0x2
56#define MEM_RESERVE_SECURE_ADDR_MASK (~0x3)
57 /*
58 * Secure memory addr
59 * This variable needs maintenance if the RAM base is not zero,
60 * or if RAM splits into non-consecutive banks. It also has a
61 * flag indicating the secure memory is marked as secure by MMU.
62 * Flags used: 0x1 secured
63 * 0x2 maintained
64 */
65 phys_addr_t secure_ram;
York Sunf84f81e2016-06-24 16:46:19 -070066 unsigned long tlb_allocated;
York Sun1ef95cc2016-06-24 16:46:18 -070067#endif
York Sund6964b32017-03-06 09:02:24 -080068#ifdef CONFIG_RESV_RAM
69 /*
70 * Reserved RAM for memory resident, eg. Management Complex (MC)
71 * driver which continues to run after U-Boot exits.
72 */
73 phys_addr_t resv_ram;
74#endif
SRICHARAN R4af19882013-04-24 00:41:23 +000075
Masahiro Yamada6e1288c2017-04-25 13:10:11 +090076#ifdef CONFIG_ARCH_OMAP2PLUS
Paul Kocialkowskid5b76242015-07-15 16:02:19 +020077 u32 omap_boot_device;
78 u32 omap_boot_mode;
79 u8 omap_ch_flags;
SRICHARAN R4af19882013-04-24 00:41:23 +000080#endif
Prabhakar Kushwaha122bcfd2015-11-09 16:42:07 +053081#if defined(CONFIG_FSL_LSCH3) && defined(CONFIG_SYS_FSL_HAS_DP_DDR)
York Sun1ecab782015-01-06 13:18:49 -080082 unsigned long mem2_clk;
83#endif
Peng Fanf17a0ce2018-10-18 14:28:10 +020084
85#ifdef CONFIG_ARCH_IMX8
86 struct udevice *scu_dev;
87#endif
Simon Glass3ac47d72012-12-13 20:48:30 +000088};
89
Simon Glass6878cd12012-12-13 20:49:14 +000090#include <asm-generic/global_data.h>
wdenk0157ced2002-10-21 17:04:47 +000091
Jeroen Hofstee43614d12014-07-30 21:54:52 +020092#ifdef __clang__
93
94#define DECLARE_GLOBAL_DATA_PTR
95#define gd get_gd()
96
97static inline gd_t *get_gd(void)
98{
99 gd_t *gd_ptr;
100
101#ifdef CONFIG_ARM64
Jeroen Hofstee43614d12014-07-30 21:54:52 +0200102 __asm__ volatile("mov %0, x18\n" : "=r" (gd_ptr));
103#else
104 __asm__ volatile("mov %0, r9\n" : "=r" (gd_ptr));
105#endif
106
107 return gd_ptr;
108}
109
110#else
111
David Feng85fd5f12013-12-14 11:47:35 +0800112#ifdef CONFIG_ARM64
113#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("x18")
114#else
115#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r9")
116#endif
Jeroen Hofstee43614d12014-07-30 21:54:52 +0200117#endif
wdenk0157ced2002-10-21 17:04:47 +0000118
Heinrich Schuchardt1a3732c2020-05-27 01:58:30 +0200119static inline void set_gd(volatile gd_t *gd_ptr)
120{
121#ifdef CONFIG_ARM64
122 __asm__ volatile("ldr x18, %0\n" : : "m"(gd_ptr));
123#else
124 __asm__ volatile("ldr r9, %0\n" : : "m"(gd_ptr));
125#endif
126}
127
wdenk0157ced2002-10-21 17:04:47 +0000128#endif /* __ASM_GBL_DATA_H */