Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Philipp Tomsich | 3015e04 | 2016-10-28 18:21:29 +0800 | [diff] [blame] | 2 | /* |
| 3 | * GTBUS initialisation for sun9i |
| 4 | * |
| 5 | * (C) Copyright 2016 Theobroma Systems Design und Consulting GmbH |
| 6 | * Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
Philipp Tomsich | 3015e04 | 2016-10-28 18:21:29 +0800 | [diff] [blame] | 7 | */ |
| 8 | |
Philipp Tomsich | 3015e04 | 2016-10-28 18:21:29 +0800 | [diff] [blame] | 9 | #include <asm/io.h> |
Andre Przywara | e42015b | 2022-07-03 00:14:24 +0100 | [diff] [blame] | 10 | #include <asm/arch/cpu.h> |
Philipp Tomsich | 3015e04 | 2016-10-28 18:21:29 +0800 | [diff] [blame] | 11 | #include <asm/arch/gtbus_sun9i.h> |
| 12 | #include <asm/arch/sys_proto.h> |
| 13 | |
| 14 | #ifdef CONFIG_SPL_BUILD |
| 15 | |
| 16 | void gtbus_init(void) |
| 17 | { |
| 18 | struct sunxi_gtbus_reg * const gtbus = |
| 19 | (struct sunxi_gtbus_reg *)SUNXI_GTBUS_BASE; |
| 20 | |
| 21 | /* |
| 22 | * We use the same setting that Allwinner used in Boot0 for now. |
| 23 | * It may be advantageous to adjust these for various workloads |
| 24 | * (e.g. headless use cases that focus on IO throughput). |
| 25 | */ |
| 26 | writel((GT_PRIO_HIGH << GT_PORT_FE0) | |
| 27 | (GT_PRIO_HIGH << GT_PORT_BE1) | |
| 28 | (GT_PRIO_HIGH << GT_PORT_BE2) | |
| 29 | (GT_PRIO_HIGH << GT_PORT_IEP0) | |
| 30 | (GT_PRIO_HIGH << GT_PORT_FE1) | |
| 31 | (GT_PRIO_HIGH << GT_PORT_BE0) | |
| 32 | (GT_PRIO_HIGH << GT_PORT_FE2) | |
| 33 | (GT_PRIO_HIGH << GT_PORT_IEP1), |
| 34 | >bus->mst_read_prio_cfg[0]); |
| 35 | |
| 36 | writel(GP_MST_CFG_DEFAULT, >bus->mst_cfg[GT_PORT_FE0]); |
| 37 | writel(GP_MST_CFG_DEFAULT, >bus->mst_cfg[GT_PORT_FE0]); |
| 38 | writel(GP_MST_CFG_DEFAULT, >bus->mst_cfg[GT_PORT_BE1]); |
| 39 | writel(GP_MST_CFG_DEFAULT, >bus->mst_cfg[GT_PORT_BE2]); |
| 40 | writel(GP_MST_CFG_DEFAULT, >bus->mst_cfg[GT_PORT_IEP0]); |
| 41 | writel(GP_MST_CFG_DEFAULT, >bus->mst_cfg[GT_PORT_FE1]); |
| 42 | writel(GP_MST_CFG_DEFAULT, >bus->mst_cfg[GT_PORT_BE0]); |
| 43 | writel(GP_MST_CFG_DEFAULT, >bus->mst_cfg[GT_PORT_FE2]); |
| 44 | writel(GP_MST_CFG_DEFAULT, >bus->mst_cfg[GT_PORT_IEP1]); |
| 45 | } |
| 46 | |
| 47 | #endif |