commit 3015e044dd9a2c5d088ef903053f0b226f7aaeb0
author Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Fri Oct 28 18:21:29 2016 +0800
committer Hans de Goede <hdegoede@redhat.com> Sun Oct 30 11:38:04 2016 +0100
tree d00e4adeea0e0102946a9affc3b1ba327ff5d4c0
parent d36af1cf24cdab44dfd006de300251f46b80715e

sunxi: add gtbus-initialisation for sun9i

On sun9i, the GTBUS manages transaction priority and bandwidth
for multiple read ports when accessing DRAM. The initialisation
mirrors the settings from Allwinner's boot0 for now, even though
this may not be optimal for all applications (e.g. headless
systems might want to give priority to IO modules).

Adding a common callout to gtbus_init() from the SPL clock init
with a weakly defined implementation in sunxi/clock.c to fallback
to for platforms that don't require this.

[wens@csie.org: Moved gtbus_sun9i.c to arch/arm/mach-sunxi/; style cleanup]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

arch/arm/mach-sunxi/gtbus_sun9i.c

diff --git a/arch/arm/mach-sunxi/gtbus_sun9i.c b/arch/arm/mach-sunxi/gtbus_sun9i.c
new file mode 100644
index 0000000..c20d3c0
--- /dev/null
+++ b/arch/arm/mach-sunxi/gtbus_sun9i.c
@@ -0,0 +1,48 @@
+/*
+ * GTBUS initialisation for sun9i
+ *
+ * (C) Copyright 2016 Theobroma Systems Design und Consulting GmbH
+ *                    Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/gtbus_sun9i.h>
+#include <asm/arch/sys_proto.h>
+
+#ifdef CONFIG_SPL_BUILD
+
+void gtbus_init(void)
+{
+	struct sunxi_gtbus_reg * const gtbus =
+		(struct sunxi_gtbus_reg *)SUNXI_GTBUS_BASE;
+
+	/*
+	 * We use the same setting that Allwinner used in Boot0 for now.
+	 * It may be advantageous to adjust these for various workloads
+	 * (e.g. headless use cases that focus on IO throughput).
+	 */
+	writel((GT_PRIO_HIGH << GT_PORT_FE0) |
+	       (GT_PRIO_HIGH << GT_PORT_BE1) |
+	       (GT_PRIO_HIGH << GT_PORT_BE2) |
+	       (GT_PRIO_HIGH << GT_PORT_IEP0) |
+	       (GT_PRIO_HIGH << GT_PORT_FE1) |
+	       (GT_PRIO_HIGH << GT_PORT_BE0) |
+	       (GT_PRIO_HIGH << GT_PORT_FE2) |
+	       (GT_PRIO_HIGH << GT_PORT_IEP1),
+	       &gtbus->mst_read_prio_cfg[0]);
+
+	writel(GP_MST_CFG_DEFAULT, &gtbus->mst_cfg[GT_PORT_FE0]);
+	writel(GP_MST_CFG_DEFAULT, &gtbus->mst_cfg[GT_PORT_FE0]);
+	writel(GP_MST_CFG_DEFAULT, &gtbus->mst_cfg[GT_PORT_BE1]);
+	writel(GP_MST_CFG_DEFAULT, &gtbus->mst_cfg[GT_PORT_BE2]);
+	writel(GP_MST_CFG_DEFAULT, &gtbus->mst_cfg[GT_PORT_IEP0]);
+	writel(GP_MST_CFG_DEFAULT, &gtbus->mst_cfg[GT_PORT_FE1]);
+	writel(GP_MST_CFG_DEFAULT, &gtbus->mst_cfg[GT_PORT_BE0]);
+	writel(GP_MST_CFG_DEFAULT, &gtbus->mst_cfg[GT_PORT_FE2]);
+	writel(GP_MST_CFG_DEFAULT, &gtbus->mst_cfg[GT_PORT_IEP1]);
+}
+
+#endif