Blame - drivers/clk/Kconfig - filogic/uboot

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Masahiro Yamada	92b8c2f	2016-01-12 16:36:38 +0900	[diff] [blame]	1	menu "Clock"
				2
Simon Glass	36ad234	2015-06-23 15:39:15 -0600	[diff] [blame]	3	config CLK
				4	bool "Enable clock driver support"
				5	depends on DM
				6	help
				7	This allows drivers to be provided for clock generators, including
				8	oscillators and PLLs. Devices can use a common clock API to request
				9	a particular clock rate and check on available clocks. Clocks can
				10	feed into other clocks in a tree structure, with multiplexers to
				11	choose the source for each clock.
				12
Masahiro Yamada	b16de45	2015-08-12 07:31:46 +0900	[diff] [blame]	13	config SPL_CLK
Simon Glass	36ad234	2015-06-23 15:39:15 -0600	[diff] [blame]	14	bool "Enable clock support in SPL"
Wenyou Yang	e4cf413	2017-07-31 15:21:57 +0800	[diff] [blame]	15	depends on CLK && SPL && SPL_DM
Simon Glass	36ad234	2015-06-23 15:39:15 -0600	[diff] [blame]	16	help
				17	The clock subsystem adds a small amount of overhead to the image.
				18	If this is acceptable and you have a need to use clock drivers in
				19	SPL, enable this option. It might provide a cleaner interface to
				20	setting up clocks within SPL, and allows the same drivers to be
				21	used as U-Boot proper.
Masahiro Yamada	92b8c2f	2016-01-12 16:36:38 +0900	[diff] [blame]	22
Philipp Tomsich	592c3db	2017-06-29 01:45:01 +0200	[diff] [blame]	23	config TPL_CLK
				24	bool "Enable clock support in TPL"
				25	depends on CLK && TPL_DM
				26	help
				27	The clock subsystem adds a small amount of overhead to the image.
				28	If this is acceptable and you have a need to use clock drivers in
				29	SPL, enable this option. It might provide a cleaner interface to
				30	setting up clocks within TPL, and allows the same drivers to be
				31	used as U-Boot proper.
				32
Álvaro Fernández Rojas	c35611c	2017-05-07 20:13:01 +0200	[diff] [blame]	33	config CLK_BCM6345
				34	bool "Clock controller driver for BCM6345"
				35	depends on CLK && ARCH_BMIPS
				36	default y
				37	help
				38	This clock driver adds support for enabling and disabling peripheral
				39	clocks on BCM6345 SoCs. HW has no rate changing capabilities.
				40
Paul Burton	0399f44	2016-09-08 07:47:38 +0100	[diff] [blame]	41	config CLK_BOSTON
				42	def_bool y if TARGET_BOSTON
				43	depends on CLK
				44	select REGMAP
				45	select SYSCON
				46	help
				47	Enable this to support the clocks
				48
Patrice Chotard	d4f2d20	2017-11-15 13:14:48 +0100	[diff] [blame]	49	config CLK_STM32F
				50	bool "Enable clock driver support for STM32F family"
				51	depends on CLK && (STM32F7 \|\| STM32F4)
				52	default y
				53	help
				54	This clock driver adds support for RCC clock management
				55	for STM32F4 and STM32F7 SoCs.
				56
Andreas Dannenberg	1530e35	2018-08-27 15:57:43 +0530	[diff] [blame^]	57	config CLK_TI_SCI
				58	bool "TI System Control Interface (TI SCI) clock driver"
				59	depends on CLK && TI_SCI_PROTOCOL && OF_CONTROL
				60	help
				61	This enables the clock driver support over TI System Control Interface
				62	available on some new TI's SoCs. If you wish to use clock resources
				63	managed by the TI System Controller, say Y here. Otherwise, say N.
				64
Eugeniy Paltsev	7e1fb09	2017-12-10 21:20:08 +0300	[diff] [blame]	65	config CLK_HSDK
				66	bool "Enable cgu clock driver for HSDK"
				67	depends on CLK
				68	help
				69	Enable this to support the cgu clocks on Synopsys ARC HSDK
				70
Stefan Herbrechtsmeier	f1f88c9	2017-01-17 16:27:29 +0100	[diff] [blame]	71	config CLK_ZYNQ
				72	bool "Enable clock driver support for Zynq"
				73	depends on CLK && ARCH_ZYNQ
				74	default y
				75	help
				76	This clock driver adds support for clock realted settings for
				77	Zynq platform.
				78
Siva Durga Prasad Paladugu	468b55f	2016-11-15 16:15:41 +0530	[diff] [blame]	79	config CLK_ZYNQMP
				80	bool "Enable clock driver support for ZynqMP"
				81	depends on ARCH_ZYNQMP
				82	help
				83	This clock driver adds support for clock realted settings for
				84	ZynqMP platform.
				85
Patrick Delaunay	e6ab627	2018-03-12 10:46:15 +0100	[diff] [blame]	86	config CLK_STM32MP1
				87	bool "Enable RCC clock driver for STM32MP1"
				88	depends on ARCH_STM32MP && CLK
				89	default y
				90	help
				91	Enable the STM32 clock (RCC) driver. Enable support for
				92	manipulating STM32MP1's on-SoC clocks.
				93
Wenyou Yang	8c772bd	2016-07-20 17:55:12 +0800	[diff] [blame]	94	source "drivers/clk/at91/Kconfig"
Jagan Teki	9d2787c	2018-07-30 18:26:18 +0530	[diff] [blame]	95	source "drivers/clk/exynos/Kconfig"
Marek Behún	61d74e8	2018-04-24 17:21:25 +0200	[diff] [blame]	96	source "drivers/clk/mvebu/Kconfig"
Manivannan Sadhasivam	91a8513	2018-06-14 23:38:35 +0530	[diff] [blame]	97	source "drivers/clk/owl/Kconfig"
Jagan Teki	9d2787c	2018-07-30 18:26:18 +0530	[diff] [blame]	98	source "drivers/clk/renesas/Kconfig"
				99	source "drivers/clk/tegra/Kconfig"
				100	source "drivers/clk/uniphier/Kconfig"
Masahiro Yamada	e4dfb05	2016-02-02 21:11:32 +0900	[diff] [blame]	101
Mario Six	a3c0706	2018-04-27 14:53:15 +0200	[diff] [blame]	102	config ICS8N3QV01
				103	bool "Enable ICS8N3QV01 VCXO driver"
				104	depends on CLK
				105	help
				106	Support for the ICS8N3QV01 Quad-Frequency VCXO (Voltage-Controlled
				107	Crystal Oscillator). The output frequency can be programmed via an
				108	I2C interface.
				109
Masahiro Yamada	92b8c2f	2016-01-12 16:36:38 +0900	[diff] [blame]	110	endmenu