Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
wdenk | bb1b826 | 2003-03-27 12:09:35 +0000 | [diff] [blame] | 2 | /* |
| 3 | * Startup Code for MIPS32 CPU-core |
| 4 | * |
| 5 | * Copyright (c) 2003 Wolfgang Denk <wd@denx.de> |
wdenk | bb1b826 | 2003-03-27 12:09:35 +0000 | [diff] [blame] | 6 | */ |
| 7 | |
Wolfgang Denk | 0191e47 | 2010-10-26 14:34:52 +0200 | [diff] [blame] | 8 | #include <asm-offsets.h> |
wdenk | bb1b826 | 2003-03-27 12:09:35 +0000 | [diff] [blame] | 9 | #include <config.h> |
Paul Burton | ce14da2 | 2015-01-29 10:04:08 +0000 | [diff] [blame] | 10 | #include <asm/asm.h> |
wdenk | bb1b826 | 2003-03-27 12:09:35 +0000 | [diff] [blame] | 11 | #include <asm/regdef.h> |
| 12 | #include <asm/mipsregs.h> |
| 13 | |
Daniel Schwierzeck | 2814459 | 2015-01-18 22:18:38 +0100 | [diff] [blame] | 14 | #ifndef CONFIG_SYS_INIT_SP_ADDR |
| 15 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \ |
| 16 | CONFIG_SYS_INIT_SP_OFFSET) |
| 17 | #endif |
| 18 | |
Paul Burton | cb2ab2f | 2015-01-29 10:04:09 +0000 | [diff] [blame] | 19 | #ifdef CONFIG_32BIT |
| 20 | # define MIPS_RELOC 3 |
Paul Burton | debf0e0 | 2015-01-29 10:04:10 +0000 | [diff] [blame] | 21 | # define STATUS_SET 0 |
Paul Burton | cb2ab2f | 2015-01-29 10:04:09 +0000 | [diff] [blame] | 22 | #endif |
| 23 | |
| 24 | #ifdef CONFIG_64BIT |
| 25 | # ifdef CONFIG_SYS_LITTLE_ENDIAN |
| 26 | # define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \ |
| 27 | (((r_type) << 24) | ((r_type2) << 16) | ((r_type3) << 8) | (ssym)) |
| 28 | # else |
| 29 | # define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \ |
| 30 | ((r_type) | ((r_type2) << 8) | ((r_type3) << 16) | (ssym) << 24) |
| 31 | # endif |
| 32 | # define MIPS_RELOC MIPS64_R_INFO(0x00, 0x00, 0x12, 0x03) |
Paul Burton | debf0e0 | 2015-01-29 10:04:10 +0000 | [diff] [blame] | 33 | # define STATUS_SET ST0_KX |
Paul Burton | cb2ab2f | 2015-01-29 10:04:09 +0000 | [diff] [blame] | 34 | #endif |
| 35 | |
wdenk | bb1b826 | 2003-03-27 12:09:35 +0000 | [diff] [blame] | 36 | .set noreorder |
| 37 | |
Daniel Schwierzeck | ecf0d79 | 2016-02-08 00:37:59 +0100 | [diff] [blame] | 38 | .macro init_wr sel |
| 39 | MTC0 zero, CP0_WATCHLO,\sel |
| 40 | mtc0 t1, CP0_WATCHHI,\sel |
| 41 | mfc0 t0, CP0_WATCHHI,\sel |
| 42 | bgez t0, wr_done |
| 43 | nop |
| 44 | .endm |
| 45 | |
Daniel Schwierzeck | 8b2fd07 | 2016-02-07 19:39:58 +0100 | [diff] [blame] | 46 | .macro uhi_mips_exception |
| 47 | move k0, t9 # preserve t9 in k0 |
| 48 | move k1, a0 # preserve a0 in k1 |
| 49 | li t9, 15 # UHI exception operation |
| 50 | li a0, 0 # Use hard register context |
| 51 | sdbbp 1 # Invoke UHI operation |
| 52 | .endm |
| 53 | |
Daniel Schwierzeck | 993a122 | 2016-09-25 18:36:38 +0200 | [diff] [blame] | 54 | .macro setup_stack_gd |
| 55 | li t0, -16 |
| 56 | PTR_LI t1, CONFIG_SYS_INIT_SP_ADDR |
| 57 | and sp, t1, t0 # force 16 byte alignment |
| 58 | PTR_SUBU \ |
| 59 | sp, sp, GD_SIZE # reserve space for gd |
| 60 | and sp, sp, t0 # force 16 byte alignment |
| 61 | move k0, sp # save gd pointer |
Andy Yan | 984c10d | 2017-07-24 17:45:27 +0800 | [diff] [blame] | 62 | #if CONFIG_VAL(SYS_MALLOC_F_LEN) |
| 63 | li t2, CONFIG_VAL(SYS_MALLOC_F_LEN) |
Daniel Schwierzeck | 993a122 | 2016-09-25 18:36:38 +0200 | [diff] [blame] | 64 | PTR_SUBU \ |
| 65 | sp, sp, t2 # reserve space for early malloc |
| 66 | and sp, sp, t0 # force 16 byte alignment |
| 67 | #endif |
| 68 | move fp, sp |
| 69 | |
| 70 | /* Clear gd */ |
| 71 | move t0, k0 |
| 72 | 1: |
| 73 | PTR_S zero, 0(t0) |
| 74 | blt t0, t1, 1b |
| 75 | PTR_ADDIU t0, PTRSIZE |
| 76 | |
Andy Yan | 984c10d | 2017-07-24 17:45:27 +0800 | [diff] [blame] | 77 | #if CONFIG_VAL(SYS_MALLOC_F_LEN) |
Daniel Schwierzeck | 993a122 | 2016-09-25 18:36:38 +0200 | [diff] [blame] | 78 | PTR_S sp, GD_MALLOC_BASE(k0) # gd->malloc_base offset |
| 79 | #endif |
| 80 | .endm |
| 81 | |
Daniel Schwierzeck | 7509b57 | 2015-12-19 20:20:45 +0100 | [diff] [blame] | 82 | ENTRY(_start) |
Bin Meng | 7557405 | 2016-02-05 19:30:11 -0800 | [diff] [blame] | 83 | /* U-Boot entry point */ |
Daniel Schwierzeck | ec44316 | 2013-02-12 22:22:12 +0100 | [diff] [blame] | 84 | b reset |
Daniel Schwierzeck | ecf0d79 | 2016-02-08 00:37:59 +0100 | [diff] [blame] | 85 | mtc0 zero, CP0_COUNT # clear cp0 count for most accurate boot timing |
Daniel Schwierzeck | ec44316 | 2013-02-12 22:22:12 +0100 | [diff] [blame] | 86 | |
Gabor Juhos | b6be59a | 2013-05-22 03:57:46 +0000 | [diff] [blame] | 87 | #if defined(CONFIG_SYS_XWAY_EBU_BOOTCFG) |
Daniel Schwierzeck | 6ff8ae0 | 2011-07-27 13:22:37 +0200 | [diff] [blame] | 88 | /* |
| 89 | * Almost all Lantiq XWAY SoC devices have an external bus unit (EBU) to |
| 90 | * access external NOR flashes. If the board boots from NOR flash the |
| 91 | * internal BootROM does a blind read at address 0xB0000010 to read the |
| 92 | * initial configuration for that EBU in order to access the flash |
| 93 | * device with correct parameters. This config option is board-specific. |
| 94 | */ |
Daniel Schwierzeck | 754cd05 | 2016-02-14 18:52:57 +0100 | [diff] [blame] | 95 | .org 0x10 |
Daniel Schwierzeck | 6ff8ae0 | 2011-07-27 13:22:37 +0200 | [diff] [blame] | 96 | .word CONFIG_SYS_XWAY_EBU_BOOTCFG |
Daniel Schwierzeck | ec44316 | 2013-02-12 22:22:12 +0100 | [diff] [blame] | 97 | .word 0x0 |
Daniel Schwierzeck | 754cd05 | 2016-02-14 18:52:57 +0100 | [diff] [blame] | 98 | #endif |
| 99 | #if defined(CONFIG_MALTA) |
Gabor Juhos | b6be59a | 2013-05-22 03:57:46 +0000 | [diff] [blame] | 100 | /* |
| 101 | * Linux expects the Board ID here. |
| 102 | */ |
Daniel Schwierzeck | 754cd05 | 2016-02-14 18:52:57 +0100 | [diff] [blame] | 103 | .org 0x10 |
Gabor Juhos | b6be59a | 2013-05-22 03:57:46 +0000 | [diff] [blame] | 104 | .word 0x00000420 # 0x420 (Malta Board with CoreLV) |
| 105 | .word 0x00000000 |
wdenk | bb1b826 | 2003-03-27 12:09:35 +0000 | [diff] [blame] | 106 | #endif |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 107 | |
Daniel Schwierzeck | 754cd05 | 2016-02-14 18:52:57 +0100 | [diff] [blame] | 108 | #if defined(CONFIG_ROM_EXCEPTION_VECTORS) |
Daniel Schwierzeck | 8b2fd07 | 2016-02-07 19:39:58 +0100 | [diff] [blame] | 109 | /* |
| 110 | * Exception vector entry points. When running from ROM, an exception |
| 111 | * cannot be handled. Halt execution and transfer control to debugger, |
| 112 | * if one is attached. |
| 113 | */ |
Daniel Schwierzeck | ec44316 | 2013-02-12 22:22:12 +0100 | [diff] [blame] | 114 | .org 0x200 |
| 115 | /* TLB refill, 32 bit task */ |
Daniel Schwierzeck | 8b2fd07 | 2016-02-07 19:39:58 +0100 | [diff] [blame] | 116 | uhi_mips_exception |
Daniel Schwierzeck | ec44316 | 2013-02-12 22:22:12 +0100 | [diff] [blame] | 117 | |
| 118 | .org 0x280 |
| 119 | /* XTLB refill, 64 bit task */ |
Daniel Schwierzeck | 8b2fd07 | 2016-02-07 19:39:58 +0100 | [diff] [blame] | 120 | uhi_mips_exception |
Daniel Schwierzeck | ec44316 | 2013-02-12 22:22:12 +0100 | [diff] [blame] | 121 | |
| 122 | .org 0x300 |
| 123 | /* Cache error exception */ |
Daniel Schwierzeck | 8b2fd07 | 2016-02-07 19:39:58 +0100 | [diff] [blame] | 124 | uhi_mips_exception |
Daniel Schwierzeck | ec44316 | 2013-02-12 22:22:12 +0100 | [diff] [blame] | 125 | |
| 126 | .org 0x380 |
| 127 | /* General exception */ |
Daniel Schwierzeck | 8b2fd07 | 2016-02-07 19:39:58 +0100 | [diff] [blame] | 128 | uhi_mips_exception |
Daniel Schwierzeck | ec44316 | 2013-02-12 22:22:12 +0100 | [diff] [blame] | 129 | |
| 130 | .org 0x400 |
| 131 | /* Catch interrupt exceptions */ |
Daniel Schwierzeck | 8b2fd07 | 2016-02-07 19:39:58 +0100 | [diff] [blame] | 132 | uhi_mips_exception |
Daniel Schwierzeck | ec44316 | 2013-02-12 22:22:12 +0100 | [diff] [blame] | 133 | |
| 134 | .org 0x480 |
| 135 | /* EJTAG debug exception */ |
| 136 | 1: b 1b |
| 137 | nop |
| 138 | |
Daniel Schwierzeck | 754cd05 | 2016-02-14 18:52:57 +0100 | [diff] [blame] | 139 | .org 0x500 |
| 140 | #endif |
| 141 | |
wdenk | bb1b826 | 2003-03-27 12:09:35 +0000 | [diff] [blame] | 142 | reset: |
Paul Burton | fcdc1fb | 2016-09-21 14:59:54 +0100 | [diff] [blame] | 143 | #if __mips_isa_rev >= 6 |
| 144 | mfc0 t0, CP0_CONFIG, 5 |
| 145 | and t0, t0, MIPS_CONF5_VP |
| 146 | beqz t0, 1f |
| 147 | nop |
| 148 | |
| 149 | b 2f |
| 150 | mfc0 t0, CP0_GLOBALNUMBER |
| 151 | #endif |
| 152 | |
Álvaro Fernández Rojas | 98a97a8 | 2017-04-25 00:39:20 +0200 | [diff] [blame] | 153 | #ifdef CONFIG_ARCH_BMIPS |
| 154 | 1: mfc0 t0, CP0_DIAGNOSTIC, 3 |
| 155 | and t0, t0, (1 << 31) |
| 156 | #else |
Paul Burton | fcdc1fb | 2016-09-21 14:59:54 +0100 | [diff] [blame] | 157 | 1: mfc0 t0, CP0_EBASE |
| 158 | and t0, t0, EBASE_CPUNUM |
Álvaro Fernández Rojas | 98a97a8 | 2017-04-25 00:39:20 +0200 | [diff] [blame] | 159 | #endif |
Paul Burton | fcdc1fb | 2016-09-21 14:59:54 +0100 | [diff] [blame] | 160 | |
| 161 | /* Hang if this isn't the first CPU in the system */ |
| 162 | 2: beqz t0, 4f |
| 163 | nop |
| 164 | 3: wait |
| 165 | b 3b |
| 166 | nop |
wdenk | bb1b826 | 2003-03-27 12:09:35 +0000 | [diff] [blame] | 167 | |
Daniel Schwierzeck | ecf0d79 | 2016-02-08 00:37:59 +0100 | [diff] [blame] | 168 | /* Init CP0 Status */ |
| 169 | 4: mfc0 t0, CP0_STATUS |
| 170 | and t0, ST0_IMPL |
| 171 | or t0, ST0_BEV | ST0_ERL | STATUS_SET |
| 172 | mtc0 t0, CP0_STATUS |
| 173 | |
| 174 | /* |
| 175 | * Check whether CP0 Config1 is implemented. If not continue |
| 176 | * with legacy Watch register initialization. |
| 177 | */ |
| 178 | mfc0 t0, CP0_CONFIG |
| 179 | bgez t0, wr_legacy |
| 180 | nop |
| 181 | |
| 182 | /* |
| 183 | * Check WR bit in CP0 Config1 to determine if Watch registers |
| 184 | * are implemented. |
| 185 | */ |
| 186 | mfc0 t0, CP0_CONFIG, 1 |
| 187 | andi t0, (1 << 3) |
| 188 | beqz t0, wr_done |
| 189 | nop |
| 190 | |
| 191 | /* Clear Watch Status bits and disable watch exceptions */ |
| 192 | li t1, 0x7 # Clear I, R and W conditions |
| 193 | init_wr 0 |
| 194 | init_wr 1 |
| 195 | init_wr 2 |
| 196 | init_wr 3 |
| 197 | init_wr 4 |
| 198 | init_wr 5 |
| 199 | init_wr 6 |
| 200 | init_wr 7 |
| 201 | b wr_done |
| 202 | nop |
| 203 | |
| 204 | wr_legacy: |
| 205 | MTC0 zero, CP0_WATCHLO |
Daniel Schwierzeck | 7aa7164 | 2016-01-09 22:24:47 +0100 | [diff] [blame] | 206 | mtc0 zero, CP0_WATCHHI |
wdenk | bb1b826 | 2003-03-27 12:09:35 +0000 | [diff] [blame] | 207 | |
Daniel Schwierzeck | ecf0d79 | 2016-02-08 00:37:59 +0100 | [diff] [blame] | 208 | wr_done: |
| 209 | /* Clear WP, IV and SW interrupts */ |
Shinya Kuribayashi | 79727f8 | 2008-03-25 21:30:07 +0900 | [diff] [blame] | 210 | mtc0 zero, CP0_CAUSE |
| 211 | |
Daniel Schwierzeck | ecf0d79 | 2016-02-08 00:37:59 +0100 | [diff] [blame] | 212 | /* Clear timer interrupt (CP0_COUNT cleared on branch to 'reset') */ |
wdenk | bb1b826 | 2003-03-27 12:09:35 +0000 | [diff] [blame] | 213 | mtc0 zero, CP0_COMPARE |
| 214 | |
Shinya Kuribayashi | 6911d0a | 2011-05-07 00:18:13 +0900 | [diff] [blame] | 215 | #ifndef CONFIG_SKIP_LOWLEVEL_INIT |
Paul Burton | 4f5561c | 2016-09-21 11:18:50 +0100 | [diff] [blame] | 216 | mfc0 t0, CP0_CONFIG |
| 217 | and t0, t0, MIPS_CONF_IMPL |
| 218 | or t0, t0, CONF_CM_UNCACHED |
wdenk | bb1b826 | 2003-03-27 12:09:35 +0000 | [diff] [blame] | 219 | mtc0 t0, CP0_CONFIG |
Paul Burton | 82c9d89 | 2016-09-21 11:18:57 +0100 | [diff] [blame] | 220 | ehb |
Shinya Kuribayashi | 6911d0a | 2011-05-07 00:18:13 +0900 | [diff] [blame] | 221 | #endif |
wdenk | bb1b826 | 2003-03-27 12:09:35 +0000 | [diff] [blame] | 222 | |
Paul Burton | 79ac174 | 2016-09-21 11:18:53 +0100 | [diff] [blame] | 223 | #ifdef CONFIG_MIPS_CM |
| 224 | PTR_LA t9, mips_cm_map |
| 225 | jalr t9 |
| 226 | nop |
| 227 | #endif |
| 228 | |
Daniel Schwierzeck | 41dc35e | 2016-06-04 16:13:21 +0200 | [diff] [blame] | 229 | #ifdef CONFIG_MIPS_INIT_STACK_IN_SRAM |
| 230 | /* Set up initial stack and global data */ |
| 231 | setup_stack_gd |
Daniel Schwierzeck | fd32b13 | 2017-04-24 19:03:34 +0200 | [diff] [blame] | 232 | |
| 233 | # ifdef CONFIG_DEBUG_UART |
| 234 | /* Earliest point to set up debug uart */ |
| 235 | PTR_LA t9, debug_uart_init |
| 236 | jalr t9 |
| 237 | nop |
| 238 | # endif |
Daniel Schwierzeck | 41dc35e | 2016-06-04 16:13:21 +0200 | [diff] [blame] | 239 | #endif |
| 240 | |
Shinya Kuribayashi | 6911d0a | 2011-05-07 00:18:13 +0900 | [diff] [blame] | 241 | #ifndef CONFIG_SKIP_LOWLEVEL_INIT |
Paul Burton | 68b4c75 | 2016-09-21 11:18:51 +0100 | [diff] [blame] | 242 | # ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD |
Shinya Kuribayashi | 6911d0a | 2011-05-07 00:18:13 +0900 | [diff] [blame] | 243 | /* Initialize any external memory */ |
Paul Burton | ce14da2 | 2015-01-29 10:04:08 +0000 | [diff] [blame] | 244 | PTR_LA t9, lowlevel_init |
Shinya Kuribayashi | c7faac5 | 2007-10-27 15:27:06 +0900 | [diff] [blame] | 245 | jalr t9 |
Shinya Kuribayashi | 6911d0a | 2011-05-07 00:18:13 +0900 | [diff] [blame] | 246 | nop |
Paul Burton | 68b4c75 | 2016-09-21 11:18:51 +0100 | [diff] [blame] | 247 | # endif |
wdenk | bb1b826 | 2003-03-27 12:09:35 +0000 | [diff] [blame] | 248 | |
Shinya Kuribayashi | 6911d0a | 2011-05-07 00:18:13 +0900 | [diff] [blame] | 249 | /* Initialize caches... */ |
Paul Burton | ce14da2 | 2015-01-29 10:04:08 +0000 | [diff] [blame] | 250 | PTR_LA t9, mips_cache_reset |
Shinya Kuribayashi | c7faac5 | 2007-10-27 15:27:06 +0900 | [diff] [blame] | 251 | jalr t9 |
Shinya Kuribayashi | 6911d0a | 2011-05-07 00:18:13 +0900 | [diff] [blame] | 252 | nop |
Paul Burton | 68b4c75 | 2016-09-21 11:18:51 +0100 | [diff] [blame] | 253 | |
| 254 | # ifndef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD |
| 255 | /* Initialize any external memory */ |
| 256 | PTR_LA t9, lowlevel_init |
| 257 | jalr t9 |
| 258 | nop |
| 259 | # endif |
Shinya Kuribayashi | 6911d0a | 2011-05-07 00:18:13 +0900 | [diff] [blame] | 260 | #endif |
wdenk | bb1b826 | 2003-03-27 12:09:35 +0000 | [diff] [blame] | 261 | |
Daniel Schwierzeck | 41dc35e | 2016-06-04 16:13:21 +0200 | [diff] [blame] | 262 | #ifndef CONFIG_MIPS_INIT_STACK_IN_SRAM |
Daniel Schwierzeck | 993a122 | 2016-09-25 18:36:38 +0200 | [diff] [blame] | 263 | /* Set up initial stack and global data */ |
| 264 | setup_stack_gd |
Daniel Schwierzeck | fd32b13 | 2017-04-24 19:03:34 +0200 | [diff] [blame] | 265 | |
| 266 | # ifdef CONFIG_DEBUG_UART |
| 267 | /* Earliest point to set up debug uart */ |
| 268 | PTR_LA t9, debug_uart_init |
| 269 | jalr t9 |
| 270 | nop |
| 271 | # endif |
Daniel Schwierzeck | 41dc35e | 2016-06-04 16:13:21 +0200 | [diff] [blame] | 272 | #endif |
Daniel Schwierzeck | 7aa7164 | 2016-01-09 22:24:47 +0100 | [diff] [blame] | 273 | |
Purna Chandra Mandal | 5c8cdf4 | 2016-01-21 20:02:51 +0530 | [diff] [blame] | 274 | move a0, zero # a0 <-- boot_flags = 0 |
Paul Burton | ce14da2 | 2015-01-29 10:04:08 +0000 | [diff] [blame] | 275 | PTR_LA t9, board_init_f |
Daniel Schwierzeck | 8b2fd07 | 2016-02-07 19:39:58 +0100 | [diff] [blame] | 276 | |
Shinya Kuribayashi | 9dabea1 | 2008-04-17 23:35:13 +0900 | [diff] [blame] | 277 | jr t9 |
Daniel Schwierzeck | f224c1a | 2014-11-20 23:55:32 +0100 | [diff] [blame] | 278 | move ra, zero |
wdenk | bb1b826 | 2003-03-27 12:09:35 +0000 | [diff] [blame] | 279 | |
Daniel Schwierzeck | 7509b57 | 2015-12-19 20:20:45 +0100 | [diff] [blame] | 280 | END(_start) |