| commit | ecf0d79be2a178e5c4bc392f5bf2a0e32c213538 | [log] [tgz] |
|---|---|---|
| author | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | Mon Feb 08 00:37:59 2016 +0100 |
| committer | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | Wed Nov 30 16:11:46 2016 +0100 |
| tree | de9839a98dd41a56a6a93cf61230c6c0d3ec43ea | |
| parent | 8b2fd077705d01bea93e7e31d7cd68013ae3f40e [diff] |
MIPS: fix iand optimize setup of CP0 registers Clear cp0 status while preserving implementation specific bits. Set bits BEV and ERL as the arch specification requires after a reset or soft-reset exception. Extend and fix initialization of watch registers. Check if additional watch register sets are implemented and initialize them too. Initialize cp0 count as early as possible to get the most accurate boot timing. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>