blob: 3c007bb450893ff78c80174911e39887d42e33fc [file] [log] [blame]
Kever Yang34ead0f2019-07-09 22:05:55 +08001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * (C) Copyright 2019 Rockchip Electronics Co., Ltd
4 */
5
6#include <common.h>
7#include <debug_uart.h>
8#include <dm.h>
Simon Glassf11478f2019-12-28 10:45:07 -07009#include <hang.h>
Simon Glass97589732020-05-10 11:40:02 -060010#include <init.h>
Simon Glass0f2af882020-05-10 11:40:05 -060011#include <log.h>
Kever Yang34ead0f2019-07-09 22:05:55 +080012#include <ram.h>
13#include <spl.h>
14#include <version.h>
15#include <asm/io.h>
16#include <asm/arch-rockchip/bootrom.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060017#include <linux/bitops.h>
Kever Yang34ead0f2019-07-09 22:05:55 +080018
Pali Rohár6e1f0852021-08-02 15:18:38 +020019#if CONFIG_IS_ENABLED(BANNER_PRINT)
20#include <timestamp.h>
21#endif
22
Kever Yang34ead0f2019-07-09 22:05:55 +080023#define TIMER_LOAD_COUNT_L 0x00
24#define TIMER_LOAD_COUNT_H 0x04
25#define TIMER_CONTROL_REG 0x10
26#define TIMER_EN 0x1
27#define TIMER_FMODE BIT(0)
28#define TIMER_RMODE BIT(1)
29
30__weak void rockchip_stimer_init(void)
31{
32 /* If Timer already enabled, don't re-init it */
33 u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
34
35 if (reg & TIMER_EN)
36 return;
37
38#ifndef CONFIG_ARM64
39 asm volatile("mcr p15, 0, %0, c14, c0, 0"
40 : : "r"(COUNTER_FREQUENCY));
41#endif
42
43 writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
44 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE);
45 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4);
46 writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE +
47 TIMER_CONTROL_REG);
48}
49
50void board_init_f(ulong dummy)
51{
52 struct udevice *dev;
53 int ret;
54
Simon Glassf4d60392021-08-08 12:20:12 -060055#if defined(CONFIG_DEBUG_UART) && defined(CONFIG_TPL_SERIAL)
Kever Yang34ead0f2019-07-09 22:05:55 +080056 /*
57 * Debug UART can be used from here if required:
58 *
59 * debug_uart_init();
60 * printch('a');
61 * printhex8(0x1234);
62 * printascii("string");
63 */
64 debug_uart_init();
Chris Webb45dd8012019-07-19 14:23:55 +010065#ifdef CONFIG_TPL_BANNER_PRINT
Kever Yang34ead0f2019-07-09 22:05:55 +080066 printascii("\nU-Boot TPL " PLAIN_VERSION " (" U_BOOT_DATE " - " \
67 U_BOOT_TIME ")\n");
68#endif
Chris Webb45dd8012019-07-19 14:23:55 +010069#endif
Kever Yang34ead0f2019-07-09 22:05:55 +080070 ret = spl_early_init();
71 if (ret) {
72 debug("spl_early_init() failed: %d\n", ret);
73 hang();
74 }
75
76 /* Init secure timer */
77 rockchip_stimer_init();
78 /* Init ARM arch timer in arch/arm/cpu/ */
79 timer_init();
80
81 ret = uclass_get_device(UCLASS_RAM, 0, &dev);
82 if (ret) {
83 printf("DRAM init failed: %d\n", ret);
84 return;
85 }
86}
87
Peng Fanaa050c52019-08-07 06:40:53 +000088int board_return_to_bootrom(struct spl_image_info *spl_image,
89 struct spl_boot_device *bootdev)
Kever Yang34ead0f2019-07-09 22:05:55 +080090{
91 back_to_bootrom(BROM_BOOT_NEXTSTAGE);
Peng Fanaa050c52019-08-07 06:40:53 +000092
93 return 0;
Kever Yang34ead0f2019-07-09 22:05:55 +080094}
95
96u32 spl_boot_device(void)
97{
98 return BOOT_DEVICE_BOOTROM;
99}